EE 434 Lecture 13. Basic Semiconductor Processes Devices in Semiconductor Processes

Size: px
Start display at page:

Download "EE 434 Lecture 13. Basic Semiconductor Processes Devices in Semiconductor Processes"

Transcription

1 EE 434 Lecture 3 Basic Semiconductor Processes Devices in Semiconductor Processes

2 Quiz 9 The top view of a device fabricated in a bulk CMOS process is shown in the figure below a) Identify the device b) Sketch a cross-section along the AA section line A A Metal Poly Active p-select n-well Contact

3 And the number is

4 Quiz 9 Solution a) p-channel MOS Transistor A A

5 Review from Last Time Process Flow is a recipe for the process Shows what can and can not be made Gives insight into performance capabilities and limitations Designer has control only of top view Some masks may be automatically generated Geometric Description File (GDF) contains all information about a layout and serves as interface with foundry

6 C D Guard Rings and Bulk Attachment A A B B C D

7 Basic Devices and Device Models Resistor Diode Capacitor MOSFET BJT

8 Basic Devices and Device Models Resistor Diode Capacitor MOSFET BJT

9 Device Modeling Goal: Obtain a mathematical relationship between the port variables of a device.

10 Device Modeling Goal: Obtain a mathematical relationship between the port variables of a device. Without loss of generality, one terminal can be selected as a reference (this can be done in one of 4 ways!) I 4-Terminal Device I 2 I 3 V V 2 V 3 Thus modeling problem is that of determining mathematical relationship Between the six variables I, I 2, I 3, V, V 2, and V 3

11 Device Modeling Goal: Obtain a mathematical relationship between the port variables of a device. I 4-Terminal Device I 2 I 3 V V 2 V 3 Any 3 of the 6 variables {I, I 2, I 3, V, V 2, V 3 } can be selected as independent variables and the remaining 3 variables can be selected as dependent variables 6 3 6! = = 3!3! There are 20 ways this can be done Thus there are 4x20=80 different mathematical representations of a 4-terminal device and all predict identical performance!

12 Device Modeling Goal: Obtain a mathematical relationship between the port variables of a device. I 4-Terminal Device I 2 I 3 V V 2 V 3 By convention, will pick { V, V 2, V 3 } as the independent variables and {I, I 2, I 3 } as the dependent variables

13 Device Modeling Goal: Obtain a mathematical relationship between the port variables of a device. I 4-Terminal Device I 2 I 3 V V 2 V 3 Modeling Goal: Obtain f, f 2, and f 3 that sufficiently accurately characterize the device I I I = f = f = f ( V,V,V ) ( V,V,V ) 2 2 ( V ),V 2,V3 3 3

14 Device Modeling Goal: Obtain a mathematical relationship between the port variables of a device. I I I I I = f = f = f 2 3 = f = f ( V,V 2,V3 ) ( V,V 2,V3 ) ( V ),V 2,V3 2 ( V,V 2 ) ( V,V ) 2 I = f V ( ) }

15 Resistors Generally thin-film devices Almost any thin-film layer can be used as a resistor Diffused resistors Poly Resistors Metal Resistors Thin-film adders (SiCr or NiCr) Subject to process variations, gradient effects and local random variations Often temperature and voltage dependent Ambient temperature Local Heating Nonlinearities often a cause of distortion when used in circuits Trimming possible resistors Laser,links,switches

16 Resistor Model W d L V I Model: R = V I

17 Resistivity Volumetric measure of conduction capability of a material Area is A units : ohm cm L R ρ = AR L for homogeneous material, ρ A, R, L

18 Sheet Resistance W d L R RW R = ( for d << w, d << L ) units : ohms / L for homogeneous materials, R is independent of W, L, R

19 Relationship between ρ and R R = ρ = RW L AR L ρ = A W R = W d W A ρ = R W A = W R = d x d R Number of squares, N S, often used instead of L / W in determining resistance of film resistors R=R N S

20 Example W L R =?

21 Example L L = W N S W

22 Example R =?

23 Example R =? N S =8.4 R = R (8.4)

24 Corners in Film Resistors Corner Rule of Thumb:.55 squares for each corner

25 Example 2 Determine R if R = 00 Ω /

26 Example N S =7. R = (7.) R R = 70 Ω 2 3

27 Resistivity of Materials used in Semiconductor Processing Cu:.7E-6 Ωcm Al: 2.7E-4 Ωcm Gold: 2.4E-6 Ωcm Platinum: 3.0E-6 Ωcm n-si:.25 to 5 Ωcm intrinsic Si: 2.5E5 Ωcm SiO 2 : E4 Ωcm

28 Temperature Coefficients Used for indicating temperature sensitivity of resistors & capacitors For a resistor: TCR = R dr dt 6 0 op. temp ppm C This diff eqn can easily be solved if TCR is a constant R R ( T ) R( T ) 2 = e T 2 T 0 6 TCR ( ) ( ) ( ) T R T + T T TCR 0 Identical Expressions for Capacitors

29 Voltage Coefficients Used for indicating voltage sensitivity of resistors & capacitors For a resistor: VCR = R dr dv 6 0 ref voltage ppm This diff eqn can easily be solved if VCR is a constant R ( V ) R( V ) 2 = e V 2 V 0 6 VCR ( ) ( ) ( ) V R V + V V 2 6 R 2 V VCR 0 Identical Expressions for Capacitors

30 Temperature and Voltage Coefficients Temperature and voltage coefficients often quite large for diffused resistors Temperature and voltage coefficients often quite small for poly and metal resistors

31 End of Lecture 3

EE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes

EE 434 Lecture 12. Process Flow (wrap up) Device Modeling in Semiconductor Processes EE 434 Lecture 12 Process Flow (wrap up) Device Modeling in Semiconductor Processes Quiz 6 How have process engineers configured a process to assure that the thickness of the gate oxide for the p-channel

More information

EE 330 Lecture 12. Devices in Semiconductor Processes. Resistors Diodes

EE 330 Lecture 12. Devices in Semiconductor Processes. Resistors Diodes EE 330 Lecture 12 evices in Semiconductor Processes Resistors iodes Exam 1 Friday Feb 16 Students may bring 1 page of notes HW assignment of week of Feb 11 due on Wed Sfeb 14 at beginning of class No 5:00

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1 LECTURE 210 PHYSICAL ASPECTS OF ICs (READING: Text-Sec. 2.5, 2.6, 2.8) INTRODUCTION Objective Illustrate the physical aspects of integrated circuits

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

EE 330 Lecture 18. Small-signal Model (very preliminary) Bulk CMOS Process Flow

EE 330 Lecture 18. Small-signal Model (very preliminary) Bulk CMOS Process Flow EE 330 Lecture 18 Small-signal Model (very preliminary) Bulk CMOS Process Flow Review from Last Lecture How many models of the MOSFET do we have? Switch-level model (2) Square-law model Square-law model

More information

LAYOUT TECHNIQUES. Dr. Ivan Grech

LAYOUT TECHNIQUES. Dr. Ivan Grech LAYOUT TECHNIQUES OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout Layout Techniques Main Layers in a typical Double-Poly, Double-Metal

More information

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow

EE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150

More information

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 16. MOSFET Modeling CMOS Process Flow EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model

More information

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow

EE 330 Lecture 17. MOSFET Modeling CMOS Process Flow EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law

More information

EE382M-14 CMOS Analog Integrated Circuit Design

EE382M-14 CMOS Analog Integrated Circuit Design EE382M-14 CMOS Analog Integrated Circuit Design Lecture 3, MOS Capacitances, Passive Components, and Layout of Analog Integrated Circuits MOS Capacitances Type of MOS transistor capacitors Depletion capacitance

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics t ti Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE105 Fall 2007

More information

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET EE 230 Lecture 33 Nonlinear Circuits and Nonlinear Devices Diode BJT MOSFET Review from Last Time: n-channel MOSFET Source Gate L Drain W L EFF Poly Gate oxide n-active p-sub depletion region (electrically

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Lecture 15 OUTLINE MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor Electrostatics Charge vs. voltage characteristic Reading: Chapter 6.1 6.2.1 EE15 Spring 28 Lecture

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16] Code No: RR420203 Set No. 1 1. (a) Find g m and r ds for an n-channel transistor with V GS = 1.2V; V tn = 0.8V; W/L = 10; µncox = 92 µa/v 2 and V DS = Veff + 0.5V The out put impedance constant. λ = 95.3

More information

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process

CMOS Cross Section. EECS240 Spring Dimensions. Today s Lecture. Why Talk About Passives? EE240 Process EECS240 Spring 202 CMOS Cross Section Metal p - substrate p + diffusion Lecture 2: CMOS Technology and Passive Devices Poly n - well n + diffusion Elad Alon Dept. of EECS EECS240 Lecture 2 4 Today s Lecture

More information

2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor?

2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor? EE 330 Exam 1 Spring 2018 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.

More information

6.012 Electronic Devices and Circuits

6.012 Electronic Devices and Circuits Page 1 of 12 YOUR NAME Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology 6.012 Electronic Devices and Circuits FINAL EXAMINATION Open book. Notes: 1. Unless

More information

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft ELEN0037 Microelectronic IC Design Prof. Dr. Michael Kraft Lecture 2: Technological Aspects Technology Passive components Active components CMOS Process Basic Layout Scaling CMOS Technology Integrated

More information

MOS Capacitors ECE 2204

MOS Capacitors ECE 2204 MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits

EE 330 Lecture 22. Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits EE 330 Lecture 22 Small Signal Modelling Operating Points for Amplifier Applications Amplification with Transistor Circuits Exam 2 Friday March 9 Exam 3 Friday April 13 Review Session for Exam 2: 6:00

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

nmos IC Design Report Module: EEE 112

nmos IC Design Report Module: EEE 112 nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the

More information

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology

EECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

Chapter 6: Field-Effect Transistors

Chapter 6: Field-Effect Transistors Chapter 6: Field-Effect Transistors slamic University of Gaza Dr. Talal Skaik FETs vs. BJTs Similarities: Amplifiers Switching devices mpedance matching circuits Differences: FETs are voltage controlled

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

Topics to be Covered. capacitance inductance transmission lines

Topics to be Covered. capacitance inductance transmission lines Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION

ECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z

More information

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

VLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large

More information

Circle the one best answer for each question. Five points per question.

Circle the one best answer for each question. Five points per question. ID # NAME EE-255 EXAM 3 November 8, 2001 Instructor (circle one) Talavage Gray This exam consists of 16 multiple choice questions and one workout problem. Record all answers to the multiple choice questions

More information

Chapter 13 Small-Signal Modeling and Linear Amplification

Chapter 13 Small-Signal Modeling and Linear Amplification Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors

More information

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2

More information

NEEDS Thermoelectric Compact Model Documentation Version 1.0.0

NEEDS Thermoelectric Compact Model Documentation Version 1.0.0 NEEDS Thermoelectric Compact Model Documentation Version 1.0.0 Published on August 31, 2015 Introduction The NEEDS thermoelectric compact model (TEsegment.va) describes a homogeneous segment of thermoelectric

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

55:041 Electronic Circuits The University of Iowa Fall Final Exam

55:041 Electronic Circuits The University of Iowa Fall Final Exam Final Exam Name: Score Max: 135 Question 1 (1 point unless otherwise noted) a. What is the maximum theoretical efficiency for a class-b amplifier? Answer: 78% b. The abbreviation/term ESR is often encountered

More information

Introduction and Background

Introduction and Background Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules

EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files - esign Rules Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate

More information

an introduction to Semiconductor Devices

an introduction to Semiconductor Devices an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -

More information

Make sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference

Make sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Spring 2006 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?

2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer? EE 330 Exam 1 Spring 2017 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Physics for Scientists & Engineers 2

Physics for Scientists & Engineers 2 Review The resistance R of a device is given by Physics for Scientists & Engineers 2 Spring Semester 2005 Lecture 8 R =! L A ρ is resistivity of the material from which the device is constructed L is the

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR EE 23 Lecture 3 THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR Quiz 3 Determine I X. Assume W=u, L=2u, V T =V, uc OX = - 4 A/V 2, λ= And the number is? 3 8 5 2? 6 4 9 7 Quiz 3

More information

EE105 Fall 2014 Microelectronic Devices and Circuits

EE105 Fall 2014 Microelectronic Devices and Circuits EE05 Fall 204 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 5 Sutardja Dai Hall (SDH) Terminal Gain and I/O Resistances of BJT Amplifiers Emitter (CE) Collector (CC) Base (CB)

More information

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 3 Dominique Thiébaut

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 3 Dominique Thiébaut mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 3 Dominique Thiébaut dthiebaut@smith.edu Crash Course in Electricity and Electronics Zero Physics background expected!

More information

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions

EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions EE105 Fall 2015 Microelectronic Devices and Circuits: Semiconductor Fabrication and PN Junctions Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 pn Junction p-type semiconductor in

More information

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET: Lecture 15: MOS Transistor models: Body effects, SPICE models Context In the last lecture, we discussed the modes of operation of a MOS FET: oltage controlled resistor model I- curve (Square-Law Model)

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

The Gradual Channel Approximation for the MOSFET:

The Gradual Channel Approximation for the MOSFET: 6.01 - Electronic Devices and Circuits Fall 003 The Gradual Channel Approximation for the MOSFET: We are modeling the terminal characteristics of a MOSFET and thus want i D (v DS, v GS, v BS ), i B (v

More information

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen

Lecture 150 Basic IC Processes (10/10/01) Page ECE Analog Integrated Circuits and Systems P.E. Allen Lecture 150 Basic IC Processes (10/10/01) Page 1501 LECTURE 150 BASIC IC PROCESSES (READING: TextSec. 2.2) INTRODUCTION Objective The objective of this presentation is: 1.) Introduce the fabrication of

More information

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs EECS 142 Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs Prof. Ali M. Niknejad University of California, Berkeley Copyright c 2005 by Ali M. Niknejad A. M. Niknejad University of California,

More information

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen

Lecture 040 Integrated Circuit Technology - II (5/11/03) Page ECE Frequency Synthesizers P.E. Allen Lecture 040 Integrated Circuit Technology - II (5/11/03) Page 040-1 LECTURE 040 INTEGRATED CIRCUIT TECHNOLOGY - II (Reference [7,8]) Objective The objective of this presentation is: 1.) Illustrate and

More information

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University NAME: PUID: : ECE 305 Exam 5 SOLUTIONS: April 17, 2015 Mark Lundstrom Purdue University This is a closed book exam. You may use a calculator and the formula sheet at the end of this exam. Following the

More information

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure Outline 1. Introduction to MOS structure 2. Electrostatics of MOS in thermal equilibrium 3. Electrostatics of MOS with

More information

Bipolar Junction Transistor (BJT) - Introduction

Bipolar Junction Transistor (BJT) - Introduction Bipolar Junction Transistor (BJT) - Introduction It was found in 1948 at the Bell Telephone Laboratories. It is a three terminal device and has three semiconductor regions. It can be used in signal amplification

More information

Lecture 11: MOS Transistor

Lecture 11: MOS Transistor Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout

More information

Lecture 12 CMOS Delay & Transient Response

Lecture 12 CMOS Delay & Transient Response EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 12 CMOS Delay & Transient Response Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology

More information

ECE321 Electronics I

ECE321 Electronics I ECE321 Electronics I Lecture 4: Physics of Semiconductor iodes Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: pzarkesh.unm.edu Slide: 1 Review of Last

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

Homework Assignment 09

Homework Assignment 09 Homework Assignment 09 Question 1 (Short Takes) Two points each unless otherwise indicated. 1. What is the 3-dB bandwidth of the amplifier shown below if r π = 2.5K, r o = 100K, g m = 40 ms, and C L =

More information

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13

Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Self-study problems and questions Processing and Device Technology, FFF110/FYSD13 Version 2016_01 In addition to the problems discussed at the seminars and at the lectures, you can use this set of problems

More information

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130

CARLETON UNIVERSITY. FINAL EXAMINATION December DURATION 3 HOURS No. of Students 130 ALETON UNIVESITY FINAL EXAMINATION December 005 DUATION 3 HOUS No. of Students 130 Department Name & ourse Number: Electronics ELE 3509 ourse Instructor(s): Prof. John W. M. ogers and alvin Plett AUTHOIZED

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

Lecture 7 MOS Capacitor

Lecture 7 MOS Capacitor EE 471: Transport Phenomena in Solid State Devices Spring 2018 Lecture 7 MOS Capacitor Bryan Ackland Department of Electrical and Computer Engineering Stevens Institute of Technology Hoboken, NJ 07030

More information

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances

EE 435. Lecture 37. Parasitic Capacitances in MOS Devices. String DAC Parasitic Capacitances EE 435 Lecture 37 Parasitic Capacitances in MOS Devices String DAC Parasitic Capacitances Parasitic Capacitors in MOSFET (will initially consider two) Parasitic Capacitors in MOSFET C GCH Parasitic Capacitors

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )

More information

5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS

5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS 5. EXPERIMENT 5. JFET NOISE MEASURE- MENTS 5.1 Object The objects of this experiment are to measure the spectral density of the noise current output of a JFET, to compare the measured spectral density

More information

Objective of Lecture Discuss resistivity and the three categories of materials Chapter 2.1 Show the mathematical relationships between charge,

Objective of Lecture Discuss resistivity and the three categories of materials Chapter 2.1 Show the mathematical relationships between charge, Objective of Lecture Discuss resistivity and the three categories of materials Chapter 2.1 Show the mathematical relationships between charge, current, voltage, and energy. Chapter 2.2-2.4 Define resistance

More information

EE 435. Lecture 22. Offset Voltages

EE 435. Lecture 22. Offset Voltages EE 435 Lecture Offset Voltages . Review from last lecture. Offset Voltage Definition: The input-referred offset voltage is the differential dc input voltage that must be applied to obtain the desired output

More information

EEE598D: Analog Filter & Signal Processing Circuits

EEE598D: Analog Filter & Signal Processing Circuits EEE598D: Analog Filter & Signal Processing Circuits Instructor: Dr. Hongjiang Song Department of Electrical Engineering Arizona State University Thursday January 24, 2002 Today: Active RC & MOS-C Circuits

More information

in Electronic Devices and Circuits

in Electronic Devices and Circuits in Electronic Devices and Circuits Noise is any unwanted excitation of a circuit, any input that is not an information-bearing signal. Noise comes from External sources: Unintended coupling with other

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 7 Interconnections 1: wire resistance, capacitance,

More information

Problem info Geometry model Labelled Objects Results Nonlinear dependencies

Problem info Geometry model Labelled Objects Results Nonlinear dependencies Problem info Problem type: Transient Magnetics (integration time: 9.99999993922529E-09 s.) Geometry model class: Plane-Parallel Problem database file names: Problem: circuit.pbm Geometry: Circuit.mod Material

More information

DIFFUSION - Chapter 7

DIFFUSION - Chapter 7 DIFFUSION - Chapter 7 Doping profiles determine many short-channel characteristics in MOS devices. Resistance impacts drive current. Scaling implies all lateral and vertical dimensions scale by the same

More information

Lecture 11: J-FET and MOSFET

Lecture 11: J-FET and MOSFET ENE 311 Lecture 11: J-FET and MOSFET FETs vs. BJTs Similarities: Amplifiers Switching devices Impedance matching circuits Differences: FETs are voltage controlled devices. BJTs are current controlled devices.

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

EE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods

EE 230 Lecture 20. Nonlinear Op Amp Applications. The Comparator Nonlinear Analysis Methods EE 230 Lecture 20 Nonlinear Op Amp Applications The Comparator Nonlinear Analysis Methods Quiz 14 What is the major purpose of compensation when designing an operatinal amplifier? And the number is? 1

More information

figure shows a pnp transistor biased to operate in the active mode

figure shows a pnp transistor biased to operate in the active mode Lecture 10b EE-215 Electronic Devices and Circuits Asst Prof Muhammad Anis Chaudhary BJT: Device Structure and Physical Operation The pnp Transistor figure shows a pnp transistor biased to operate in the

More information

Chapter 2 The Well 9/5/2017. E E 480 Introduction to Analog and Digital VLSI Paul M. Furth New Mexico State University

Chapter 2 The Well 9/5/2017. E E 480 Introduction to Analog and Digital VLSI Paul M. Furth New Mexico State University hapter 2 The Well E E 480 Introduction to Analog and Digital VLSI Paul M. Furth New Mexico State University p+ sub ~ 150 m thick, p-epi ~ 30 m thick All transistors go in p- epi layer Typical p- doping

More information

Conventional Paper I-2010

Conventional Paper I-2010 Conventional Paper I-010 1. (a) Sketch the covalent bonding of Si atoms in a intrinsic Si crystal Illustrate with sketches the formation of bonding in presence of donor and acceptor atoms. Sketch the energy

More information

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering NAME: GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering ECE 4430 First Exam Closed Book and Notes Fall 2002 September 27, 2002 General Instructions: 1. Write on one side of

More information

Electrical Characteristics of MOS Devices

Electrical Characteristics of MOS Devices Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage

More information

Device 3D. 3D Device Simulator. Nano Scale Devices. Fin FET

Device 3D. 3D Device Simulator. Nano Scale Devices. Fin FET Device 3D 3D Device Simulator Device 3D is a physics based 3D device simulator for any device type and includes material properties for the commonly used semiconductor materials in use today. The physical

More information

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom

ID # NAME. EE-255 EXAM 3 April 7, Instructor (circle one) Ogborn Lundstrom ID # NAME EE-255 EXAM 3 April 7, 1998 Instructor (circle one) Ogborn Lundstrom This exam consists of 20 multiple choice questions. Record all answers on this page, but you must turn in the entire exam.

More information

Operational Amplifiers

Operational Amplifiers Operational Amplifiers A Linear IC circuit Operational Amplifier (op-amp) An op-amp is a high-gain amplifier that has high input impedance and low output impedance. An ideal op-amp has infinite gain and

More information

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00 1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.

More information

Chapter 25 Current, Resistance, and Electromotive Force

Chapter 25 Current, Resistance, and Electromotive Force Chapter 25 Current, Resistance, and Electromotive Force Lecture by Dr. Hebin Li Goals for Chapter 25 To understand current and how charges move in a conductor To understand resistivity and conductivity

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices

Electronic Circuits 1. Transistor Devices. Contents BJT and FET Characteristics Operations. Prof. C.K. Tse: Transistor devices Electronic Circuits 1 Transistor Devices Contents BJT and FET Characteristics Operations 1 What is a transistor? Three-terminal device whose voltage-current relationship is controlled by a third voltage

More information