Blind phase/frequency synchronization with low-precision ADC: a Bayesian approach

Transcription

1 Blind phase/frequency synchronization with low-precision ADC: a Bayesian approach Aseem Wadhwa, Upamanyu Madhow Department of ECE, UCSB 1/26

2 Modern Communication Receiver Architecture Analog Digital TX Channel Analog Preprocessing (Downconversion, AGC etc) ADC DSP Leveraging Moore s Law Faithful Conversion Synchronization Equalization Decoding (low quantization error) 2/26

3 Challenge Wideband (multi GHz) Applications: mm-wave communication (eg. 60 GHz) Backplane chip-to-chip communication Optical Fiber communication Effective Number of Bits (ENOB) f s (Hz) - sampling frequency * Data from B. Murmann, "ADC Performance Survey ," [Online]. Available: 3/26

4 Low Precision ADC Are DSP-centric designs with heavily quantized samples effective? Shannon-theoretic analysis : loss in channel capacity relatively small (J. Singh et al 2009) AWGN channel Block Non-coherent Communication 4/26

5 Revisiting DSP Algorithms with significant Non-linearity Reconsider classical problems: synchronization, equalization etc Architecture: Bayesian Mixed-Signal Processing TX Channel Analog Frontend (Preprocessing) A-to-D Conversion Coarse Digitally Controlled Feedback (AGC, phase rotation etc) Bayesian Inference (DSP) Non-linear Algorithms 5/26

6 Focus of our paper Canonical Problem of Blind phase/frequency synchronization TX complex symbols (unknown) Unknown Channel Phase Unknown Frequency Offset Complex AWGN Observations: Heavily Quantized Phase Simplifying Assumptions: Non-Dispersive Channel Perfect Timing Sync, Nyquist rate symbols differentially modulated QPSK 6/26

7 Outline 1. Receiver Architecture 2. Rapid Phase Acquisition (Blind mode) 3. Phase/Frequency Tracking (Decision Directed mode) 7/26

8 Receiver Architecture: Phase-only Quantization using 1-bit ADCs (AGC-free quantization) Received Passband Waveform Downconversion I Q Pass Linear combinations of I & Q through 1-bit ADCs M=8 bins (4 ADCs) M=12 bins (6 ADCs) 8/26

9 Receiver Architecture: Feedback Transmitter Phase Quantization Channel QPSK Feedback DSP for Bayesian estimation Decoded Symbols Quantized phase measurements (1,2,..,M) Digitally controlled Derotation Phase 9/26

10 Phase Acquisition example: T s = (6 GHz) -1 f c = 60GHz Δf = (100)10-6 * f c Set Δf=0 consider unquantized phase u {1,3,5,7} Blind Mode (Unknown Sequence) net phase rotation 10/26

11 (1) Bayesian Estimation (Given θ k ) Conditional Distribution of u has a closed form expression (2) M=12 bins (6 ADCs) 11/26

12 (3) Recursive Bayes Update Updated Posterior Old Posterior Step Update How to set the derotation phase? 12/26

13 Constant θ k : Issues Example 1 : 4 ADCs (M=8 bins) Bimodal Posterior with Peaks at x 0 and (45 x) 0 θ k = 0 0 θ k = 10 0 θ k Random Posterior of φ after 150 symbols (SNR = 5dB) 13/26

14 Constant θ k : Issues Example 2 : High SNR θ k = 0 0 θ k = 10 0 θ k Random Posterior of φ after 30 symbols (SNR = 35dB) 1. Dithering is Required 2. Random Dithering is a robust choice 14/26

15 Can we do better than Random Dither? Optimizing {θ k } to minimize MSE difficult problem - leads to Partially Observable Markov Decision Process Problem (POMDP) We propose an Information-theoretic Greedy Entropy Policy Idea : Minimize the entropy of the posterior distribution across choices of derotation phase over the next step 15/26

16 Greedy Entropy Policy (Single Horizon) Latest Posterior : Next Posterior : average over f k-1 (φ) 16/26

17 Greedy Entropy Policy: What it tries to do? Roughly, it tries to moves the net phase, prior to quantization, towards boundary at high SNR middle for M=12 at low SNR boundary for M=8 at low SNR Ē(θ) becomes flatter as variance of posterior of φ (f(φ)) decreases --> Random Dithering initially, when variance is high but estimate is good, better than randomly choosing θ M=8 M=12 17/26

18 Simulation Results (1/4) Low SNR (5dB) 8 bins Expected RMSE Pr(error) < /26

19 Simulation Results (2/4) Low SNR (5dB) 12 bins Expected RMSE Pr(error) < /26

20 Simulation Results (3/4) High SNR (15dB) 8 bins Expected RMSE Pr(error) < /26

21 Simulation Results (4/4) High SNR (15dB) 12 bins Expected RMSE Pr(error) < 5 0 High SNR and coarse quantization Gains by optimizing Dither 21/26

22 Frequency Estimation example: T s = (6 GHz) -1 f c = 60GHz Δf = (100)10-6 * f c Phase almost constant for few 10s of symbols This motivates a Hierarchical Approach: 1. windowed MAP estimate of phase coarse estimate 2. feed to an EKF for tracking both phase and frequency 22/26

23 Extended Kalman Filter (EKF) State model Process Model Measurement Model 23/26

24 Remarks Derotation Phases: set to current estimate of phase undo channel phase Decision Directed Mode W=50, Tracking Robust to choice of R (R = [0.1 0, 0 0.1] T ) Q (process noise) controls speed of adaptation and accuracy of estimates 24/26

25 Simulations 25/26

26 Conclusions Digitally controlled Analog pre-processing provides dither Bayesian algorithms for estimation and feedback generation Future Work: Modeling other non-idealities (fading, dispersion, timing asynchronism) Larger Constellations Fundamental limits on performance 26/26

27 Back up Slides 27/26

28 *Walden /26

29 uniform action Example Φ = 10 0 θ = net phase posterior φ posterior Φ = 10 0 θ = net phase posterior φ posterior 29/26

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