SiGe and CMOS. K. J. Kuhn, A. Murthy, R. Kotlyar, and M. Kuhn Intel Corporation. Kelin Kuhn / ECS Meeting / October 10 th,

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1 Past, Present and Future: SiGe and CMOS Transistor Scaling K. J. Kuhn, A. Murthy, R. Kotlyar, and M. Kuhn Intel Corporation Kelin Kuhn / ECS Meeting / October 10 th,

2 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

3 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

4 Consistent 2-year scaling 22nm WIDE 32nm WIDE 45nm WIDE m m nm WIDE m m 2 90nm TALL 1.0 m 2 90 nm 65 nm 45 nm 32 nm 22 nm projected 90: 7 65: 8 45: 9 32: 9 Kelin Kuhn / ECS Meeting / October 10 th,

Changes in Scaling THEN NOW Scaling drove

constrained Active power dominates Standby

Collaborative design-process 130nm 90nm 65nm

5 Changes in Scaling THEN NOW Scaling drove down cost Scaling drives down cost Scaling drove performance Materials di drive performance Performance constrained Power constrained Active power dominates Standby power dominates Independent design-process Collaborative design-process 130nm 90nm 65nm 45nm 32nm Kelin Kuhn / ECS Meeting / October 10 th,

6 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

7 Transistor Performance Trend Drive Current (ma/um) V, 100 na I OFF 90nm 130nm 65nm 45nm 32nm Strain Hi-k-MG Other Classic scaling PMOS Gate Pitch (nm) 100 Strain is a critical ingredient in modern transistor scaling Strain was first introduced at 90nm, and its contribution has increased in each subsequent generation Kelin Kuhn / ECS Meeting / October 10 th,

8 Uniaxial Strain Enhancement with Embedded SiGe (PMOS) Thompson Intel Ghani Intel Chidambaram IEDM 2002 / 2004 [28-30] IEDM 2003 [31] TI / Applied Materials VLSI [32] Kelin Kuhn / ECS Meeting / October 10 th,

9 Transistor Results: Channel Strain -0.1 Simulations show epitaxial S/D transistor has uniaxial compressive channel strain (Giles VLSI 04, [24]) TEM electron diffraction 0 measurements confirm 0.6% lattice displacement (Mistry, VLSI 04 04, [26]) Channel SiGe L 0.1 GATE =50nm Kelin Kuhn / ECS Meeting / October 10 th,

10 Technology Strain Trend Ge concentrati ion in EPI (a at.%) Channel Strain Ge concentration l Strain (GPa a) Channe 0 130nm 90nm 65nm 45nm 32nm 0.0 Strain is a critical ingredient in modern transistor scaling Strain was first introduced at 90nm, and its contribution has increased in each subsequent generation Kelin Kuhn / ECS Meeting / October 10 th,

11 K.P Bandstructure: No Stress Bulk heavy hole has 12 nodes 4 of them are in k z =0 plane Vertical gate field confines holes into an inversion layer Moves from a bulk to a confined band structure 8 off-plane nodes projected to k z =0 plane in quantized k.p k z [110] k y Channel Quantized k z Band k x D 4 A D 3 B C In-plane WingsABCD A,B,C,D Off-plane Wings 1,2,3,4 3 B 2 1 C Bulk Band Giles et al., Wang et al.: IEDM 2004,

Uniaxial Stress along [110] Uniaxial stress along [110] has shear and

Holes redistribute from (A,B) to (C,D) The effective mass and density

1GPa uniaxial stress along g[ [110],(001) surface, 1MV/cm effective

12 Uniaxial Stress along [110] Uniaxial stress along [110] has shear and biaxial components C A Shear compression lowers the energy of (C,D) Holes redistribute from (A,B) to (C,D) The effective mass and density of states (DOS) for scattering are reduced k y (2 /a) B k x (2 /a) D 1GPa uniaxial stress along g[ [110],(001) surface, 1MV/cm effective field, 30meV energy contours Giles et al., Wang et al.: IEDM 2004,

13 Uniaxial vs Biaxial Uniaxial strain introduced in a Si channel by SiGe in the S/D region. Biaxial strain introduced in a Si channel by SiGe below the channel region (or by a bonding process starting with SiGe below the channel region). s-si SGOI, SSGOI SSOI, SSDOI Strained Si Strained Si Strained Si SiGe SiGe Buried oxide Buried oxide Si substrate Si substrate Si substrate Kelin Kuhn / ECS Meeting / October 10 th,

Calculated using MASTAR (http://www.itrs.net/models.

14 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

15 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

16 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

17 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

18 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

19 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

20 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

21 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

22 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

23 Calculated using MASTAR ( UNIAXIAL COMPRESSION BIAXIAL TENSION Kuhn IEDM SC GP 2GP 3GP 14

24 Kuhn, IEDM SC Wang, IEDM 2006 NO STRAIN UNIAXIAL COMPRESSION BIAXIAL TENSION 2.5GPa 3D plots Calculated using MASTAR ( 15

25 Orientation and Strain: More complex for non-(100) orientations (100) <110> (001) Surface (k =0) (001) Surface Vg=-1V (001) Surface Vg=-1V, Sxx=-1GPa (110) (110) Surface (k =0) (110) Surface Vg=-1V (110) Surface Vg=-1V, Sxx=-1GPa <110> BULK 1 D CONFINED 1 D CONFINED STRAINED Kuhn/Packan, Intel, IEDM Kelin 2008 Kuhn / ECS Meeting / October 10 th,

26 Orientation and Strain: More complex for non-(100) orientations 1000 s Si (110) Si Mobility cm^2/v (100) Si 200 Hole Stress (GPa) 0 Kelin Kuhn / ECS Meeting / October 10 th,

27 Orientation and Strain: More complex for non-(100) orientations Thompson U of Florida IEDM 2006 Sun U of Florida JAP 2007 Yang AMD/IBM IEDM 2007 While (100) mobilities agree reasonably well, a strong discrepancy exists for (110) mobilities - Yang, AMD/IBM, IEDM 2007, with reference to Thompson, IEDM 2006) 17A Kelin Kuhn / IEDM

28 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

29 Transistor Performance Trend Drive Current (ma/um) V, 100 na I OFF 90nm 130nm 65nm 45nm 32nm Strain Hi-k-MG Other Classic scaling PMOS Gate Pitch (nm) 100 Manufacturable HiK-MG transistors were first introduced in the 45nm generation Kelin Kuhn / ECS Meeting / October 10 th,

Si vs Ge MOSFETs Gate Source Source n-ge

led to the reconsideration of Ge channels

30 Si vs Ge MOSFETs Gate Source Source n-ge Drain Intel 45nm HiK-MG Si device [43] Intel HiK-MG Ge device The introduction of manufacturable HiK-MG transistors has led to the reconsideration of Ge channels Kelin Kuhn / ECS Meeting / October 10 th,

31 The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. The image cannot be displayed. Your computer may not have enough memory to open the image, or the image may have been corrupted. Restart your computer, and then open the file again. If the red x still appears, you may have to delete the image and then insert it again. Challenge of Lattice Mismatch Issues Device Layer Silicon Direct Deposition Defects Si Silicon Dislocations III-V Stacking faults Si Twin Defects Adapted from J. Kavalieros Intel - VLSI SC 2007 Kelin Kuhn / ECS Meeting / October 10 th,

32 Ge and PMOS Hole and Electron Mobility (cm2-v.s) Si Ge InP GaAs InSb Bandgap and Electron Affinity (ev) Ge mobility makes it uniquely interesting for PMOS Kelin Kuhn / ECS Meeting / October 10 th,

33 Si vs Ge Bandstructure/Parameters Band Masses at Gamma point (using kp parameters, in m e ): HH LH SO Si Ge Energy ev G Bandstructure Si, Ge L X K G 5 Kelin Kuhn / ECS Meeting / October 10 th,

34 Low Field Long Channel Mobility (as a function of stress) 1000 s Si (110) Si Mobility cm^2/v (100) Si 200 Hole Stress (GPa) 0 Kelin Kuhn / ECS Meeting / October 10 th,

35 Low Field Long Channel Mobility (as a function of stress) Si (100) Ge (110) Si Ge (110) Ge Mobility cm^2/v s (100) Si 200 Hole Stress (GPa) 0 Kelin Kuhn / ECS Meeting / October 10 th,

36 III-V vs Ge: NMOS The Lure of High Mobility d y (ev) ndgap and n Affinity Ban Electro Si Ge InP GaAs InSb ron V.s) nd Electr ty (cm2-v Hole an Mobili Adapted from J. Kavalieros Intel - VLSI SC 2007 K. Kuhn ECS 2010 Kelin Kuhn / ECS Meeting / October 10 th,

37 Low m* MOSFETs: Density-of-states states bottleneck On-current of a MOSFET I Q Velocity υ Diffusive : mobility μ, υ = μe Ballistic: injection velocity υ inj Light m* high μ, high υ inj From R. Kim Charge Q MOS limit (C Q» C ox ), C C ox Light m* less D (C Q ), less C, less Q More important for thin oxide (large C ox ), DOS bottleneck Q C V V G C C C C Q ox 2 q D Q th Kelin Kuhn / ECS Meeting / October 10 th,

38 5 High-Current L & -L channels: 5 Approaches Rodwell et al, 2010 Device Research Conference 6/21/2010 Rodwell, DRC, 2010 blue=occupied red=vacant ed drive current K 1 normaliz only InGaAs EET=Equivalent Electrostatic Thickness =T / +T / ox SiO2 ox inversion SiO2 semiconductor Si 0.4 nm 0.6 nm EET=1.0 nm g=2 g=1 0 includes the wavefunction depth term T inversion SiO2 / semiconductor m*/m o normalize ed drive current K nm EET=1.0 nm 0.3 nm 0.4 nm g=2, m /m =0.7 perpendicular 0 g=2, m /m =0.6 perpendicular 0 g=2, m perpendicular /m 0 =0.5 ma V 1 84 gs V J K th m 1V 0.1 EET=Equivalent Electrostatic Thickness =T ox SiO2 / ox +T inversion SiO2 / semiconductor m*/m o 3/ 2 Drain cu urrent, ma/ m nm well pitch 0.3 nm EET 0.6 nm EET 6 5 V -V =0.3 V gs th nm well pitch 2 EET=Equivalent Electrostatic Thickness 1 =T / +T / ox SiO2 ox inversion SiO2 semiconductor 0 includes the wavefunction depth term T / inversion SiO2 semiconductor m*/mo

39 Use of L-valleys: GaAs From R. Kim GaAs 4 nm (100) k y 8 L-valleys [011] Small DOS with high v inj High DOS with low v inj k x [010] single band from Γ k y [-1-12] [-211] Multiple bands from More DOS with high v inj Γ and L (111) k x [-110] Kelin Kuhn / ECS Meeting / October 10 th,

40 Different body thicknesses (EOT=1.0 nm) 2nm 4nm 8nm GaAs>InGaAs>GaSb>Ge>Si GaSb,InGaAs>Ge,GaAs>Si InGaAs>GaSb>Ge,GaAs>Si Different body thicknesses (EOT=0.5 nm) 2 nm 4 nm 8 nm GaSb>GaAs>Ge>Si>InGaAs GaSb>Ge>GaAs>Si,InGaAs GaSb>Ge>GaAs, InGaAs>Si Kelin Kuhn / ECS Meeting / October 10 th, 2010 From R. Kim

41 Ge Historical Issues: Still critical today Bandga ap and Elec ctron Affini ity (ev) Si Ge InP GaAs InSb MO (cm2/v V.s) Si (no strain) Ge 100% Ge 55% SiGe 25% TOXE (A) Narrow Bandgap Poor Quality Dielectric Kelin Kuhn / ECS Meeting / October 10 th,

42 Narrow Bandgap Ene ergy Bandga ap (ev) Eg SiGe (PERCENTAGE) mobility (cm m^2/v.s) Hole s [A/um] Id, I Source 1.E-03 1.E-04 1.E-05 1.E-06 1.E-07 Adapted from Saraswat [59], Krishnamohan [60] BTBT h e DRAIN DRAIN High Junction Leakage Eg Drain 1.E-08 Source Source 1.E Vg - Vt [V] Band-to-band tunneling: challenge for low Eg materials Kelin Kuhn / ECS Meeting / October 10 th,

43 Narrow Bandgap Adapted from Saraswat [59], Krishnamohan [60] Source High BTBT Weak quantum confinement Narrow effective energy gap Source h e Eg Drain Reduced BTBT Strong quantum confinement Wide effective energy gap h e Eg Drain Two solutions: Use lower voltages and/or use quantum confined systems Kelin Kuhn / ECS Meeting / October 10 th,

Dielectric Quality Ge to GeO (110) 2 Ge/Ge GeO

Since HiK-MG dielectrics typically form with a

challenge of germanium oxide still exists.

unfortunately, most are hydroscopic and/or

44 Dielectric Quality Ge to GeO (110) 2 Ge/Ge GeO 2 sub oxide transition Ge(111) Heynes, 2008 [9] Since HiK-MG dielectrics typically form with a bilayer (the HiK + an interface layer) the challenge of germanium oxide still exists. Germanium oxide exists in several morphologies, unfortunately, most are hydroscopic and/or volatile.. Kelin Kuhn / ECS Meeting / October 10 th,

adsorbates Density of St tates 40 30 20 10 Flat dimers Ge(100)-4 2: PBE0 Ge(100)-2x1: PBE0 E (2 1) F VB CB Ge interfaces.

0 Each Ge atom has ½ filled dangling bond Energy (ev) VB O = red, Ge = green, Hf = blue, H = white No GeO2 needed, full

Therefore, oxide must passivate ALL tricoodinated Ge surface atoms Density D function theory molecular l dynamics (DFT-MD)

45 E. Chagarov, T. Grassman, A. Kummel (UCSD) a-mo 2 /Ge without and with Passivation (2010 Sematech) 2 1/4 2 buckled dimers PBE0-Grassman Free of adsorbates Density of St tates Flat dimers Ge(100)-4 2: PBE0 Ge(100)-2x1: PBE0 E (2 1) F VB CB Ge interfaces. Buckled dimers Each Ge atom has ½ filled dangling bond Energy (ev) VB O = red, Ge = green, Hf = blue, H = white No GeO2 needed, full passivation possible with HfO2, path to small EOT E f CB Although ideal Ge(100) is unpinned, flat dimers or undimerized Ge atoms can pin the Fermi level. As shown on the left the ideal surface has a bulk like bandgap due to tilted dimers which will be absent at oxide- Therefore, oxide must passivate ALL tricoodinated Ge surface atoms Density D function theory molecular l dynamics (DFT-MD) was used to bond amorphous HfO 2 to Ge(100) and anneal at 700K. Interface has a mix of Ge-O and Ge-Hf bonds. Oxides passivate dangling bonds; 100% of interfacial Ge have 4 bonds. Interface is abrupt and Ge lattice is undisturbed. DOS shows a bandgap gpof 0.8 ev with no midgap states either in the interface or the channel. Fermi level shift from dipoles at oxide/vacuum interface being fixed. 34

46 Ge-J. Lee, T. Kaufman-Osborn, A. Kummel (UCSD) Monolayer Functionalization of Ge (2010 Sematech) The key requirement for scaling oxides on Ge while nm 2 H maintaining high mobility is functionalizing the O Ge(100) with a monolayer of reactive sites. This is challenging as even the most stable germanium oxides react with the substrate to form volatile suboxide. The Kummel group at UCSD has used STM to show that very large doses of water onto clean 300K H Ge(100) can functionalize 99% of the unit cells with O Ge-H and Ge-OH bonds. Ge These bonds are sufficiently reactive with TMA (trimethyl aluminum) that the ALD process can be initiated at 300K for the first layer. Key message: A 300K process has been developed to template the ALD processes in nearly every unit cell for EOT scaling without disrupting the substrate Ge lattice. Ge H Ge fully - occupied dimer Ge unoccupied or H Ge half - occupied dimer Ge dimer Ge Ge-OH and Ge-H sites cover Ge(100) surface (rectangle) with >10 6 L dose of H 2 O at 300K Fuzzy bright features are unreacted dangling bonds (squares). Can passivate with H or annealing ½ ML of Ge-OH perfect template for nucleation of TMA for scaled ALD gate oxide (even HfO 2 ) XPS studies show this surface reacts at 300K with TMA to form ½ ML of Ge-O-Al bonds which are stable up to 450C thereby functionalizing the surface for ALD of high-k. 35

47 Ge Dielectric: Another strategy: use an Si passivation layer Zimmerman Intel/IMEC IEDM 2006 [48] Si passivation Hellings IMEC/Leuven EDL 2009 [50] Si passivation Mitard IMEC/Leuven VLSI 2009 [51] Si passivation Kelin Kuhn / ECS Meeting / October 10 th,

48 Ge Benchmarking Yamamoto 2007 Wang 2007 Ioff (A/u um) Irisawa E-03 1.E-04 1.E-05 1.E-06 1.E-07 1E08 1.E-08 Romanjek 2008 Nicholas 2007 Batail 2009 [52] Zimmerman 2006 [48] Tezuka 2006 Andrieu E Liao 2008 Ion (ma/um) Harris 2007 Mitard 2009 [51] Hellings 2009 [50] Batail [52] updated with (48, 50, 51, 52) Kelin Kuhn / ECS Meeting / October 10 th,

49 Mitard, IMEC/Leuven, IEDM 2008 Ultra-thin Si cap + 4nm HfO2 Inversion EOT 13A Dit integrated over valence band Kelin Kuhn / ECS Meeting / October 10 th,

50 Mitard, IMEC/Leuven, VLSI 2009 Higher Coulomb scattering For 2 or 3nm HfO2 Kelin Kuhn / ECS Meeting / October 10 th, 2010 Higher Coulomb scattering For thinner TL SiO2 40

Zimmerman, IMEC/Intel, IEDM 2006 6A epi-si, partially oxidized d after

51 Zimmerman, IMEC/Intel, IEDM A epi-si, partially oxidized d after growth+4nm HfO2 10x10um Note respectable high field mobility CET = 16A, EOT = 12/12.5A 10x10um structure Jg not influencing Ids Before/after Post metallization anneal (PMA) Kelin Kuhn / ECS Meeting / October 10 th,

52 Ge Benchmarking Yamamoto 2007 Wang 2007 Ioff (A/u um) Irisawa E-03 1.E-04 1.E-05 1.E-06 1.E-07 1E08 1.E-08 Romanjek 2008 Nicholas 2007 Batail 2009 [52] Zimmerman 2006 [48] Tezuka 2006 Andrieu E Liao 2008 Ion (ma/um) Harris 2007 Mitard 2009 [51] Hellings 2009 [50] Batail [52] updated with (48, 50, 51, 52) Kelin Kuhn / ECS Meeting / October 10 th,

53 Hellings IMEC/Leuven, EDL 2009 Boron LDD Ultra-thin Si cap + 4nm HfO2 Batail ST-Micro, IEDM 2008 Selective epitaxy of pure Ge capped with Si Kelin Kuhn / ECS Meeting / October 10 th,

54 Kita (U. Tokyo) IEDM 2009 Another strategy: Advanced GeO 2 processing Ge diffusion High-pressure O2 (HPO) suppresses surface reaction Isotope experiment Suggests Ge diffusion Possible Defects Low-T oxygen Annealing (LOA) 70 atm Kelin Kuhn / ECS Meeting / October 10 th,

55 Lee (U. Tokyo) IEDM 2009 High pressure O 2 (HPO) + Low-Temperature Oxygen Anneal (LOA) Kelin Kuhn / ECS Meeting / October 10 th,

56 Kuzum (Stanford) IEDM/TED 2009 GeOxNy + Low-Temperature Oxygen Anneal (LOA) Kelin Kuhn / ECS Meeting / October 10 th,

57 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

58 WIDTH = 2H + W WIDTH LENGTH Non-planar architectures t Kelin Kuhn / ECS Meeting / October 10 th,

(gates tied together) Improved RDF (low doped channel) Can be on bulk or

59 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal subthreshold slope (gates tied together) Improved RDF (low doped channel) Can be on bulk or SOI Kelin Kuhn / ECS Meeting / October 10 th, 2010 Excellent channel control 49

60 MuGFET with RSD Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Nearly ideal subthreshold slope (gates tied together) Benefits Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Kelin Kuhn / ECS Meeting / October 10 th,

61 MuGFET Benefits Double-gate relaxes Tsi requirements Fin Wsi > UTB Tsi (less scattering, improved VT shift) Possibility for independent gate operation Improved RDF (low doped channel) Excellent channel control Kelin Kuhn / ECS Meeting / October 10 th,

62 MuGFET Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring Hsi/Wsi/epi) Challenges Gate wraparound (Endcap coverage) Small fin pitch (2 generation scale?) Fin/gate fidelity on 3 D (Patterning/etch) Fin Strain engr. (Effective strain transfer from a fin into the channel) Topology Rext: (Polish / etch (Xj/Wsi challenges) limitations) Kelin Kuhn / ECS Meeting / October 10 th,

63 Kawasaki Toshiba / IBM IEDM 2009 MuGFET Sim Jurczak IMEC - SOI 2009 Kelin Kuhn / ECS Meeting / October 10 th,

64 High Mobility SiGe FinFETs 2 eff (cm /V-s) 350 SiGe {110}<110> (110) 300 SiGe SiGe fin {100}<100> (Tinv= Si 1.8nm) {110}<110> 250 Si {100}<100> (100) universal (100) shell/core fin (Tinv=1.5nm) Si fin (Tinv = 1.2nm) Universal (100) 0 0 1x x10 13 N INV (#/cm 3 ) INV Extracted by Split CV Method SiGe PFETs have higher mobility than Si fins. Potential for performance > strained Si in non-planar devices November 2010

65 Nanowire Benefits Nearly ideal subthreshold slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Excellent channel control Kelin Kuhn / ECS Meeting / October 10 th,

66 Nanowire Benefits Nearly ideal subthreshold slope (gates tied together) Nanowire further relaxes Tsi / Wsi requirements Improved RDF (low doped channel) Compatible with RSD technology Excellent channel control Kelin Kuhn / ECS Meeting / October 10 th,

67 Nanowire Integrated wire fabrication (Epitaxy? Other?) Mobility degradation (scattering) Gate conformality (dielectric and metal) Wire stability (bending/warping) Challenges Capacitance (fringe to contact/facet) (Plus, additional dead space elements) Variation (Mitigating RDF but acquiring a myriad of new sources) Fin Strain engr. (Effective strain transfer from wire into the channel) Rext: (Xj/Wsi limitations) Kelin Kuhn / ECS Meeting / October 10 th, 2010 Fin/gate fidelity on 3 D (Patterning/etch) Topology (Polish / etch challenges) 52

68 Stacked Si Nanowire Formation using SiGe SiGe/Si Superlattice Fin etch Selective SiGe etch Si Si Si SiGe SiGe BOX Si Si Si SiGe SiGe BOX Si SiGe Si SiGe Si Suspended NWs November

69 Dupre CEA-LETI IEDM 2008 Nanowire FETs Bangsaruntip IBM IEDM 2009 Kelin Kuhn / ECS Meeting / October 10 th,

70 Hashemi/Hoyt MIT IEDM 2008 EDL/ESSDRC 2009 Nanowire FETs Moselund Ecole Polytechnique, Switzerland IEDM 2007 Kelin Kuhn / ECS Meeting / October 10 th,

71 Non-planar options Si SiN HM HfO 2 TiN BOX 27 November

72 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

TFET (Tunneling Field-Effect Transistor) Principle of operation Band-to-band- tunneling through source

Disadvantages Low drive currents Ambipolar conduction Unidirectional conduction Potentially high hot-e -

A KEY question is whether some clever Tunneling barriers combination of Si, Ge, or Si 1-x Ge x can deliver

73 TFET (Tunneling Field-Effect Transistor) Principle of operation Band-to-band- tunneling through source barrier, modulated by gate field Advantages Steep (< 60 mv/dec) sub-threshold slope Large Ion/Ioff ratio Disadvantages Low drive currents Ambipolar conduction Unidirectional conduction Potentially high hot-e - effects Vg Gate Source Drain P + i-inas N Vd Materials choice? A KEY question is whether some clever Tunneling barriers combination of Si, Ge, or Si 1-x Ge x can deliver enough drive current for viable TFETs. Courtsey M. Luisier (Purdue) M. Luisier and G. Klimeck, EDL, 2009 Kelin Kuhn / ECS Meeting / October 10 th,

1.00E -02 1.00E -03 1.00E -04 1.00E -05 1.00E -06 1.00E -07 1.00E -08 0 0.2 0.4 0.6 0.8 1 Best Demonstrated TFETs 32nm MOS @ Vds = 0.

poor [1] S. Mookerjea et al., IEDM 09 [1] K. Jeon, et al., VLSI (11.4.1.-1) 2010 [2] W. Choi et al., IEEE-EDL vol.28, no.8, p.

74 1.00E E E E E E E Best Demonstrated TFETs 32nm Vds = 0.8V Still MUCH lower drive currents than conventional MOS Require band-gap engineering with hetero-junction layers Sub-threshold slope still poor [1] S. Mookerjea et al., IEDM 09 [1] K. Jeon, et al., VLSI ( ) 2010 [2] W. Choi et al., IEEE-EDL vol.28, no.8, p.743 (2007) [3] F. Mayer et al., IEDM Tech Dig., p.163 (2008) [4] T. Krishnamohan et al., IEDM Tech Dig., p.947 (2008) Kelin Kuhn / ECS Meeting / October 10 th,

75 AGENDA Past (Scaling) Present (Planar SiGe S/D) Future Planar Ge channel Non-planar architectures Tunnel FETs Summary Kelin Kuhn / ECS Meeting / October 10 th,

76 Summary Strain from e-sige S/D PMOS is a critical part of modern CMOS technology - replacement technologies must exceed the high bar set by e-sige PMOS. Strained SiGe/Ge PMOS offers a potential mobility advantage over strained Si. However, gate dielectric engineering remains the key roadblock to competitive performance. Non-planar architectures will be of increasing interest for the 15nm node and beyond. Integrating e-sige S/D and/or Si/SiGe channels in non-planar architectures offers significant new challenges. TFETs are gaining visibility as potential ultra-low power devices, leveraging better than 60mV/dec SS. Significant challenges to constructing Si-Ge/SiGe TFETs with competitive drive currents. Kelin Kuhn / ECS Meeting / October 10 th,

77 Questions? Kelin Kuhn / ECS Meeting / October 10 th,

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs

High Mobility Materials and Novel Device Structures for High Performance Nanoscale MOSFETs Prof. (Dr.) Tejas Krishnamohan Department of Electrical Engineering Stanford University, CA & Intel Corporation