Dynamics of Dickson Charge Pump Circuit

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1 Dynamics of Dickson harge Pump ircuit Kenji KASHIWASE, Haruo KOBAYASHI, Nobuyuki KUROIWA, Naoto HAYASAKA, Takao MYONO, Tatsuya SUZUKI, Takashi IIJIMA, and Shuhei KAWAI Dept of Electronic Engineering, Gunma University, -5- Tenjin-cho Kiryu Japan phone: fax: k haruo@elgunma-uacjp Semiconductor ompany, Sanyo Electric orp -- Sakata Oizumi-Machi Ora-Gun Gunma Japan Abstract This paper presents dynamics of Dickson charge pump circuits for high voltage generation Several formulas regarding their output voltage, energy and efficiency in the transient state and the steady state are derived Keywords: harge Pump, High ltage Generator, Power Supply ircuit, State-Space Approach I Introduction harge pump circuits generate higher output voltages than the regular supply voltage [,, 3,, 5, 6, 7, 8, 9, 0,, and they have been used in non-volatile memories - such as EEPROM and flash memories - for their programming and erase operations through their floating gates They are also used for liquid crystal display (LD) systems and low-supply-voltage switchedcapacitor systems that require high voltages to drive analog devices Recently we have developed charge pump circuits for relatively large output current (several ma) for D driver [, 3, Most of MOS charge pump circuits are based on Dickson [, and Fig shows a four-stage Dickson charge pump circuit The drain-gate connected NMOS s (MD - MD5) are used as diodes there, so that the charges can be pushed only in one direction LK and LK are two out-ofphase pumping clocks, whose amplitude is usually the supply voltage V dd, and - are coupling capacitors with the same capacitance of The two clocks push the charge (and hence the node voltage) upward through the MOSFETs When LK goes from high to low and LK from low to high, the voltage at node is settled to V + V, and the voltage at node is to V, where V and V are defined as the steadystate lower voltage at nodes and respectively Both MD and MD3are reverse biased, and the charges are pushed from node to node through MD and the final voltage difference between nodes and is the threshold voltage of MD In this paper we describe the dynamics of Dickson charge pump circuits systematically For transient analysis, we assume that the circuit is ideal, and for steady state analysis, circuit nonidealities such as voltage drop across each switch, parasitic capacitance at each node and output current are incorporated The derived formulas would be useful for design and analysis of charge pump circuits II Basic Study of Power Electronics Before discussing the dynamics of charge pump circuits, we would like to call for the reader s attention to the following two examples to understand the energy dissipation in a circuit which consists of capacitors and switches: Example : Let us consider to charge a capacitor in a R circuit in Fig where the voltage across the capacitor is zero at time t = 0 Its differential equation is given by R d dt V out(t)+v out (t) =V dd, V out (0) = 0, and V out (t) is obtained as follows: V out (t) =V dd ( exp( t R )) The energy E Supply supplied from V dd for t =0to is given by E Supply = V dd because the charge V dd flows from V dd The energy stored in at the steady state (t = ) is given by E = V dd Also the energy E R dissipated through R from t =0 to is obtained by E R = R 0 (V dd V out (t)) = V dd

2 Then we have the following relationships: E Supply = E + E R, E = E R () One half of the energy supplied from V dd is stored in and the other half is dissipated through R Example : Let us consider a circuit in Fig3which consists of a capacitors, and a switch When the switch is off and the voltages across, are V, V respectively, the charges Q, Q and the energies E, E stored in, are given by Q = V, Q = V, E = V, E = V Then the total energy E is given by E = E + E = V + V () Next let the switch turn on, and the voltages across and becomes the same (V M ) at the steady state Then we obtain the followings: Q = V M, Q = V M (3) Since the charges are conserved between the states in Fig3(a) and Fig3(b), we have the following relationships: Q + Q = Q + Q () Then it follows from eqs(3) and () that and V + V = V M + V M V M = V + V + Hence the energies E, E stored in, in Fig3 (b) are given by E = V M = ( V + V ) ( + ), E = V M = ( V + V ) ( + ) Thus the total energy E in Fig3(b) yields to E = E + E = ( V + V ) (5) ( + ) It follows from eqs(),(5) that the energy difference E between the states in Figs3(a) and (b) is given by E := E E = (V V ) (6) ( + ) Note that when V V, then E >0 and the energy E was dissipated through the switch On the other hand, when V = V, E is equal to zero and this is called Zero-lt Switching (ZVS) III Transient Analysis of Dickson harge Pump ircuit This section derives a formula for the node voltage in the transient state of an ideal three-stage charge pump circuit and also shows that one half of the energy E Supply supplied from V dd and clock drivers for t =0 to are stored in the capacitors at t = and the other half is dissipated through the switches from t =0to Proposition : In an ideal three-stage charge pump circuit in Fig, the output voltage node V o (n) and the internal node voltage V (n) atn-th clock cycle are given by V o (n) = (λn + λn )V o(0) + (λ n λn )V (0)+ [ ( + 3 )λ n ( + 3 )λ n +V dd, (7) V (n) = (λ n λ n )V o (0) + (λn + λ n )V (0)+ where [ ( + 3 )λ n ( 3 )λ n +3V dd, (8) λ = +, λ = Proof : See Appendix Remark (i) Since λ < and λ <, as n, λ n 0, λ n 0, V o (n) V dd, V (n) 3V dd (ii) The proof of Proposition in Appendix uses socalled a state-space approach With this approach we can derive output node and internal node voltages at n-th cycle in an N-stage charge pump circuit for any positive integer N Proposition : When the charges in all the capacitors are zero at t = 0 in Fig, we have the following: E Supply = E + E R, E = E R (9)

3 Here E Supply is the energy supplied from V dd and clock drivers for t =0to, E is the energy stored in all the capacitors at the steady state (t = ) and E R is the dissipated power through the switches for t =0 to Proof : See Appendix Remark Propositin is a general case of Example IV Steady State Analysis of Dickson harge Pump ircuit Next we will consider the charge pump circuit at the steady state which includes circuit nonidealities Effects of ltage Drop Across Switch Let us consider the case that the switch is realized with a diode or a diode-connected MOSFET and it has some voltage drop V d when it is ON (Fig5) Proposition 3: (i) For 3-stage charge pump circuit, V o ( ) =(V dd V d ) (0) (ii) The energy dissipation P loss ( ) during one clock cycle T in the circuit at the steady state is given by P loss ( ) =0 Proof See Appendix 3 Effects of Parasitic apacitance Let us consider the case that each node has parasitic capacitance p (Fig6) Proposition : (i) For a 3-stage charge pump circuit, V o ( ) =( 3 p + p )V dd () (ii) The energy dissipation P loss ( ) during one clock cycle T in the circuit at the steady state is given by P loss ( ) = 3 p + p V dd () Remark Example helps us understand intuitively why the parasitic capacitance causes the energy loss given by eq() 3 Effects of Output urrent Let us consider the case that the output node provides load current I out (Fig7) Proposition 5: (i) For a 3-stage charge pump circuit, V o ( ) =( 7TI out )V dd (3) (ii) The energy dissipation P loss ( ) during one clock cycle T in the circuit at the steady state is given by P loss ( ) =8TI out V dd () Remark Examples and help us understand intuitively why the parasitic capacitance causes the energy loss given by eq() Proposition 6 : Efficiency η for a 3-stage charge pump circuit at the steady state is given by Output Power from V o η = Supplied Power from V dd and lock Drivers = 3 TI out (5) V dd Effects of Switch ltage Drop, Parasitic apacitance and Output urrent Altogether Let us consider the case that the charge pump circuit has the switch voltage drop V d, parasitic capacitances p and output load current I out (Fig8) Proposition 7: For a 3-stage charge pump circuit, V o ( ) =(+3 )V dd V d 7TI out + p (6) Proof See Appendix 7 Proposition 8 : Efficiency η for an N-stage charge pump circuit at the steady state is given by η = N p +(N + )( + p)v d TI out +NT Iout N p +(N +)V ddti out + p V dd TI out (7) Proof See Appendix 6 Note that Eq(7) yields to the following: η = Nα+(N + )( + α)βx +Nx Nα+γx (8) where x, α, β and γ are dimensionless, and defined by x := TI out, α := p V dd, β := V d, γ := N ++α V dd Proposition 9 : Effeciency η given by eq(8) has a peak value when x has the following value: x = Nα+ N α + [( β)γ Nαβγα (9) γ Proof By calculating η/ x = 0 and x > 0, we obtain eq(9)

4 We conclude this paper by remarking that Proposition 9 can theoretically explain our measurement result that the efficiency of our charge pump circuit [3 has a peak for a certain value of the output current I out and also for a certain value of the clock period T when the other conditions are fixed We would like to thank K Wilkinson for valuable discussions References [ J F Dickson, On-hip High-ltage Generation in NMOS Integrated ircuits Using an Improved ltage Multiplier Technique, IEEE J of Solid-State ircuits, vol, pp37-378, June 976 [ H San, H Kobayashi, T Myono, T Iijima and N Kuroiwa, Highly-Efficient Low-ltage-Operation harge Pump ircuits Using Bootstrapped Gate Transfer Switches, IEEJ, vol0-, No0, pp (Oct 000) [3 T Myono, S Kawai, A Uemoto, T Iizima, and H Kobayashi, Highly Efficient harge-pump ircuits with Large Output urrent Load for Mobile Equipment Applications, IEIE Trans Electron, vole8-, no0, pp60-6 (Oct 00) [ T Myono, T Iijima, A Uemoto, S Kawai and H Kobayashi, High-efficiency charge-pump circuits by 05 pumping up method, Proc of the 3th Workshop on ircuits and Systems in Karuizawa, pp79-8 (April 000) [5 J T Wu and K L hang, MOS harge Pumps for Low-ltage Operation, IEEE J of Solid-State ircuits, vol33, no, pp (April 998) [6 H Lin, K-H hang and S- Wong, Novel High Positive Pumping ircuits for Low Power Supply, Proc of ISAS99, pp38- (May 999) [7 K-W Min and S-H Kim, A High-ltage Generator Using harge Pump ircuit for Low ltage Flash Memories, IEIE Trans Electron, vole8-, no5, pp78-78 (May 999) [8 T Tanzawa and S Atsumi, Optimization of Word- Line Booster ircuit for Low-ltage Flash Memories, IEEE J of Solid-State ircuits, vol 3, no8 pp , (Aug 999) [9 J S Witters, G Groesenken, and H E Maes, Analysis and Modeling of On-hip High-ltage Generator ircuit for Use in EEPROM ircuits, IEEE J of Solid-State ircuits, vol, no5 pp , (Oct 989) [0 A Umezawa, S Atsumi, M Kuriyama, H Banba, K Imamiya, K Naruke, S Yamada, E Obi, M Oshikiri, T Suzuki, and S Tanaka, A 5-V-Only Operation 06- m Flash EEPROM with Row Decoder Scheme in Triple-Well Structure, IEEE J of Solid-State ircuits, vol 7, no, pp (Nov 99) [ Lauterbach, W Weber and D Romer, harge Sharing oncept and New locking Scheme for Power Efficiency and Electromagnetic Emission Improvement of Boosted harge Pumps, IEEE J of Solid- State ircuits, vol35, no5, pp (May 000) Appendix (Proof of Proposition ) Using the charge conservation law, we have the following state equation in Fig: where Then A := v(n +)=Av(n)+bV dd v(n) := [ [ V (n) V o (n) [, b := n v(n) =A n v(0) + A k bv dd k=0 and eqs(7), (8) are obtained Appendix (Proof of Proposition ) Using the charge conservation law for each cycle, the energy loss E loss (n) and the energy stored in all capacitors E c (n) atn-th cycle are given by and E loss (n) = 6 [0V (n) +5V o (n) +7V dd 8V (n)v o (n) 6V o (n)v dd 8V (n)v dd, E c (n) = [V (n) +V dd (n) V (n)v dd + V o )n) Then considering an initial condition E loss0, E R := E loss (n)+e loss0 =5, n=0 E c := lim E c(n) =5V n dd, and eq(9) is obtained Appendix 3 (Proof of Proposition 3) We have the following state equation in Fig5 v(n +)=Av(n)+Bv m

5 where [ B := 0 When n, we have [, v m := V d v( ) =Av( )+Bv m and eq(0) is obtained Appendix (Proof of Proposition ) We have the following state equation in Fig6: v(n +)=Av(n)+cV dd Then +6 V ddti out + p +V dd TI out η = E load E s ( ) and eqs(5),(7) have been obtained Appendix 7 (Proof of Proposition 7) In Fig8 we have the following state equations: V (n) = V (n)+ V dd V d, c := [ (+ p) + p (+ p) o (n) = V (n)+ V o(n) V d + V dd TI out, ( + p ) V When n, we have v( ) =Av( )+cv dd and eq() is obtained Appendix 5 (Proof of Proposition 5) We have the following state equation in Fig7 [ V (n +) = V o (n +) [ [ V (n) V o (n) When n, we have [ V ( ) = V o ( ) + [ 3 [ + [ 3 [ [ [ V ( ) V o ( ) TI out TI out and eq(3) is obtained Appendix 6 (Proof of Propositions 6 and 8) onsider the steady state in Fig8 Then the energy E load supplied from the output node during one clock cycle T is given by E load =[V dd 8V d +6 V dd TI out TI out + p + p Also the energy E s ( ) supplied from V dd and clock drivers during one clock cycle T is given by E s ( ) =3V dd 3 + p V dd V (n +)= V (n)+ V o + V d, V o (n +)= V o(n) TI out + p Then eq(6) has been obtained Figure aptions Fig: A four-stage Dickson charge pump Fig: A R circuit Fig3: Two capacitors and switch (a) In case that switch is OFF, the voltages across and are V and V respectively (a) In case that switch is ON The charges in and moves so that the voltages across and becomes the same (V M ) and some energy is dissipated through the switch Fig: An ideal three-stage Dickson charge pump circuit Fig5: A non-ideal three-stage Dickson charge pump circuit where voltage drop V d across each switch is considered Fig6: A non-ideal three-stage Dickson charge pump circuit where parasitic capacitance p at each node is considered Fig7: A non-ideal three-stage Dickson charge pump circuit where output load current I out is considered Fig8: A non-ideal three-stage Dickson charge pump circuit where voltage drop V d across each switch, parasitic capacitance p at each node, and output load current I out are considered

6 V MD MD MD3 MD Fig Vd V Vd T time Fig5 Fig R V ut p p p p Fig Fig6 V Iout V V (a) Fig7 VM (b) VM Vd V Vd p p p p Iout Fig3 Fig8

Heap Charge Pump Optimisation by a Tapered Architecture

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