Current Mirrors. For the nmos mirror, 2. If transistors are matched, then + =± +

Transcription

1 Current Mirrors For the nmos mirror, I V V D1 = β1( GS1 th1) / I V V V D = β( GS th) / = V GS1 GS ± I I V V β + =± + D1 D th1 th 1 β If transistors are matched, then β W L I = I = I 1 D D1 D1 β1 W1 L Thus, for a given M1, M can be sized to produce any multiples of I D 1 Design Project P1

2 Differential Pairs Iss = ID 1+ ID I I = I ( I I ) = I I D1 D D1 ss D1 D1 ss I tanh( α( V V )) ss d d tanh(.) is the hyperbolic tangent funtion. (Typically, α = 5 mv. ) Design Project P

3 Basic Transconductance Amplifier The chip design is comprised of three stages High Level ( system specifications, block definitions) Component Level (Architectural/topology, simulations) Layout Level (Cadence LVS, DRC,..) Design Project P3

4 Wide Transconductance Amplifier Use the transistor number to identify the I_ds thru the transistor Design Project P4

5 Wide Transconductance Amplifier I = I I out 7 9 = I I 1 = I tanh( α( V V )) (approximately) 3 1 tanh(.) is the hyperbolic tangent funtion. (Typically, α = 5 mv. ) Use the transistor number to identify the I_ds thru the transistor in the schematic. Current mirrors act as (current) buffers and copiers/reflectors. Dependening on tx sizing, they may scale the input current. Design Project P5

6 Multiplier Use the transistor number to identify the I_ds thru the transistor Design Project P6

7 Multiplier I = I I = ( I ) ( I ) = ( I + I ) ( I + I ) out = ( I I ) + ( I I ) = ( I tanh( V V )) + ( I tanh( V V )) = ( I I ) tanh( V V )) = ( I I )tanh( V V )) = ( I ) tanh( V V ) tanh( V V )) Use the transistor number to identify the I_ds thru the transistor Set V=V4=Vdd/. 0<V1<Vdd, 0<V3<Vdd Design Project P7

8 Current Mirrors For the nmos mirror, I V V D1 = β1( GS1 th1) / I V V V D = β( GS th) / = V GS1 GS ± I I V V β + =± + D1 D th1 th 1 β If transistors are matched, then β W L I = I = I 1 D D1 D1 β1 W1 L Thus, for a given M1, M can be sized to produce any multiples of I D 1 Design Project P8

9 Multiplying Digital-Analog Converter (MDAC) MDAC:. Digital word ddddd k= 4 k= 4 k k Iout = dk I = I dk k= 0 k= 0 I I d 0 By tx sizing design, W k L I : k dk = I = dk I W Lk Design Project P9

10 Multiplying Digital-Analog Converter (MDAC) Comments:. -Each digital (voltage) signal d _k controls a pass transistor for the current. Therefore, in this design, the size of the pass transistors must be similar to the transistors in series. This would result in large chip real-estate! Hint: A better design may place the pass transistors at the red squares in the next figure to activate (or not) a select current mirror. In this design, the pass transistor size can be minimum. Team may explore this possibility with a pass-pull-down tx combo. -Two MDACs can be cascaded in series to generate a digital-to-digital multiplier: I d I I d k= 4 k= 4 k k out1 = k = k k= 0 k= 0 j= 4 k 4 j= 4 j = k j out = out1 j = k j j= 0 k= 0 j= 0 I I b I d b Design Project P10

11 Multiplying Digital-Analog Converter (MDAC) MDAC:. Digital word ddddd k= 4 k= 4 k k Iout = dk I = I dk k= 0 k= 0 I I d 0 By tx sizing design, W k L I : k dk = I = dk I W Lk Design Project P11

12 Active Resistive Loads For two pmos in series, driven by the current Iin, the voltage Vout is derived as follows: I in V out -Using pmos provides larger resistances I D - pmoss in diode configuration form a voltage divider. -Apply KCL to get eqns below. I = I I in SD SD1 I = β ( V V ) / = β ( V V V ) / SD1 1 SG1 thp1 1 DD out thp1 I = β ( V V ) / = β ( V V ) / SD SG thp out thp Design Project P1

13 I in I D Active Resistive Loads V out -assume txs are matched, thus have equal thresholds. Assume also same sizes, thus β = β = β Thus the eqns lead to 1. I = I I in D D1 = ( I + I )( I I ) D D1 D D1 I = β ( V V )( V V /) in DD thp out DD Which is re-written as 1 Vout = Iin + ( VDD /) β ( VDD Vthp ) Thus current is converted into voltage. By sizing the txs one can determine the scaling (slope) for the conversion (over some range of the current. (Simulate your design). Design Project P13

14 I in Active Resistive Loads V out -considering the (equivalent) capacitance of the pmos txs (or explicitly adding a capacitor in parallel to Mp), the equations can be modified to I D Conductance I C V = β ( V V )( V V /) in eq out DD thp out DD Design Project P14

15 pmos floating gates -Use a pmos for a floating gate (FG). -Impossible to program nmos due to specifics of fab. control process techniques. Easier to program a pmos. -Use tunneling to remove electron from FG Vtp is increased. This is used for Global erase. -Use hot-electron injection to place electrons on FG, thus reducing Vtp. This is used for selectively programming each FG in an array. Design Project P15

16 I in Active Resistive Loads V out -considering the (equivalent) capacitance of the pmos txs (or explicitly adding a capacitor in parallel to Mp), the equations can be modified to I D Conductance I C V = β ( V V )( V V /) in eq out DD thp out DD Design Project P16