SCALING of MOS devices requires higher and higher

Transcription

1 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST Impact of Super-Steep-Retrograde Channel Doping Profiles on the Performance of Scaled Devices Indranil De and Carlton M. Osburn, Fellow, IEEE Abstract Super-steep retrograded (SSR) channels were compared to uniformly doped (UD) channels as devices are scaled down from 250 nm to the 50 nm technology node, according to the scheme targeted by the National Technology Roadmap for Semiconductors (1997). The comparison was done at the same gate length L gate and the same off-state leakage current I o, where it was found that SSR profiles always have higher threshold voltages, poorer subthreshold swings, higher linear currents, and lower saturation currents than UD profiles. Using a simulation strategy that takes into account the impact of short-channel effects on drive current, it was found that the improved shortchannel effect of retrograde profiles is not enough to translate into a higher performance over the UD channels for all technologies. Hence, if the effective gate-dielectric thickness scales linearly with technology, retrograde doping will not be useful from a performance point of view. However, if the scaling of the gatedielectric is limited to about 2 nm, SSR profiles can give higher drive current than UD channels for the end of the roadmap devices. Thus, the suitability of SSR channels over UD channels depends on the gate-dielectric scaling strategy. Simulations using a self-consistent Schrödinger Poisson solver were also used to show that the impact of quantum mechanical (QM) effects on the long-channel characteristics of SSR and UD MOSFET s will be similar. Index Terms Channel engineering, MOS device design. I. INTRODUCTION SCALING of MOS devices requires higher and higher substrate dopings to control short-channel effects. As the depletion width of the MOSFET scales down, the substrate doping that determines the threshold voltage also controls the short-channel effects, and the decoupling achieved in earlier technologies by using separate channel implants for threshold voltage control and punchthrough control do not appear feasible. Indeed, simulations reveal that a separate punchthrough implant has only a small effect on device performance and that scaled MOSFET s with the traditional threshold implant and a Boron I/I for the punchthrough have dc characteristics closely resembling uniformly doped (UD) MOSFET s [1]. In the rest of the paper, the UD MOSFET will be taken to approximate a conventional MOSFET with the traditional channel doping scheme. Manuscript received August 19, 1998; revised March 13, This work was supported in part by the National Science Foundation Engineering Research Centers Program through the Center for Advanced Electronic Materials Processing (AEMP) under Grant EEC and the Semiconductor Research Corporation under SRC Contract BP-132. The review of this paper was arranged by Editor K. Shenai. The authors are with the Center for Advanced Electronic Materials Processing, North Carolina State University, Raleigh, NC USA ( ide@eos.ncsu.edu). Publisher Item Identifier S (99) With the substrate doping controlling both the threshold voltage and the short-channel effects in UD MOSFET s, concerns have been raised that in the future the substrate doping required to control short-channel effects will lead to an unacceptably high, or conversely, the substrate dopings required to achieve proper threshold voltages may be insufficient to control the short-channel rolloff [2], [3]. To control the short-channel effects, MOSFET s with a retrograded channel profile (RCP) have been suggested in recent years [4] where the high substrate doping is buried somewhat beneath the surface, leaving a lightly doped region close to the surface. The case of a RCP MOSFET where the transition from the lightly doped surface to the heavily doped substrate is sharp is referred to as the super-steep-retrograded (SSR) profile. SSR profiles have been given different names by different researchers depending on the fabrication technique: delta-doped (DD) MOSFET [5], [6], low impurity channel transistors (LICT s) [7], and atomic layer doped (ALD) MOS- FET s [8]. In this paper, the suitability of SSR is examined for mainstream CMOS technology as it scales in accordance with NTRS guidelines. Section II reviews the arguments presented for the use of SSR profiles over UD profiles in the literature and looks at their shortcomings in making a fair comparison. Section III presents a more meaningful simulation strategy for comparing SSR and UD. In Section IV, the results of such a comparison using classical simulation are examined. Section V compares the impact of quantum effects on UD and SSR profiles. II. DEVICE PERFORMANCE OF SSR AND UD CHANNELS MOSFET s with RCP channel profiles were originally proposed to control latchup in CMOS circuits [9] and later to reduce ionized impurity scattering in the channel [10]. In the deep submicron regime where the mobility is dominated by surface scattering, MOSFET s with RCP profiles have been recognized primarily for their superior short-channel characteristics [2] [8], [11]. This has been attributed to a smaller channel depletion width at a given threshold voltage [2]. However, using both short-channel equations [2] and long-channel equations [12], it has been realized that the higher subsurface doping required in a RCP MOSFET for the same causes it to pinch off at a smaller drain bias due a larger body effect and gives it a lower drive current than a UD MOSFET. The smaller depletion width also results in a poorer long-channel subthreshold swing than a UD device. It will be shown in the results that follow that the same is true for the /99$ IEEE

2 1712 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999 short-channel devices. As a result of the poorer subthreshold slope, an SSR device also has a higher off-state leakage current when compared to the UD device at the same and. We now ask why a retrograde device may be useful for performance enhancement in device scaling even though at the same channel length and, a SSR MOSFET has lower as well as a higher than a UD MOSFET. Although the SSR MOSFET has a slightly higher linear current than a UD MOSFET, that can probably be discounted since circuit speed is generally more strongly influenced by saturation current. Possible answers are given in literature are as follows. References such as [12] state that at any given channel length, a SSR profile has a lower than a UD profile for a specified. However, for a specified, the same as that of the UD profile may be obtained in a SSR at a smaller channel length. While this means having to define shorter channel lengths, the performance benefit would be smaller gate capacitance. This method of comparison fails to consider that at this shorter channel length, a UD profile could give a still higher while maintaining the specified with a higher substrate doping. Other references, such as [2], have compared SSR and UD profiles at the same long-channel and compared the at (where the is established by some acceptable rolloff from a long-channel device or DIBL). This yields a higher current for the SSR because of it having a smaller. Unfortunately, this methodology compares devices which have differing channel lengths. Since, for a given technology, the minimum dimension is already set by the lithography, such a comparison is essentially meaningless. One needs to compare UD and SSR profiles not with the same long-channel, but rather with a similar at the nominal channel length of the technology. Finally, such a comparison between profiles characterizes by using the rolloff from the longchannel device whereas a more accurate comparison is based on the rate of rolloff at, i.e.,. Numerous references suggest that UD devices with acceptable short-channel characteristics have too high a and that SSR devices can allow for lowering this. However, such references do not take the proper scaling of into account, and this leads them to predict much higher for the UD. For example in [3], an unreasonable oxide thickness of 5 nm is used for comparisons at of 100 nm. There are two reasons why an unacceptably high results if the gate oxide is not scaled down suitably with channel length. First, for a given substrate doping, is higher in the case of a thicker gate-dielectric. Second, a higher substrate doping is required to control short-channel effects if the oxide is too thick. References such as [13] claim that SSR profiles give a higher drive current by comparing with the UD case at the same gate overdrive at a given channel length but do not maintain the same between the UD and SSR devices. This is very misleading because when the devices are compared at the same at any given channel length, a much higher subsurface doping is needed for the SSR which results in current degradation due a higher body factor. III. SIMULATION METHODOLOGY A simulation methodology was developed here that compares SSR and UD at the same and and that includes the impact of short-channel effects on. Devices on an IC have fluctuations in the patterned gate length about a nominal value because of some specified tolerances in gate lithography. The devices with the shortest gate lengths,, will generally have the largest (because they have the smallest due to rolloff) while the devices with the largest channel length generally have the lowest drive current. The designer has to ensure that the devices have less than the maximum specified. Then the devices have a lower drive current than the devices because of the increase in channel length and partly because of the increase in with increasing channel length. This minimum is the specified minimum drive current that can be used for computing maximum circuit delay. While a SSR MOSFET does not give any performance enhancement at a given channel length and, a performance enhancement might accrue with this design methodology because as we move from the device to the device, the reduction in drive current attributable to increasing is less with a SSR than that for UD. If the increase in moving from to for the UD is much larger than that for SSR, the SSR MOSFET may have a higher at and, hence, a higher minimum for the given technology. Thus, a design more resistant to short-channel effects can result in better device performance. Higher drive current in SSR also results from the higher inversion layer mobility because of lower doping at the surface. The loss of drive current and the enhancement in shortchannel effects in a RCP MOSFET are functions of the degree of retrograding, the channel length, the thickness of the oxide, and the allowable. At every nominal channel length and oxide thickness, UD and SSR (at different degrees of retrograding) need to be compared before concluding which channel profile gives better performance. In the simulations that follow, scaling parameters suggested by the NTRS [14] have been used (see Table I). The technology parameter is represented by the nominal length of the poly gate. Gate length variations of % about nominal are used. Hence, and refer to devices with gate lengths greater and less than. The effective gate dielectric thickness is scaled at, and the spacer (of oxide material) length is scaled at (see Fig. 1). The extension junction and the deep source/drain junction have a Gaussian profile with electrically active surface concentrations of cm and cm respectively. The characteristic lengths for these Gaussian profiles are tailored in the UD case to give an extension junction depth of and a deep source-drain junction depth of. To be fair, the drain doping profile in the SSR devices are identical to that of the UD case, so that SSR devices actually have a somewhat lower junction depth because of a higher subsurface doping.

3 DE AND OSBURN: SUPER-STEEP-RETROGRADE CHANNEL DOPING PROFILES 1713 TABLE I NTRS GUIDELINES FOR FUTURE SCALING Fig. 1. MOSFET structure used in simulations. The SSR profile is a stepped profile with a lightly doped layer ( cm 01 ) of thickness x j =2 or x j =3 where x j is the extension depth. The technology parameter is the nominal gate length,. The used for each technology is the maximum allowable from Table. I. The retrograde devices have a lightly doped layer cm fixed at either or where is the extension depth. Poly depletion effects are not taken into account. A workfunction of 4.17 ev for n -poly and 5.25 ev for p -poly is used. All simulations are done in a commercial version of the 2-D simulator PISCES [15] using the transverse field-dependent mobility model from the University of Texas at Austin [16], [17]. The substrate doping in the UD and the subsurface doping in the SSR devices were tailored to get a NTRS specified at. With these substrate dopings, the drive current of the device was used as a performance measure of any doping profile. This method of comparing channel profiles allows the reduction of drive current due to short-channel effects to be taken into account. IV. SIMULATION RESULTS The substrate doping required to meet the specifications in NMOS devices is shown in Fig. 2. Clearly, the doping required in the SSR case is higher and increases as the thickness of the undoped layer is increased. The required substrate doping for the UD case increases with shrinking dimensions as expected. For the SSR case, the subsurface doping should increase for smaller channel lengths, but may decrease due to the relaxed specification and the reduced thickness of the lightly doped layer in smaller technologies. Due to the competing factors that come into play, the required doping in the sub- case is nonmonotonic. Fig. 2. Substrate doping required in SSR and UD channels to meet the I o specified in the NTRS. Fig. 3. Subthreshold swing for L0 devices measured with drain biased at V dd. SSR MOSFET s exhibit poorer subthreshold slope than UD MOSFET s. Shown in Fig. 3 is the subthreshold slope for the devices. It shows that when compared at the same and, SSR devices have a poorer turn on. As a result of the poorer subthreshold slope, the SSR devices require a higher at. The subthreshold slope was also found to be poorer for the SSR devices at and (not shown here). The change in the threshold voltage when moving from the device to the device is shown in Fig. 4. Clearly, the SSR devices exhibit smaller rolloff in than the UD devices confirming their superior short-channel characteristics. The SSR devices at have a higher linear current (measured at a 50 mv drain bias), as shown in Fig. 5. This is attributed to lower surface doping and hence higher mobility. The linear currrent generally increases by reducing effective the channel length. However, the linear current actually falls

4 1714 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999 Fig. 4. V t rolloff quantified by change in V t between L0 and L+ devices with drain biased at V dd. SSR MOSFET s show smaller rolloff and, hence, better short-channel characteristics than UD MOSFET s. Fig. 7. Substrate doping required in SSR and UD channels of PMOS devices to meet the I o specified in the NTRS. Fig. 5. Linear current I lin measured at a drain bias of 50 mv for L+ devices. SSR devices show higher I lin because of higher mobility. Fig. 8. Saturation current Isat for L+ devices in PMOS devices. Isat for SSR devices are less than that of UD. Fig. 6. Saturation current Isat for L+ devices. Isat for SSR devices are less than or almost equal to that of UD. at the 50 nm node because the power supply voltage is scaled, whereas it is not feasible to reduce the threshold voltage. The drive current of the devices is found to be lower in SSR than UD MOSFET s for both (not shown) and (Fig. 6) devices. This can be attributed mainly to the higher body factor and the higher of SSR devices. The higher body factor causes the channel of the SSR device to pinchoff at a smaller drain bias than in the UD case [12]. Some current degradation in the SSR devices may also result from the higher spreading resistance because of the lightly doped surface. Fig. 6 shows that the improved short-channel characteristics of the SSR are not enough to translate into a higher at. Increasing effects of velocity saturation and nonscalability of with supply voltage scaling typically reduce drive currents with shrinking technologies. However, in jumping from the 180-nm node to the 130-nm node, the supply voltage is not proportionally scaled (from 1.8 V to 1.5 V), and the allowed off-state leakage current is also relaxed at 130 nm (from 1 na/ mto3na/ m); as a result is slightly higher at 130 nm than at 180 nm. For the PMOS devices the results are qualitatively similar. In Fig. 7 is shown the required substrate doping to meet the target specifications for devices. As in the NMOS case, SSR devices need a higher subsurface doping than UD devices. The drive current at is shown in Fig. 8. Once again, the currents for SSR devices are less than those of UD devices. Other results for PMOS devices are also very similar to NMOS results. For the 50-nm technology in the NMOS case, the SSR and UD designs were compared for cases when is scaled slower than than that suggested by the NTRS. Fig. 9 shows as a function of in the UD and SSR case. The at is maintained at the NTRS suggested value of 10 na/ m. It is found that the SSR devices show an improvement in performance over UD devices as the effective oxide thickness increases. This is because as the increases, shortchannel effects become more severe, and the better shortchannel characteristics of SSR allow for performance gains. The higher current for the SSR case for thicker oxides can also be attributed to higher inversion layer mobility. Finally, with an increase in oxide thickness, the required doping in the SSR case (while maintaining the same ) is considerably

5 DE AND OSBURN: SUPER-STEEP-RETROGRADE CHANNEL DOPING PROFILES 1715 Fig. 9. Saturation current I sat for L + devices. SSR devices show a performance enhancement over UD devices as the effective oxide thickness is increased. Fig. 10. Inversion layer capacitance C inv normalized to C ox (C ox = ox=tox) for classical simulation and QM simulations for SSR and UD profiles in NMOS case. SSR and UD profiles have almost the same capacitance in both the classical and QM case. reduced, and the current degradation due to the body-effect is also less. However, we note that the drive currents with thicker oxides are lower, and it is unlikely that such thick oxides can be used with such a low power supply voltage ( V for the 50-nm technology). V. QUANTUM EFFECTS The simulations performed above employed a classical 2-D device solver which does not take into account the reduction in inversion charge resulting from quantum-mechanical (QM) energy quantization at the dielectric-substrate interface. To compare the impact of QM effects on SSR versus UD profiles we looked at the change in long-channel threshold voltage and the reduction in inversion capacitance (measured on a simple capacitor) as we changed from classical simulation to a self-consistent QM simulation. Only NMOS devices were considered, and the doping profiles were identical to those considered in the simulations of Section IV. All simulations were performed using a self-consistent Schrödinger Poisson solver [18]. Fig. 10 shows the inversion capacitance as a fraction of for the classical and QM case. It is interesting to see that the reduction in inversion capacitance from in the classical case which results from finite inversion layer thickness as well the QM case are almost identical for the UD and the SSR profile. The reason is that devices that Fig. 11. Difference in long-channel V t between that obtained in classical and QM simulations for UD and SSR profiles. have the same have similar threshold voltages and also similar electric fields at the dielectric-silicon interface (this has been confirmed in the case of classical simulations). Both the inversion layer thickness and the reduction in inversion charge are primarily functions of this surface electric field. Shown in Fig. 11 is the difference in long-channel threshold voltages between classical simulation and QM simulation. The differences are essentially the same, suggesting that to a first order the impact of QM effects on SSR and UD profiles will be close as long as the comparison is done for doping profiles that lead to similar off-state leakages in the two cases. This also largely validates the comparisons performed in the previous section. VI. DISCUSSION AND CONCLUSIONS In a uniform doping profile, both the channel depletion width and the threshold voltage are determined by the substrate doping concentration and the two cannot be decoupled from each other. Since the channel depletion width, along with the gate dielectric thickness and junction depth, determines the short-channel effects, the threshold voltage of the device and its short-channel effects cannot be decoupled from each other. Such a decoupling can be achieved by using a nonuniform doping profile where there is high doping at the surface with a lower doping underneath it (high-low profile) or by a using a low doping at the surface with a higher doping underneath it (low-high profile). A uniformly doped profile lies in the middle of this spectrum of doping profiles between the highlow profile and the low-high profile. The traditional channel doping profile consisting of a punchthrough implant followed by a shallow threshold implant gives a high-low doping profile. All retrograde channel profiles are low-high doping profiles. For a given threshold voltage, a high-low doping profile gives a larger depletion width than a uniformly doped profile, while a low-high profile gives a smaller depletion width than a uniformly doped profile. A larger channel depletion width for a given threshold voltage gives poorer short-channel effect but improves the body effect and long-channel subthreshold swing. Conversely, a smaller depletion width improves short-channel characteristics but worsens the body effect because of a higher subsurface doping. The subthreshold slope is also degraded in this case. The impact of depletion width on the short-channel

6 1716 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 8, AUGUST 1999 characteristics is closely looked at in [19]. Better immunity to short-channel effects improves device performance because of a smaller rolloff in the threshold voltage. However, poorer body effect can degrade the device performance because the device pinches off at a smaller drain bias. Hence, any nonuniform doping profile has a tradeoff between its shortchannel effects and its body effect. It has been suggested that in coming technologies the shortchannel characteristics will become unacceptable for target threshold voltages. In such a case, a low-high doping profile i.e., a retrograde doping profile which reduces the channel depletion width may give a more optimal tradeoff between short-channel characteristics and body effect. However, this paper finds that retrograde profiles yield no improvement if the gate dielectric scales linearly with channel length as specified in the NTRS and, in such a case, retrograde profiles do not seem useful from a performance point of view. On the other hand, if the dielectric scaling is limited to 2 nm for the 50-nm technology node, higher current is possible with retrograde profiles because of higher mobility and better shortchannel effects. Hence, retrograde profiles may be useful if the dielectric cannot be linearly scaled with technology. A general conclusion from the simulation results is that for a given gate length and gate length variation, there exists a crossover point in the dielectric thickness, above which a retrograde profile is more suitable and below which a uniform profile is better. A yet more refined statement in the context of nonuniform doping profiles in general would be that at each gate length, gate length variation and gate dielectric thickness, there exists an optimal channel depletion width. Shorter gate lengths, greater gate length variation and thicker gate dielectrics call for smaller channel depletion widths i.e., more retrograded profiles, and vice versa. Comparing devices having the same, the reduction in inversion capacitance and increase in due to QM effects are found to be almost the same for the UD and the SSR case, suggesting that to a first order quantum effects will effect the long-channel characteristics of both doping profiles similarly. However, since the dielectric thickness is effectively increased due to quantum effects [20], the crossover value in the oxide thickness above which a retrograde profile becomes useful, may be lowered. Simulations for the 50-nm technology also predict much lower than the NTRS targeted values of 600/280 A/ m for the NMOS/PMOS case. It is therefore likely that either will have to be raised or the maximum specification somewhat relaxed for the end of the roadmap technology nodes. Either scenario will increase the gate overdrive voltage, and this makes the degradation of drive current due to shortchannel effects less severe. In such a case the use of SSR for performance gain will be yet more redundant. The simulation methodology in this paper focusses on threshold voltage variations arising only from channel length variations. Unfortunately this ignores the effect of the coupling with other sources of statistical fluctuations. Two such effects that can be expected to become more dominant for sub- 100-nm CMOS are dielectric thickness variations [21] and random dopant distribution [22]. The effects of random dopant distribution also needs to be considered in comparing uniform and retrograde profiles since both analytical equations and experimental data [23] predict reduced fluctuations with retrograde profiles. On the other hand, fluctuations in threshold voltage arising from variations in the thickness of the lightly doped layer [24] is peculiar only to retrograde profiles, and also deserves assessment. ACKNOWLEDGMENT The authors would like to thank Y. Taur of IBM for helpful discussions. REFERENCES [1] K. F. Yee and C. M. Osburn, Response surface based optimization of 0.1 m NMOSFET s with thin gate dielectrics, in Proc. TECHCON, [2] C. H. Wann, K. Noda, T. Tanaka, M. Yoshida, and C. Hu, A comparative study of advanced MOSFET concepts, IEEE Trans. Electron Devices, vol. 43, p. 1742, Oct [3] J. A. Lopez-Villanueva, F. Gamiz, J. B. Roldan, Y. Ghailan, J. E Carcellar, and P. Cartujo, Study of effects of a stepped doping profile in short-channel MOSFET s, IEEE Trans. Electron Devices, vol. 44, p. 1425, Sept [4] G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, Indium channel implant for improved short-channel behavior of submicrometer NMOS- FET s, IEEE Trans. Electron Devices, vol. 14, p. 409, Aug [5] K. Noda, T. Uchida, T. Tatsumi, T. Aoyama, H. Miyamoto, and I. Sasaki, 0.1 m delta-doped MOSFET using post low-energy implanting selective epitaxy, in Proc. Symp. VLSI Technol., 1996, p. 19. [6] R. Kircher, J. Moruta, M. Foruno, K. Aizawa, M. Kato, A. Horinouchi, and S. Ono, In-situ doping of epitaxial silicon by low-temperature LPCVD for the fabrication of delta-doped MOSFET s, in Proc. Int. Conf. SSDM, 1991, p [7] M. Aoki et al., Design and performance of 0.1 m CMOS devices using low-impurity channel transistors, IEEE Electron Device Lett., vol. 13, p. 50, Jan [8] K. Yamaguchi, Y. Shiraki, Y. Katayama, and Y. Muriyama, A new short-channel MOSFET with an atomic-layer-doping impurity profile, Jpn. J. Appl. Phys., vol. 22, pp , [9] W. H. Chang, L. K. Wang, and R. A. Wachnik, Latch-up studies in 0.5 micron gate CMOS technology with retrograde n-well, in Proc. 1st Int. Symp. ULSI Sci. Technol., 1987, p. 80. [10] G. G. Shahidi, D. A. Antoniadis, and H. I. Smith, Electron velocity overshoot at room and liquid nitrogen temperatures in silicon inversion layers, IEEE Trans. Electron Devices, vol. 9, p. 94, Feb [11] B. Agrawal, V. K. De, and J. D. Meindl, Device parameter optimization for reduced short-channel effects in retrograde doping MOSFET s, IEEE Trans. Electron Devices, vol. 43, p. 365, Feb [12] S. Venkatesan, J. W. Lutze, C. Lage, and W. J. Taylor, Device drive current degradation observed with retrograde channel profiles, in IEDM Tech. Dig., 1995, p [13] T. Skotnicki and P. Bouillon, Electrical performances of retrograde versus conventional profile MOSFET s, in Proc. Symp. VLSI Technol., 1996, p [14] National Technology Roadmap for Semiconductors, Semiconductor Industry Assoc., San Jose, CA, [15] ATLAS 4.0, Silvaco Int., Santa Clara, CA. [16] H. Shin, A. F. Tasch, C. M. Maziar, and S. K. Bannerjee, A new approach to verify and derive a tranverse field dependent mobility model for electrons in MOS inversion layers, IEEE Trans. Electron Devices, vol. 36, pp , June [17] V. M. Agostinelli, H. Shin, and A. F. Tasch, A comprehensive model for inversion layer hole mobility for simulation for submicrometer MOSFET s, IEEE Trans. Electron Devices, vol. 38, pp , Jan [18] UTQUANT 2.0, Univ. Texas, Austin, [19] Z. Liu, C. Hu, J. Huang, T. Chan, M. Jeng, P. K. Ko, and Y. C. Cheng, Threshold voltage model for deep-submicrometer MOSFET s, IEEE Trans. Electron Devices, vol. 40, pp , Jan [20] M. J. Van Dort, P. H. Woerlee, and A. J. Walker, A simple model for quantization effects in heavily-doped silicon MOSFET s at inversion conditions, Solid State Electron., vol. 37, p. 411, 1994.

7 DE AND OSBURN: SUPER-STEEP-RETROGRADE CHANNEL DOPING PROFILES 1717 [21] R. Sitte, S. Dimitrijev, and H. B. Harrison, Device parameter changes caused by manufacturing fluctuations of deep submicron MOSFET s, IEEE Trans. Electron Devices, vol. 41, pp , Nov [22] X. Tang, V. K. De, and J. D. Meindl, Effects of random MOSFET parameter fluctuations on total power consumption, in Proc Int. Symp. Low Power Electron. Des., pp [23] K. Takeuchi, T. Tatsumi, and A. Furukawa, Channel engineering for the reduction of random-dopant-placement-induced threshold voltage fluctuation, in IEDM Tech. Dig., 1997, p [24] J. R. Brews, Sensitivity of subthreshold current to profile variations in long-channel MOSFET s, IEEE Trans. Electron Devices, vol. 43, pp , Dec Indranil De was born in Trivandrum, India, in He received the B.Tech. degree from the Indian Institute of Technology, Kanpur, in 1994, and the M.S. degree from Duke University, Durham, NC, in 1994, both in electrical engineering. He is currently pursuing the Ph.D. at the North Carolina State University, Raleigh, also in electrical engineering. His research focusses on device design and process integration issues for sub-100-nm CMOS. Carlton M. Osburn (M 85 SM 88 F 98) received the B.S. degree in engineering sciences in 1966 and the Ph.D. degree in electrical engineering in 1970, both from Purdue University, West Lafayette, IN. He subsequently joined IBM Research as a Research Staff Member studying the dielectric properties of insulators. He was Manager of Exploratory Fabrication Technology at IBM Research with responsibility for research studies and fabrication of advanced semiconductor devices. In this capacity, he was responsible for managing the Yorktown silicon processing facility. He became Professor of Electrical and Computer Engineering, North Carolina State University, Raleigh, in 1983, where he was assigned as Director of Advanced Semiconductor Technology at the Microelectronics Center of North Carolina from 1983 to He has published over 130 papers and has 24 patents and patent publications. Dr. Osburn received an honorable mention as Eta Kappa Nu s Outstanding Electrical Engineer of the Year in In that same year, he also received the T. D. Callinan Award from the Dielectrics and Insulation Division of the Electrochemical Society. He received the 1989 Maurice Simpson Award of the Institute of Environmental Sciences and the Electronics Division Award of the Electrochemical Society in He became a Fellow of the Electrochemical Society in He is currently Vice President of the Electrochemical Society where he is the past Chairman of the Executive Committee of the Electronics Division, and he is a member of Sigma Xi. He previously served on the Semiconductor Research Corporation s University Advisory Board.