Technology Choices, Challenges and Timing Requirements for Nanolithography at the 32nm Node and Beyond

Transcription

1 Technology Choices, Challenges and Timing Requirements for Nanolithography at the 32nm Node and Beyond Christof Krautschik Technology & Manufacturing Group External Programs Intel, Santa Clara, CA October 7, 2009 Semicon Europa (Dresden, Germany) 1/36

2 Outline Moore s s Law & the R&D Pipeline (the cost reduction engine) Intel Lithography Roadmap & Technology Choices Immersion Lithography (193i) & Double Pattering (DP) EUV Lithography (EUVL) Summary & Conclusions 2/36

3 Moore s s Law - The cost reduction engine 3/36

4 Moore s s Law Reduced cost is one of the big attractions of integrated electronics, and the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. Electronics, Volume 38, Number 8, April 19, /36

5 Transistors/Die Moore s s Law Spans Multiple Technologies µm 13 Bipolar PMOS NMOS CMOS Voltage Scaling Data (Moore) Memory Microprocessor 1µm 100nm 10nm $ Pwr Eff Scaling Materials Innovation & Source: WSTS/Dataquest/Intel Beyond CMOS? Spin based? Molecular? Other? 10 As the 10 number of transistors 10-1 goes UP Price per transistor goes DOWN /36

6 Suppliers Nat l Labs Unwavering Commitment to Invest in R&D Pipeline Internal Investment University Consortia Beyond 11nm External Research Materials Equipment Structures Processes Pipeline designed to capture and refine innovations Internal Research RP nm 22nm 32nm Pathfinding RP1/D1D Development D1D 45nm Manufacturing D1D/Fabs 6/36

7 Staged Investment Aligned to Risks Step 5 Step 4 Step 3 Step 2 Step 1 External Research $/Year ~ 10 7 Research ~ 10 8 Pathfinding Development Manufacturing ~ 10 9 ~ Risk & Options High Moderate Low Create very early on options externally Evaluate options, collaborate externally Focus on choices, reduce risk Synchronize and integrate Copy exactly, ramp rapidly 7/36

8 Silicon R&D Pipeline 65nm 45nm 32nm 22nm 16nm 11nm Manufacturing Development Research A wide range of technology options are needed in the R&D pipeline to ensure the continuity of Moore s Law. 8/36

9 Consortia Landscape MARCO JR NRI March 2005 niac i IRAI 9/36

10 Lithography Roadmap & Technology Choices 10/36

11 Lithography: Key Driver to Enable Patterning Half-Pitch Reduction g-line (435) i-line (365) DUV (248) EUV DSA E-beam NIL 193i DP 11/36

12 Intel Lithography Roadmap Tech. Node MT1 HP (nm) k1 Potential Approaches Insertion Date 45 nm 80 nm nm, NA= nm 56 nm nm 1.2NA nm 40 nm nm 1.30NA DP or SE w/ Low 2011 k1 16 nm 28 nm 0.52 EUV 0.25NA or 193nm 1.30NA DP nm 20 nm 0.37 EUV > 0.25NA or TBD nm 14 nm TBD EUV TBD 2017 HP = λ k1 NA Intel Metal 1 Half Pitch Scales ~0.7x per Generation from 45 nm HP Intel will Continue to Monitor all Emerging Lithography Technologies 32nm SRA Cell:0.182 um 2 cell size 12/36

13 193 Immersion & Double Patterning 13/36

14 Wafer Immersion Causes Defects! 14/36

15 Steady Improvement in Immersion Defects Levels at the 32nm Node 15/36

16 Rapid SRAM Yield Improvement 90 nm 65 nm 45 nm 32 nm Defect Density (log scale) 2 year Higher Chip Yield nm yield improvement on track for 4Q09 production 16/36

17 32nm Overly Improvements 17/36

18 DPPD vs. SBPD Process Flows Most mature double patterning methods are either LELE (Litho/Etch/Litho/Etch) or LFLE (Litho/Freeze/Litho/Etch) Line DP can be either. Space DP has to be LELE Key challenges are process complexity and synthesis issues in splitting original pattern into two masks Interconnect design rule density is critically dependent on shorting margin between vias and adjacent metal lines Transistor parameters can be affected by asymmetry between the source and drain regions Resist HM Etch X-section LFLE LFLE 29 nm HP 18/36

19 Spacer-Based Pitch Division Patterning Space H/M removed 30 nm L/S Advantages Edge placement accuracy goes (approximately) as ΔCD/2 can be much more accurate than overlay especially for patterning techniques like alternate phasesshifting. Likely to require fewer masks even with trim requirement. Process demonstrated and reasonable from integration standpoint Disadvantages Can only do one feature size or one space difficult for random logic layouts Requires trim mask that could be complicated for random Layouts 19/36

20 Resolution Limits & Challenges for DP/DE Resolution Limits Classical Single Exposure patterning has a theoretical limit of D Patterning (Memory) k1 ~ D Patterning (Logic) ~ DP will reduce k1 from ~0.30 to ~0.20 Challenges Tighter Overlay Requirements: HP/3 ~HP/20. CD control below 50nm Throughput, defects/yield, CoO D Patterning k 1 Limits k1 theoretical k1 manufacturing 0.4 2D Patterning k 1 Limits 0.3 k1 theoretical k1 manufacturing k DE materials k X Exp 2X Exp 2X Pattern 3X Pattern 4X Pattern 0.0 1X Exp 2X Exp 2X Pattern 3X Pattern 4X Pattern Patterning Technique Patterning Technique 20/36

21 EUV Lithography 21/36

22 Micro & Full-Field EUV Tools are Main Vehicles to drive EUV Development Intel s s NA=0.30 EUV Micro Exposure Tool Operational since Jan at Intel, Oregon Nikon EUV 1 (Kumagaya) ASML EUVL Alpha Tool (IMEC) Intel MET Nikon EUV1 ADT 1 Field size 600 x 600 μm 2 26 x 33 mm 2 26 x 33 mm 2 NA Illumination 0.36/0.55 annular sigma+oai 0.5 disk Flare ~7% ~12% ~16% Overlay No Yes Yes 22/36

23 Intel MET : Experimental Conditions λ = 13.5 nm 0.3 NA with 10% Area Central Obscuration Annular Illumination (0.36/0.5) Low Flare ~ 3 (DF) - 7% (BF) Field Size = 600 um x 600 um Developer = NMD-3 TOK 1123 E0 ~ 5.90 mj/cm 2 (2008 LBNL/NIST New Dose Calibration) 2009 Upgrades New EUV collector installed Intel MET Dose Delivery Log New outer shell extended σ outer from 0.55 to 0.65 and has enabled 22nm HP resolution with quadrupole illumination This is the first step in preparation for 0.5 NA MET projection optics (2010) that will enable 14nm HP resolution > 250 Resists Screened in 08. Goal > 500 in 09 23/36

24 Intel MET + Resist Exhibits 22nm HP Resolution % Contrast ILS 30nm HP 28nm HP 26nm HP 24nm HP 22nm HP 20nm HP New Intel MET Quadrupole illumination enables 22 HP resolution 24/36

25 EUV Resist Outgassing Rate 30 hp Champ ASML spec Albany ROX data scaled to HVM outgassing rate shows 30 hp champion is passing existing HVM EUV outgassing target. In general, underlayers + negative tone CARs tend to demonstrate lower outgassing rates. Continuous improvement required to consistently meet both RLS and OR targets for 32 HP and below. 25/36

26 EUV Mechanism * Provides RLS Gain With No Sensitizer With Sensitizer nz 32 ~17.7 Resist A S=13.8 mj; L<5.5 nm 40 NM HP Dose (mj/cm2) Resist Sensitivity Improved 30-50% via Addition of EUV Sensitizing Agents No Loss In Resolution or Degradation in LWR Multiple Suppliers Achieved similar performance nz 32 ~6.3 Resist B S=7.0 mj; L<5.0 nm * Kozawa, et al. JVSTB 25, 2481 (2007) 26/36

27 LWR Reduction Techniques * No Treatmen t Etch/Trim Vapor Hardbake Ozonation Rinse Explored several techniques with leading EUV resist platform Physical (Etch/Trim, Hardbake) Photoresist chemistry independent Chemical (Vapor, Ozonation, Rinse Agent) Photoresist chemistry dependent Techniques that reduce LWR by 20% are worth pursuing Technique LWR reduction (nm) %LWR reduction Etch/Trim Vapor smoothing Hardbake Ozonation Rinse Largest Improvement Observed to date with Rinse Agent * Chandhok et al, J. Vac. Sci. Technol. B, (Nov 2008) 27/36

28 General Mask Specifications: Substrate: Intel Mask Pilot Line & EUV Reticle Specs Intel mask pilot operational since EUV blank starts expected to reach 100. Intel uses absorber coated blanks from suppliers. LTEM Multilayer: 2.5nm Ru capped full ML 40-pairs of Mo-Si Absorber: 87nm TaON/TaN Backside coating: 70nm CrN Final mask EUV peak λ of nm ML: 63.9% Absorber: 0.6% Blank Starts Blank Starts Year forecasted 32 nm Node EUV CH Mask 28/36

29 Intel s s EUVL Mask Pilot Line 29/36

30 OPC minimal due to k 1 ~1 0 nm hammerhead 9 nm hammerhead 18 nm hammerhead Rule based OPC 1. CD bias 2. Corner rounding hammer-head head 3. ETE pull-back 30/36

31 Staggered trenches nm pitch 193nm POR EUV Less corner rounding with EUV 31/36

32 Particle adders associated with Reticle Handling on ADT blank inspection data Procedure Segmented studies Shipping Transfer to reticle boxes at IMEC 50 cycles of load/unload on ADT with clamping Pre and post scans quality area of 142x142 mm 2 with Intel Lasertec M % capture rate for 7 pixels ( 100 nm and above) On average the adders were: Shipping ~ 7 particles Transfer to reticle boxes ~ 4 particles Load/clamp/unclamp/unload cycle on ADT ~ 1 particle added per cycle Load/Unload adders can be reduced if reticle is in library during lifetime - Need a large reticle library All adders can be cleaned off with standard wet chemistries 32/36

33 EUVL Pellicle Development Full Size Pellicle Testing for different Stand-Off Distances Ni Mesh High risk/benefit backup project Ni honey comb mesh with ~50 nm thickness Si membrane. Full size pellicle demonstrated with > 70% single path transmission. Stand-off distance impact currently being studied experimentally on ADT tool impacts CD control. 33/36

34 EUV Litho - Key Infrastructure Gaps SEMATECH s s EUV mask infrastructure strategy is to obtain support from various partners (public and private) Commit most of SEMATECH s s Litho budget to mask infr infrastructure over the next four years. Need industry consensus on required funding to bridge gaps 3 34/36

35 EUV Critical Issues and EUV Focus Areas th International EUVL Symposium Program Steering Committee. Lake Tahoe, October 1, /36

36 Summary & Conclusion Moore s s Law expected to continue at current 2-year 2 cadence well towards the end of next decade. Many innovations in materials & processing are needed besides the capability to pattern smaller dimensions. Immersion lithography entering HVM & approaching dry patterning performance. 193i is expected to carry current roadmap through at least the next two technology generations for logic technology. EUV lithography seems to be the most promising wavelength to become the successor to 193i Suffers from many infrastructure & technical challenges that can only be solved by the industry as a whole (source, mask tools, investments, timing ). Sematech addressing some of the major gaps in the photomask area. 36/36

37 Thank You 37/36

38 FT Example EUV Film Thickness Effects 50 nm HP 80 nm 60 nm 40 nm 20 nm CD (nm) LWR (nm) Dose (mj/ cm 2 ) NODE PC (AR=2) HP 30 HP 20 HP 10 HP 50 nm HP Balance increased film thickness (FT) for max absorption vs. pattern collapse Acceptable levels of dark loss can become a problem in thin films Must understand and account for thin film effects -- film homogeneity, diffusion, thermal / mechanical properties Continually assess FT/ AR; However, reduction in FT may not be possible due to thin film / confinement effects 38/36

39 Trends in EUV Mask Blank Defect Levels Metrology & 2G Deposition tools limit rate of progress and HVM insertion. 39/36

40 EUV Litho - Key Infrastructure Gaps 1. Source readiness: funded by suppliers 2. Zero defect reticle process capability: funded by Intel and is 2009 internal focus 3. EUV AIMS and 3G blank inspection: not funded (cost ~ $150M full industry enabling cost) 4. Blank defect improvement trend: insufficiently funded by suppliers (cost is unknown ~ $50M) 5. Fab reticle quality control infrastructure: not funded (cost ~ $10M single tool cost) 6. Sematech driving Mask EUV Infrastructure effort as of July 09. Technical gaps, especially on the mask defectivity and inspection fronts, will limit EUV HVM insertion if not addressed in time 4 40/36