Double patterning for 32nm and below: an update. ASML US Inc, 4211 Burton Dr. Santa Clara, CA, USA. IMEC vzw, Kapeldreef 75, B-3001 Heverlee, Belgium;

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1 Double patterning for 32nm and below: an update Jo Finders (a), Mircea Dusa (b) Bert Vleeming (a) Henry Megens (a) Birgitt Hepp (a) Mireille Maenhoudt (c), Shaunee Cheng (c), Tom Vandeweyer (c) (a) ASML, De Run 1110, 5503 LA Veldhoven, The Netherlands (b) ASML US Inc, 4211 Burton Dr. Santa Clara, CA, USA (c) IMEC vzw, Kapeldreef 75, B3001 Heverlee, Belgium; ABSTRACT Double patterning lithography either with two litho and etch steps or through the use of a sacrificial spacer layer, have equal complexity and particularly tight requirements on CDU and Overlay. Both techniques pose difficult challenges to process control, metrology and integration, but seem feasible for the 32nm node. In this paper, we report results in exploring CDU and overlay performance at 32nm ½ pitch resolution of two double patterning technology options, Dual Photo Etch, LELE and sidewall spacer with sacrificial layer. We discuss specific aspects of CD control present in any double patterning lithography, the existence of multiple populations of lines and spaces, with overlay becoming part of CDU budget. The existence of multiple and generally uncorrelated CD populations, demands utilization of full field and full wafer corrections to bring together the CDU of these multiple populations in order to meet comparable 10% CDU as in single exposure. We present experimental results of interfield and intrafield CD and overlay statistical and spatial distributions confirming capability to improve these distributions to meet dimensional and overlay control levels required by 32nm node. After compensation, we achieved a CDU control for each population, of 2nm or better and 3nm overlay on multiple wafers and multiple state of art, hyper NA immersion scanners. Results confirmed our assumptions for existence of multiple CDU populations entangled overlay into CDU. Keywords: Double Patterning Lithography, DPL, LELE, Spacer SelfAligned, Line/Space CDU populations, DoseMapper, Gridmapper, XT:1900i, XT:1700i 1. INTRODUCTION Currently, 45nm memory designs are pushing resolution down to 0.28 k 1 for regular 1D patterns (flash memory) and 0.31 k 1 for regular 2D patterns (DRAM). These dimensions can be resolved with single exposure water immersion lithography scanners (1.3.<NA<1.35). In contrast, single exposure below 40nm, necessitates either scanners working using fluids with refractive index higher than water, or EUV tools. As such tools are not available in time to continue with aggressive resolution shrink, technologists are looking at Double Patterning Lithography to stay on the ITRS roadmap. DPL technique has been proposed before [1], but it gained much more attention recently because no other single exposure solution is available [2,3,4,5] In DPL, each individual litho step takes place at a robust k 1 factor of 0.35 to 0.4, with a resulting final ½ pitch resolution below k 1 =0.25. Compared to single exposure low k 1 lithography, working at k 1 around 0.40 is favorable for lithographers, Optical Microlithography XXI, edited by Harry J. Levinson, Mircea V. Dusa, Proc. of SPIE Vol. 6924, , (2008) X/08/$18 doi: / Proc. of SPIE Vol

2 but is coming with added process complexity, significantly lower process tolerance, more metrology and subsequently cost increase. Decision on adopting a lithography double patterning scheme is not anymore determined by litho, but by device integration, layout topology, polarity of critical layers and requirements to minimize the impact of dimensional variability on device CDU for either a line or space pattern. Double patterning schemes have been proposed for Flash and DRAM applications [2,3]. Amongst these, the litho DPL scheme (LithoEtchLithoEtch, LELE) and the selfaligned spacer/trim DPL scheme (pattern sacrificial layer sidewall deposition etch back, then trim) are presented schematically in Figure 1(a) and 1(b). LELE scheme shown in figure 1(a) employs a positive tone resist process. A 1:1 L/S pattern on the mask is exposed to ~1:2 L/S and then etch trimmed down to ~1:3 L/S ratio (steps 1,2,3). This is followed by a 2 nd litho and etch (steps 4, 5). The selfaligned spacer scheme shown in Figure 1(b) is similar to the LELE during patterning steps 1 to 3. Further on, a number of nonpatterning process steps replace LELE step 4 and 5, by spacer steps 4 and 5, where a thin, conformal spacer layer is being deposited against the sidewalls of a sacrificial hard masks which is removed in step 5.. Positive litho LELE DPL Spacer 1 st Litho: Resist Barc HM 1:1 L/S 1 st litho: Expos 1 2 Resist Barc Sacrificial HM Electric layer HM Poly SiO2 1 st etch + Trim to 3 Sacrificial HM Electric layer 2 nd litho 4 Spacer Deposition and etchback Pitch split after 2 nd LE 5 Pitch split after Sacrificial removal Figure 1: Schematic representation of a lithobased (a) and spacer (b) DPL process options. Both processes in Figure 1 are considered positive tone where the exposed and etched patterns in steps 1 to 3 are defined by opaque mask structures. During steps 1 and 2, CD target for the mask pattern and litho exposure are optimized through biases determined by requirements to maximize lithography latitudes and to account for etchtrim process. Steps 4 and 5 are mainly defined by specific device integration requirements, which often are defined by its layout characteristics. In addition to the positive tone, there are also negative tone DPL schemes for both LELE and for selfaligned spacer trim technique [4,5,6], where the line patterns become spaces and viceversa. Adoption of a positive or negative DPL scheme is generally dependent on device characteristics: layout topology, process integration flow, electrical operation. Where lithography contributes is in providing the required resolution with a level of dimensional control that is most critical for device electrical operation, i.e., control for lines CD, spaces between lines, or both. Proc. of SPIE Vol

3 2. DUAL CD DISTRIBUTIONS FOR LINES AND SPACES Primary characteristic to any double patterning lithography scheme is the existence of dual populations for line and for their adjacent spaces. In addition, the variance of linecd population is uncorrelated to the variance of spacecd populations. Generally, when calculating CDU budget, one can take into account the presence of four populations, two for lines and two for spaces. However, when considering a specific DPL approach, the line or space CD population could show a certain level of correlation, such as in LELE scheme, where spacecd populations are correlated through the overlay error between laye1 and layer2. Likewise, in the spacer scheme, the linecd populations are correlated through the conformality of the spacer layer deposition along the edges of the sacrificial pattern. Figure 2 exemplifies the concept of bimodal CD populations in a LELE scheme Line population # ISO IS CD [nm] Line population #2 Space populations #1 and #2 Figure 2. Bimodal linecd distribution occurs when CD differs in the two exposures and etch steps. The line populations are different in mean CD and in statistical and spatial distributions. Additionally, overlay error creates a bimodal CD distribution for space populations. 3. CDU BUDGET BREAKDOWN First attribute of any double patterning scheme is the creation of a single device layer from multiple patterning steps. Second attribute is the direct contribution of overlay, or overlaytype errors, to the CD variation of the final pattern. This is more noticeable in LELE scheme where an overlay error directly modifies the critical dimension of a space or of a line, function of process polarity, positive (= printing lines), or negative (= printing trenches). In spite of the fact that selfaligned spacer DPL scheme, doesn t use a 2 nd patterning step, CD variations during 1 st patterning step, can generate a pitchwalking occurrence with an induced CD error on spaces between spacerdefined lines, that creates an overlaytype of error, comparable to LELE scheme. Third attribute is a consequence of the first two and implies CDU calculation from pooling two adjacent patterns within 2*pitch distance in order to capture all dimensional errors of a DPL final pattern which consists from two adjacent linespace pairs. Based on the above attributes, we estimated CDU for two positive tone schemes, Spacer and LELE see Table 1. We derived the CDU for lines and spaces for a target CD of 32nm L/S, using Monte Carlo simulations [7,8]. For all budget components, we assumed an acceptable level of variations of 10% with variations described by Gaussian distribution and 3σ values,. Contribution of track and etch to CD errors was assumed to be 2.4nm (3σ). Furthermore, for LELE, a nominal CD offset of 0.8nm was predicted to be present between averages of line 1 and line 2 CD populations. Proc. of SPIE Vol

4 With these assumptions, Table 1 shows the presence of two line and two space populations as well as the effect of an overlay error to space CDU in LELE scheme and of pitchwalking, overlaylike error reflected as spaces CD error in the spacer scheme. In the following sections we will describe the experimental work to validate these assumptions as well as the magnitude of contribution and total CDU errors. Table 1: Predicted CD Populations with contributions from primary components Estimation for 32nm ½ pitch L/S pattern exposed with 1.35NA Error component Dose Focus Track and etch process Spacer deposition (+ multiple etch steps) Mask CDU (1x) (assumes MEEF of 1.4) Mask registration and overlay (1x) Scanner overlay CDU lines (nm) CDU spaces (nm) Positive Tone Spacer Lines Spaces Positive tone LELE Lines Spaces EXPERIMENTAL SETUP: KEY FOR PROCESS CONTROL To generate experimental proof data for 32nm DPL process performance, we used multiple litho clusters with multiple reticles and multiple etchers. This was primarily employed to account for process complexity and available tool setprocesses. In addition, by using multiple tools and processes, we obtained more statistical data and become more confident in the final results. Experimental setup is described in Table 2. Proc. of SPIE Vol

5 Table 2: Experimental context Exposure Multiple XT:1900i (ASML VHV) XT:1700i (IMEC) Target: 32nm L/S: annular 1.2 NA XYpol 0.8/0.5 Reticle Track Etch Metrology 6% Attenuated PSM multiple tracks; interfaced to XT:1900 and XT:1700 ASML: LELE IMEC: LELE and Spacer CDSEM 64nm L/S Process Control DoseMapper GridMapper Intrafield and Interfield dose and grid corrections A key aspect of the experimental setup is the metrology characterization of each tool and process such that their contribution to final CDU distributions is know and can be compensated. 5. OVERLAY CONTROL AND LELE SPACE CDU For space CDU control in LELE, the scanner overlay and mask registration are crucial contributors as illustrated in Table 1. The DPL overlay was measured on the final 32nm ½ pitch pattern by CDSEM using two pitch measurements (7). Results are depicted in Figure 3. The CDSEM measures the two pitches (pitch left and pitch right). From this the onresolution overlay is constructed : 2.9nm (X, mean +3σ) and 3.0nm (Y, mean +3σ) / '(L rt I!_1. / It 7 if K \7rAt t 7 : 6 Figure 3: Experimental overlay for 32nm ½ pitch created by LELE, as calculated from the two CDSEM pitch measurements (2579 measurement points across the wafer). This LELE experiment was repeated on multiple Twinscan XT:1900i awith overlay being evaluated on multiple wafers and with two metrology sampling scheme Figure 4. Proc. of SPIE Vol

6 XT:1700i CDSEM 2579 XT:1900i #1 XT:1900i, 4 CDSEM 332 meas Same wafer, different sampling XT:1900i, #2 CDSEM 2579 Figure 4: experimental DPL overlay for 32nm ½ pitch by LELE, multiple exposure tools and multiple wafers. Different sampling schemes were used; full: 2579 SEM measurements, reduced sampling for multiple wafers: 332 SEM measurements. For one wafer; the results of the two sampling schemes are compared. For Twinscan XT:1900i, we observed consistent and repeatable DPL overlay around nm compared to 4 4.5nm overlay from Twinscan XT1700i [8] and DPL Overlay numbers were similar over multiple wafers and on two 1900 scanners. Bearing in mind that XT:1900i SMO is in 3 to 4nm range, we are confident that we can achieve the 3nm overlay required by DPL LELE scheme. Since the full DPL flows on multiple Twinscan XT:1900i make use of the same reticle set; we could pinpoint the reticle contribution by evaluating the common intrafield overlay fingerprint. The experimental result of 1.5nm 3σ is in line with our expected contribution from Table 1 and with reticle registration data [10,11] 6. LELE CDU CONTROL To complete our study into the CDU control in a LELE scheme, we evaluated the reticle, lithocluster and etch contributions as they are expected to have the largest contributions to the CDU of the lines a) Reticle contribution In the course of our studies three reticle sets have been used. Characteristic CDU fingerprints are plotted in Figure 5 for a single plate of each set. Previous studies [8,9,10] has shown that when fingerprint of the two reticles in a set are highly correlated, contribution of reticle CDU to wafer CDU is minimized to 1nm or less. Proc. of SPIE Vol

7 I I U I. Figure 5: reticle CD fingerprint for three DPL reticle sets, measured with reticle CD SEM (nm CD@1X) Left: 3σ=0.9nm, Middle 3σ=0.6nm [9,10], Right 3σ=1.9nm [7] Left set has been used for LELE results in this paper. Middle is used to gather experimental results for spacer process. Since the MEEF for our LELE process is 1.5 ±0.2, the reticle contributes significantly to our CDU budget. All three reticle CD fingerprints can be (partially) corrected by higher order dose corrections. We calculated the reticle CD fingerprint after DoseMapper to be 0.4nm, 0.5nm and 0.7nm 3σ respectively. b) Litho track contribution For two litho clusters, the track contribution was evaluated after the first Litho step of LELE process. Figure 6 shows the raw measured CD data, which besides the track contribution clearly contains the reticle contribution, visible as a repeated CD fingerprint in every die. The distinct track contribution becomes noticeable when looking at the fitted CD interfield fingerprint Applying DoseMapper we expect the CDU to improve from 2.9nm 3σ to 1.1nm 3σ for left and from 3.8nm to 1.4nm 3σ for right lithocluster example. Litho Cluster #1 Litho Cluster #2 Raw Fitted Raw Fitted Figure 6: CD fingerprint for two lithoclusters. Raw data as measured by CDSEM and fitted interfield CD fingerprint are shown. Fit was obtained by applying polynomial fit to the raw CDdata. Proc. of SPIE Vol

8 c) Etch Contribution In a similar way we evaluated the contribution from the two etch processes, which use different recipe and etch hardware. Results after the first hardmask etch are illustrated in Figure 7. 0 Etch #1 Etch #2 Raw Fitted Raw Fitted Figure 7: CD fingerprint after etch of first hard mask in LELE process for two different etch configurations (recipe and hardware). Applying DoseMapper, we expect the CDU to improve from 4.0nm 3s to 1.8nm for left configuration and from 3.3nm to 2.0nm 3σ for right configuration. In order to meet our CDU target of 3.2nm 3σ for the two line populations and given the experimental context of reticles, tracks and etch modules as used in this study, DoseMapper is required. d) Final result for LELE 32nm ½ pitch Knowing the individual contributors to our LELE process, we now started studying the final 32nm ½ pitch pattern. Figure 8 shows the CD fingerprint of the two line populations and the two space populations. The two line populations are offset in mean CD due to different etch biases. Each line population clearly shows the radial etch fingerprint and the intradie fingerprint coming from the reticle. The space populations are impacted by I Line1: Mean=36.1 3σ=4.6nm Line2: Mean=38.8 3σ=5.5nm Space1 Mean=26.8 3σ=5.7nm Space2 Mean= σ=5.6nm Figure 8: Final experimental CD data for LELE process for 4 features: line 1, line 2, space1, space 2. Exposures on Twinscan XT:1900i, no dose and grid corrections applied. Proc. of SPIE Vol

9 From the experimentally observed line CD fingerprints, we calculated and then applied experimentally the DoseMapper corrections. As demonstrated in the previous chapter we expect up to 50% CDU by taking the CDU fingerprint context information of reticle, track and etch into account. This is validated in Figure 9 where the 4 populations are shown after the DoseMapper correction. The largest improvement is obtained for the lines by compensating the contributions from reticle, track and etch. The space populations are almost entirely determined by the overlay from scanner and registration errors of the reticles. Further improvement of the space CDU is expected by improvements in scanner overlay [12]. Line1: Mean=34.9 3σ=2.2nm Line 2: Mean=34.6 3σ=2.3nm Space 1: Mean= σ=3.7nm Space 2 Mean=28.5 3σ=3.8nm Figure 9: Final experimental CD data for LELE process for 4 features: line 1, line 2, space1, space 2 after applying DoseMapper. Exposures on Twinscan XT:1900i. 7. CDU CONTROL: SELFALIGNED SPACER Selfaligner spacer scheme has been proposed as an alternative to LELE double patterning because if its superior control of the lines that are patterned by a uniform and conformal deposition of a spacer layer along sidewalls of the sacrificial patterning lines. Effects of litho and etch process deviations from nominal, are predominantly found in CD variation of the sacrificial line which has been generated through one step litho and one step etch see Figure 1(b). According to our estimations shown in Table 1, the CD variations of the sacrificial layer are caused by variations in scanner dose and focus and by variations in track processing, etch and reticle CDU and registration. On the final doubled patterned layer, these errors are captured as space CD variation. As shown in previous section and considering the sources of error of our process, we expected to achieve a CDU of the second space in the range of 4.2nm. For the lines, which are generated by the sidewall deposited spacer layer, we anticipated a CDU of 1.6nm, where primary source of error is an estimated 5% across the wafer nonuniformity deposition and etchback. Figure 10 shows experimental results from our positive spacer process. The mean and 3σ variations of all four populations are remarkable close to estimated values (from Table 1) As expected, the spacerdefined lines 1 and 2 populations are perfectly correlated in both mean CD and 3σ. Their variation is slightly higher than our 5% prediction, which could indicate about 6.5% nonuniformity of spacer deposition across entire wafer. Variation in space width CD for second space is 4.1nm which is notable close to our estimation of 4.2nm bear in mind that this variation is from the sacrificial patterned layer. Proc. of SPIE Vol

10 L1 S1 L2 S2 Line1 Mean=32.7 3σ=2.1nm 0Line2 Line2 Mean=32.7 3σ=2.0nm Space1 Mean= σ=2.1nm Space2 Mean=32.8 3σ=4.1nm Figure10. Experimental results from a positive spacer process. Line1 and Line2 are the spacerdefined lines at the left and right edges of the sacrificial pattern. Space 1 is the space width between two spacerdefined lines and Space 2 is the space width defined by the sacrificial patterning and the spacer lines. Exposures on Twinscan XT:1700i. In previous section, we proposed DoseMapper technique to compensate LELE process to decrease CD variation to the levels required by a 32nm ½ pitch process, i.e., 3.2nm, or 10%. By applying the same technique for the spacer process, we predicted significant improvement in space width variation, which decreased from its measured value of 4.1nm to max. value of 2.8nm. In addition, applying DoseMapper corrections, the imbalance between mean CD of the two space width populations has been compensated for resulting in two populations with almost equal mean. These results are summarized in Table xxx Table 3: Four measured CD Populations in spacer scheme Measured and predicted variations in population mean and variance Line 1 Line2 Space 1 Space 2 Before dose corrections (measured) mean CD (nm) 3sigma (nm) After dose corrections (expected) mean CD (nm) 3sigma (nm) SPACEWIDTH CDU CONTROL IN SELFALIGNED SCHEME As described before, the most critical aspect in spacer selfaligned scheme is dimensional control during sacrificial patterning processing steps. An obvious question is how tight should we control the sacrificial patterning process in order to achieve the 10% control tolerances for space width? To answer this question, we performed a simple experiment where we programmed CD errors during sacrificial layer litho step. We exposed multiple wafers with modified dose to size, in 1nm increments. We measured line CD during litho and etch of the sacrificial layer. On the final processed wafers, we measured all four populations, 2 linecdu and 2 spacecdu results are shown in Figure 11. Changes in exposure dose do not have any effects on the line CDU which is defined by spacer layer deposition uniformity line1 and line2 CD s are constant through dose. In contrast, the space width defined by the sacrificial patterning step, space1, decreases linearly with dose, following exactly the trend of the sacrificial CD during litho and etch. In the same time, space2, CD increases in size at same rate as space1 decreases. Combined variation of the space Proc. of SPIE Vol

11 width difference, or Space1Space2, is about 4x larger than the variation in sacrificial line CD, which points out to the need to control the errors sources during patterning of the sacrificial layer to a level of 4x tighter than in single exposure Space or line [nm] Litho CD (nm) Etch CD (nm) Line1 (nm) Line2 (nm) Space1 (nm) Space2 (nm) Dose (mj) 27mJ 33mJ ifliffi Figure 11. Experimental validation of the control level required to achieve 10% CDU on space width in the selfaligned spacer process. Exposures on Twinscan XT:1900i. 9. CONCLUSIONS AT THIS STAGE Due to the capability to shrink the pitch below 0.25k1, DPL is a natural resolution extension for ArF immersion lithography. Compared to single exposure lithography, DPL resolution benefits are coming with trade offs from added process complexity, significantly tighter CDU and overlay control and increased metrology. In this paper we reported results of hyperna litho system integrated with etch and other processing tools to explore CDU and overlay performance at 32nm ½ pitch resolution in LELE and selfaligned spacer DPL schemes. A key challenge is the control of the multiple CDU populations created during independent patterning steps. For LELE scheme, we identified four independent CDU population, two for lines and two for spaces. Line CDU populations generated from the two independent Litho and Etch steps, have different averages with different statistical and spatial distributions. Mean difference between two space CDU populations are correlated through overlay error from layer1tolayer2, while their spatial and statistical distribution could be different. In selfaligned spacer scheme, we recognized also four populations, three of them being clearly separated in their averages and distributions. In a positive spacer process, the two line CDU populations are perfectly correlated with almost equal means and 3σ distributions. The two associated space CDU populations have different means and distributions. Dimensional imbalance of the two space CDU populations behaves like a local overlay error. The biggest DPL challenge is to control of whole process as an integrated system. Sources of CDU error from all components of the patterning system become visible: reticle CDU & registration, wafer spatial distributions caused by film deposition (stress), etch fingerprint, PEB, and metrology. This interconnectedness coupled with subhalf nm control tolerances motivates application of active compensation control of both CDU and overlay. By applying the active compensation technique, we reported CDU control levels of 2nm and overlay control of ~3nm, which support future adoption of double patterning as the resolution enhanecment solution at 32nm node. Proc. of SPIE Vol

12 Acknowledgement We would like to acknowledge entire DPL teams at ASML and IMEC for their support and outstanding work results. References [1] Beyond k1=0.25 lithography : 70nm L/S patterning using KrF scanners, A. Ebihara et al., Proceedings of SPIE 5256, 2003 [2] Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool, WooYung Jung, et al, Proceedings of SPIE , 2006 [3] Positive and negative tone double patterning lithography for 50nm flash memory, ChangMoon Lim et al, Proceedings of SPIE, Vol ,2006 [4] Issues and challenges of double patterning lithography in DRAM, SM Kim et al, Proceedings of SPIE, Vol , 2007 [5] Double patterning scheme for sub0.25k1 single damascene structures with NA=0.75, λ=193, M. Maenhoudt et al, Proceedings of SPIE Vol. 5754, 2005 [6] Manufacturing challenges in double patterning lithography, W. Arnold et al, ISSM2006 MC233, October 2006 [7] Pitch doubling through dualpatterning lithography challenges in integration and litho budgets; Pitch doubling through dualpatterning lithography challenges in integration and litho budgets, M. Dusa et al, Proceedings of SPIE Vol. 6520, 2007 [8] J. Finders et al, Double Patterning Lithography: the Bridge Between low k 1 ArF and EUV, MLW, March 2008 [9] Sub32nm half pitch imaging with high NA immersion exposure systems using Double Patterning techniques, Bert Vleeming et al, 4th International Symposium on Immersion Lithography, Keystone 2007 [10] Mask characterization for doublepatterning lithography, K. Bubke et al, SPIE Photomask Technology Conference 2007, Proceedings of SPIE Vol [11] Robert de Kruijf et al, Waferbased Mask Characterization for Double Patterning Lithography, EMLC, 2008 [12] J. de Klerk at al, Latest developments on immersion exposure systems, SPIE Conference , 2008 Proc. of SPIE Vol