Towards 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography

Transcription

1 Towards 3nm overlay and critical dimension uniformity: an integrated error budget for double patterning lithography Bill Arnold SPIE Advanced Lithography Optical SPIE 69-3 / Slide Outline Double patterning motivation CDU and overlay requirements for single exposure Entangled CDU and overlay requirements for double patterning Approaches to maximizing combined window Conclusions SPIE 69-3 / Slide

2 Why Double Patterning? NAND Flash DRAM Logic / SRAM Resolution, Shrin nk (nm) AT: XT:.7 ~.3.9 ~.35 XT:7i ASML Product XT:9i Introduction NEXT EUV 6 Transistor SRAM Cell.36 ~. Immersion Double Patterning Note: Process development.5 ~ years in advance / updated /7 Year of Production Start* SPIE 69-3 / Slide 3 EUV Outline Double patterning motivation CDU and overlay requirements for single exposure Entangled CDU and overlay requirements for double patterning Approaches to maximizing combined window Conclusions SPIE 69-3 / Slide

3 Single Exposure Isolated and Dense Lines (D) Target CD dense Real CD is smaller than target CD Error caused by litho step Target CD iso Lines and spaces printed together L S L S Nominally L = L = L iso S =S Dense One population of lines One population of spaces Iso SPIE 69-3 / Slide 5 ITRS Roadmap for Single Exposure CDU & Overlay 6 Overlay (nm) 8 6 Overlay is % of half pitch CDU is 7 % of half pitch 5 3 CD Uniformity (nm m) Resolution - half pitch (nm) SPIE 69-3 / Slide 6 Ref: ITRS 7 3

4 5nm isolated lines /.35NA.. nm nm Full wafer.8 nm Intrafield.9 nm Horizontal Factory qualification: Resist and reticle correctables removed SPIE 69-3 / Slide 7 Vertical 5nm Isolated Lines-Full Wafer CDU (see M. van de Kerkhof, 69-67) Prediction.6nm Measured.7nm (avg) 5 nm Isolated line CDU Performance NA=., σ in =.5, σ out =.7 Wafer 8% Reticle NCE 8% 5 Intra field Full wafer Scanner % Metology % nm 3 Process NCE % System SPIE 69-3 / Slide 8 Average Maximum CDU 5 nm Iso Intrafield.. CDU 5 nm Iso Full wafer.7.

5 . nm 5nm dense lines /.35NA. nm Full wafer. nm. nm Intrafield Horizontal Vertical SPIE 69-3 / Slide 9 5nm dense lines- full wafer CDU Prediction.nm Measured.nm (avg) 5 nm Dense Lines Wafer % CDU Performance NA=.35, σ in =.79, σ out =.9 Reticle NCE % 5 Intra field Full wafer nm 3 Scanner % Metrology 5% Process NCE % System SPIE 69-3 / Slide Average Maximum CDU 5 nm Dense Intrafield.5. CDU 5 nm Dense Full wafer..9 5

6 XT:9i: 38nm dense line CDU.35 NA, dipole illumination full wafer CDU =.6 nm intrafield CDU =. nm SPIE 69-3 / Slide From Scanner-centric dense/iso CDU to a real layout case: Predicted CDU performance of 5nm NAND WL Total CDU is Root Square Sum (RSS) of all contributors CDU total = CDU focus / dose + CDU i= MSD,Flare,... i CDU [nm] F=nm F=5nm F=nm. System CDU Reticle Total CDU Focus/Dose/MSD/Flare from Bossung convolved with system budgets NA/sigma/polarization/reticle contribution based on NAND real feature sensitivity Metrology and Processing contributions are neglected SPIE 69-3 / Slide 6

7 Predicted CDU contributions of 5nm NAND WL from scanner primary parameters + reticle Drawn layout (non-optimized for litho) Scalar simulation of a scalar mask Constraints/requirements: nm (3σ) reticle non-uniformity; it Scanner focus control budget of 3nm (8σ) Contribu ution to BF [nm 3σ] WL6 WL3 WL WL SG L.. ½ P.. SG and SG n* ½ P. NA σ(center) MSDxy MSDz Flare DOP Dose Focus Reticle NCE SPIE 69-3 / Slide 3 Entangled CD & Overlay control for Design Rule decision What is the minimum Contact to Gate edge-to-edge separation supported by a technology node? X MIN_wafer XMIN _ wafer > a Where the a parameter is set by device reliability requirements to avoid shorts failures NAND Logic X = X Tol MIN _ wafer NOM _ wafer X = X + Gate Contact NOM _ wafer design shrink increase CD control OL control ( 3 ) ( 3 ) ( ) CH CD Gate CD OL _ Gate to CH Tol = σ + σ + σ 3 3 ( 3 ) ( 3 ) ( ) X a Gate CH σ σ σ design > CDshrink + 3 CDincrease + 3 CHCD + GateCD + OL _ Gate to CH SPIE 69-3 / Slide 7

8 3 nm 6T SRAM: cell area shrink example (see S. Verhaegen, 695-6) ACTIVE GATE T pass -T pass L T pass -T pu T pu -T pu W pass extension T pass T pu T pd Memory architecture:.33 μm N ROW = 5 N COL = 6 N RedCol = L pd T pd W pd T pu W pu L pu gap T pass Parametric yield limit Layout parameter Yields when there is no short contact to gate Spacer Strain CH CD gate CD + overlay Minimum contacted pitch 5% smaller cell requires % better overlay 6% better CDU Pass transistor SPIE 69-3 / Slide 5 Pull-down transistor Bitline contact Internal node GND contact Process overlay errors can be partly compensated with higher order grid corrections Raw Overlay (before GridMapper) Gate to Active XT:7i GridMapper Reticle and field contributions account ~5% of the residual overlay after grid corrections M + 3S =. Grid corrected (using GridMapper) Grid corrected + avg field removed M + 3S =5. SPIE 69-3 / Slide 6 M + 3S =. 8

9 Current Immersion tools can show significant overlay < 5nm on process wafers DP layer aligned to STI; NA.; Best wafer of Courtesy: Hynix (see Won-Kwang Ma et al, 69-3) SPIE 69-3 / Slide 7 Single machine Overlay: towards < and <3nm Major new designs to improve Overlay (see Jos deklerk, 69-6) Overlay budget Positioning 6 Now 3 Calibration Optics Thermal Alignment Mechanical SPIE 69-3 / Slide 8 9

10 Outline Double patterning motivation CDU and overlay requirements for single exposure Entangled CDU and overlay requirements for double patterning Approaches to maximizing combined window Conclusions SPIE 69-3 / Slide 9 Double patterning CDU and Overlay Double patterning options, Spacer and LELE, can be either a positive or a negative process flow Critical for Lithography Target CD and CDU control for multiple populations Overlay is present in CDU in LELE CDU is present as overlay-like errors ( pitchwalking ) in spacer SPIE 69-3 / Slide

11 Entangled CD and Overlay Single Exposure A pattern is created at once from correlated edges CDU based on pattern control Design rules based on placement control of edges generated in separate process steps (layers) DPL Layer-to-layer edge placement are uncorrelated A pattern is created from two separated and uncorrelated edges CDU based on edge control Design rules based on placement control of edges generated in On same DPL-created layer and from separate process steps (layers) Layer-to-layer edge placement are uncorrelated Twice as many edge placement errors required for DR Paradigm shift for device designers: SPIE To 69-3 be adopted, / Slide DPL shall 6 produce February devices 8 with same electrical characteristics as SE (D. Kim, Hynix) Single exposure CDU + OL budget at 3nm for reference L L S S One CDU population for all lines etch,.6, % SE CDU: 3.nm metrology,., 5% nce,., 5% scanner,.8, % One Space-CDU population, correlated to Line CDU Entangled CDU-OL tolerance for DR decision CDU gate 6% CDU CH % mask,.6, % SE OL budget: 8nm litho process,.6, % metrology, apc,, mask,.8,, 6% % 7% nce,, 6% *OL 6% process OL, 5, 3% SMO, 5, 9% SPIE 69-3 / Slide

12 LELE: CDU for Isolated and Dense Lines Target CDlitho (dense) Real CDlitho is smaller than target CDlitho Errors caused by st litho Target CDlitho (iso) Dense Iso st etch introduces additional CD error Overlay error nd Litho: target CD different from CDlitho Overlay error causes spaces (in a positive process) to be different L S L S Final CD < % Target CD Final CD includes populations, two for lines, two for spaces SPIE 69-3 / Slide 3 LELE CDU and OL budget at 3nm L L S S 3.nm Predicted LELE CDU for tw o line pop. Line CDU populations =3.nm Two uncorrelated L, L line-cdu populations pp separated by differences in population mean, Line-cdu,.9, 3% Line-cdu,.9, 3% Space-CDU population affected by Overlay LELE Space CDU:.5nm Mean L - Mean L.6, % LELE Line () CDU:.9nm mask,.3, % process OL, 3., 8% SMO, 3., 8% litho process,.9, % mask,.9, % etch process, litho process,., %., % scanner CD,., % metrology,.3, 3% nce,.3, 3% scanner CD,., % nce,., 5% metrology,., 5% etch,.9, % Space CDU: 5% Line CDU: % SPIE 69-3 / Slide

13 LELE CDU-lines: measured to predicted CDU Predicted budget: Target CDU is set to 3.nm (%) for combined Line and Line CDU populations plus.6nm added difference between the means of the two populations Measured budget current results: 3nm LELE Line process on 7 at IMEC, after DoseMapper compensation close match to predicted budget breakdown Predicted LELE CDU for two line pop. Measured LELE CDU for two line pop. Line-cdu,.9, 3% Line-cdu,.9, 3% Line-cdu,., 5% Line-cdu,.3, 9% Mean L - Mean L.6, % 3.8nm predicted CDU Mean L - Mean L.3, 6% 3.nm measured CDU SPIE 69-3 / Slide 5 LELE CDU-space: measured to predicted CDU Predicted budget: Target CDU-space is set to.5nm (5%) and includes space CDU combined with overlay error Measured budget: 3nm LELE process on 7 at IMEC; after DoseMapper Measured overlay of ~ 3.3nm including SMO and process Scanner (imaging) and patterning Predicted (nm) Measured (nm).7. Overlay (SMO, process). 3.3 Reticle.3.5 Others.? Total.8nm 5.6 measured 3.8nm after DoseMapper corrections Overlay entangled in CDU SPIE 69-3 / Slide 6 3

14 Spacer Double Patterning: Isolated and Dense Lines (D) Target CDlitho (dense) Real CD is smaller than target CD Error caused by litho and etch trim patterning steps Dense Iso Target CDlitho (iso) Spacer deposition, CMP, and etch introduces further CD errors S S CD error in the sacrificial layer causes overlay-like error in L L final pattern ( pitch walking ) SPIE 69-3 / Slide 7 Self-Aligned Spacer CDU + OL budget at 3nm L L S S One CDU population for all lines (spacer generated) Two Space-CDU populations caused by sacrificial patterning errors reflected as OL errors (pitch-walking) Spacer Space-CDU: 3.nm Spacer Line-CDU:.nm non-litho process,, 7% S to S,.8, 6% Singleline,.9, % litho process,, % mask,, % scanner CD,, % nce,., 5% metrology,.3, % Litho has no contribution to spacer-line CDU metrology,.5, % Spacer patterning Space-CDU:.9nm nce,., scanner 5% CD,., % SPIE 69-3 / Slide 8 litho process, etch,.9,.9, % % mask,.9, % Litho has highest potential for compensation sacrificial (spacer-line CDU)

15 y y Outline Double patterning motivation CDU and overlay requirements for single exposure Entangled CDU and overlay requirements for double patterning Approaches to maximizing combined window Conclusions SPIE 69-3 / Slide 9 CD Performance: CDU spatial map on DPL patterns 8 6 Layer CD Maps (TPS fit of Data) Layer 3 - CD performance of DPL features Layer Off- target t CDU (nm,3σ) ) (nm) Matching of CDU Signatures 6 8 x x Correlation Max Deviation - Coefficient i (nm) Promising off-target performance with negligible mean-to-target difference Bubke, et. al.,, SPIE Photomask Similar CDU signature on both masks 7 SPIE 69-3 / Slide 3 5

16 Correlation Reticle vs Wafer Overlay Mask- to mask- Overlay (calculated from y mask and registration) y Corresponding layer- to layer- wafer Overlay 8 x x 7 6 x 8 x x 7 x Xcor cor. Y cor. Wafer dx [nm] Wafer dy [nm] slope = Reticle dx [nm] slope =..5.5 R =.79 Chisq = Reticle dy [nm] Overlay signature from Mask to Mask clearly transfers onto R.deKruif, et. al., EMLC Photomask 8 Layer- to Layer- wafer overlay signature SPIE 69-3 / Slide R =.89 Chisq =. Exposure-related CD control for wafer CDU Single exposure Minimize intra (incl. reticle)/interfield CDU LELE: bring together two CD populations p minimize difference between populations mean, intra/interfield Reticle and intrafield more critical Match CDU fingerprint maps of two populations, intra/interfield Distinguish patterns (st or nd) Spacer: extreme control/compensation of sacrificial patterning st pattern CDU (+Mean to target), litho and etch performance Minimize CD difference between st and nd patterning Exposure tolerance and control w/ enough dose margin at scanner only relieves MTT spec and allow tight wafer CDU!! (HanKu-Cho, SPIE Photomask, 9//7) SPIE 69-3 / Slide 3 6

17 Intrafield DoseMapper for LELE lines CDU control Goal: bring LELE interfield line CDU to calculated tolerances for variance and mean difference (for 3nm) Raw CDU map CDU variance/population: <nm; difference between means: <.8nm CD-/CD- after Line Line Raw CD-/CD- DoseMapper CDU map after DoseM Mapper See Jo Finders, et al, 69-7 Line (3s) Line (3s) Before DoseMapper.6nm 5.5nm After DoseMapper.nm.3nm SPIE 69-3 / Slide 33 3nm Spacer Final result (experimental data: CD-SEM) Line Mean=3.7 3σ=.nm Line Mean=3.7 3σ=.nm Space Mean= 3. 3σ=.nm Space Mean=3.8 3σ=.nm Expected performance after applying DoseMapper (calculated) Line Mean=3.7 3σ=.nm Line Mean=3.7 3σ=.nm Space Mean= 3.3 3σ=.3nm Space Mean= 3.3 3σ=.8nm SPIE 69-3 / Slide 3 7

18 Spacer needs tighter CD control Sacrificial pattern width variation caused by Litho + HD etch Experimentally measured sensitivity to changes in exposure dose for spacer S S S Sensitivity process to Dose in nm/mj S = S ε S = + ε ' ' S ' S ' S nm/mj - hardmask S S S-S - ε ε ε ε ε: positional change of one edge S = S ε S ' = S + ε ' Δ S = ε To control pitch-walking, CD control of sacrificial pattern SPIE 69-3 / Slide 35 should 6 February be ~x 8 tighter than SE -6 Pattern Normalized Sensitivity nm/mj Hardmask a S.8a S -a S-S -3.7a All DPL: measured CDU before/after corrections 3nm LELE and Spacer baseline processes on 7 at IMEC Encouraging results towards achieving 3nm CDU and OL control for DPL Litho compensation of inter and and intrafield processing variation is unavoidable to reach 3nm control tolerances Expected CDU (nm) measured LELE LELE +Litho compensations experimental measured Spacer Spacer+ Litho compensation modeled CDU Line.9.6..nm.nm CDU Line nm.nm Line-Line mean difference Overlay 3.5 to CDU space nm 3.3nm CDU space nm.9nm Space-Space mean difference <.8nm.nm SPIE 69-3 / Slide 36 Overlay entangled in CDU CDU entangled in local overlay 8

19 LELE: Overlay aware stitching split stitch Red: Necking without Overlay aware stitching Blue: contour with Overlay aware stitching Without overlay error at nominal condition 5 nm x overlay error at nominal condition 5 nm x and 5 nm y overlay error at nominal condition SPIE 69-3 / Slide 37 LELE: Overlay aware stitching split stitch Red: Necking without Overlay aware stitching Blue: contour with Overlay aware stitching Reduced necking with Overlay aware stitch Without overlay error at nominal condition Delta focus=5 nm Delta dose = 5% SPIE 69-3 / Slide 38 9

20 Outline Double patterning motivation CDU and overlay requirements for single exposure Entangled CDU and overlay requirements for double patterning Approaches to maximizing combined window Conclusions SPIE 69-3 / Slide 39 nm lines and spaces with 93nm LELE see Jo Finders et al, 69-7 nm dense lines!!! 3 nm dense lines SPIE 69-3 / Slide

21 Conclusions 93nm Extension to 3X and X nm with double patterning Extension of 93nm lithography to 3X and X nodes Realizing there is no new NA on the horizon, the focus shifts from a straight shrink to learning how to reduce the effective k through double patterning Spacer and LELE are the most likely approaches LELE is a lower cost, higher productivity opportunity Spacer can be used with any existing lithography tool but is more complex to layout and process Litho tool Both spacer and LELE require much tighter CDU than required from SE lithography; LELE must also achieve overlay on the order 3nm < nm CD and <.5nm OL controls become unrealistic and expensive. Tighter CDU and overlay budgets should be achieved through active compensation of wafer and field spatial distributions. SPIE 69-3 / Slide Acknowledgements Mircea Dusa, Jo Finders XT 9i Team - Andre Engelen, Eelco van Setten, Mark van de Kerkhof, Hans Bakker, Jos de Klerk TDC - Donis Flagello, ll Steve Hansen, Bob Socha, Alek Chen, Marla Downing Brion Stephen Hsu ASML DPT Team - Birgitt Hepp, Bert Vleeming, David Deckers, Dorothee Oorschot, Bart Rijpers, Henry Meegens, Paul de Haas, Christian Leewis, Martyn Coogans, Eddy van der Heijden, Henry Megens, John Quaedackers, Jeroen Meessen IMEC DPT Team - Mireille ill Maenhoudt, Shaunee Cheng, Patrick Jaenen, Tom Vandeweyer, Diziana Vangoidsenhoven Peter Jenkins SPIE 69-3 / Slide