Lithography Challenges Moore s Law Rising Costs and Challenges of Advanced Patterning
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1 Lithography Challenges Moore s Law Rising Costs and Challenges of Advanced Patterning SEMI Texas Spring Forum May 21, 2013 Austin, Texas Author / Company / Division / Rev. / Date
2 A smartphone today has more computing power than all of NASA did when it put a man on the moon in 1969 Paul Otellini CES 2012
3 Moore s Law Number of transistors doubles every 2 years
4 Patterning Advances Wavelength Extensions Process Innovations Novel Materials
5 Half Pitch resolution (nm) Lithography Roadmap Logic NAND DRAM i DPT EUV
6
7 Wavelength Extensions John William Strutt aka Lord Rayleigh Process factor Resolution = k 1 λ NA Wavelength 248nm 193nm 157nm 13.5nm (EUV) Numerical Aperture Lens property Immersion
8 Why EUV (13.5nm)? 40nm HP 193i EUV
9 Old vs. New 3x footprint Vacuum-based Complex components
10 EUV Optics 40 layers of Mo / Si ~70% transmission
11 Key EUV Challenges EUV Source Resist Mask
12 Old vs. New Source 193nm Source Excimer laser EUV Source
13 Creating 13.5nm Radiation 30um Tin droplets 80kW CO 2 Laser Debris Generator
14 EUV Utilities 193i EUV Electrical Power (kw) Water (l/min)
15 Patterning Advances Wavelength Extensions Process Innovations Novel Materials
16 Double Patterning 40nm to 20nm
17 Double Patterning Deposition
18 Double Patterning Etchback
19 Double Patterning Etchback
20 Double Patterning 20nm Features
21 Cost per Layer (a.u.) Cost per Layer i 193i + DPT 193i + QPTEUV wph EUV wph EUV - 10 wph
22 Patterning Advances Wavelength Extensions Process Innovations Novel Materials
23 Directed Self-Assembly (DSA) DSA is realized by separation of the different polymer blocks DSAL is a lithography to make patterns using lithographically directed selfassembly (DSA) of block copolymer Disordered state Two different property polymers are connected with covalent bond Polymer A Polymer B Coating and &Bake Ordered State A with A and B with B approach each other A and B are separated
24 Pattern Scaling Theory Lamellar A B A B A Cylinder A B B A B B A B L 0 L 0 a Statistical monomer segment length N Total degree of polymerization L 0 an 2/3 χ 1/6 χ AB Interaction strength (Flory-Huggins parameter) A. N. Semenov, Sov. Phys. JETP 61, 733 (1985)
25 Complementary Lithography Customer Applications and Design Rules Self-Aligned Hole or Pitch Shrink Line/ Space Pitch Shrink Novel capability Resolution CDU/ LWR Healing Line Pattern Collapse Prevention Process Window Improvement (Dose, Focus)
26 Directed Self-Assembly Opportunities Pattern shrink 90nm hole 30nm hole PS-PDMS Small size pattern DSA SEM pictures by Tokyo Electron Ltd. Applicability Y. S. Jung, J.B. Chang, E. Verploegen, K. K. Berggren, C. A. Ross, Nano Lett, 10, 1000 (2010) M. P. Stoykovich, H. Kang, K. C. Daoulas, G. Liu, C. C. Liu, J. J. de Pablo, M. Muller, P. F. Nealey, ACS Nano, 1 (3), 168 (2007)
27 Line/ Space DSA (SPIE 2012) PS-b-PMMA Grapho-Epitaxy PS-PMMA Chemo-Epitaxy (Lift off) 14 nm HP DSA pattern RIE Etch DSA Pre-pattern Neutral Layer ~35 nm LN/ 112 nm pitch Coat Develop Liftoff After 4x DSA anneal 14 nm line/spaces Etch Guide Chemo-Epitaxy High Chi L/S Demonstration DSA Pre-pattern ~35 nm LN/ 100 nm pitch Trim etch ~15 nm Wet resist strip After 4x DSA process 12.5 nm line/spaces 9 nm HP B. Rathsack, et. Al., Pattern Scaling with Directed Self Assembly Through Lithography and Etch Process Integration, SPIE (2012)
28 Graphoepitaxy Hole Application Ellipse Hole Ellipse Hole Trench Hole Split (two 16nm holes) Slit hole 16nm 1:1 holes B. Rathsack, et. Al., Advances in DSA integration and manufacturability at 300 mm, SPIE (2013)
29 Device Integration Through collaborative process development, DSA patterns have been etch transferred into device relevant substrate (silicon substrate) Schmid, et. al., Fabrication of 28nm pitch Si fins with DSA lithography, SPIE , (2013)
30 DSA Patterning Etched SOI substrates with DSA process (PS-PMMA on neutralization layer) LER ~1.5 nm with post etch annealing 29 nm Pitch Hsin-Yu Tsai, et al., J. Vac. Sci. Technol. B 30, 06F205 (2012)
31 DSA Line with Cut for FIN FET Devices after etch transfer into a silicon-on-insulator (SOI) substrate 29 nm Pitch HsinYu Tsai, et al., IBM 5 April 2013, SPIE Newsroom
32 Summary Wavelength Extensions Process Innovations Novel Materials EUV Double Pattern Multi Pattern Direct Self Assembly Cost will drive which option is adopted by industry
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