EUV Lithography Status and Key Challenges for HVM Implementation
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1 EUV Lithography Status and Key Challenges for HVM Implementation Sam Intel Corporation
2 Moore s Law at Intel 10 Feature Size (um) 100 Cell Area (sq um) x every 2 years The trend is expected to continue Goal Find most cost-effective lithography solution to allow trend to continue 2
3 Choosing between Lithography Options If current lithography is capable of delivering a manufacturable process, use it If not: If new lithography technology is ready, manufacturable and cost-effective, use it (increase NA, reduce λ) If not: need to make alternative decisions to enable scaling without litho improvements (operate more effectively at lower k 1 ) Managing litho transitions is key! Requires significant planning 3
4 1.2 ArF Pitch Division vs. EUV NA ArF DP 1.35NA ArF EUV k NA ArF 0.3 k = /2 Pitch (nm) 45nm node 80nm HP 07 HVM Dry 32nm node 56nm HP 09 HVM Immersion 22nm node ~40nm HP 11 HVM Immersion 15nm node 26-30nm HP 13 HVM ArF PD/ EUV 11nm node 18-22nm HP 15 HVM ArF PD/ EUV 4
5 Patterning Choices for 15nm and 11nm ArF Pitch Division EUV Advantages: Known technology Well-established infrastructure Mature photoresist and tooling Disadvantages: Complex process flow Very expensive Complicated DRs Advantages: Single exposure Simpler DRs Disadvantages: Unknown technology Infrastructure needs to be developed Immature photoresist, tooling 5
6 EUV HVM Key Requirements Stable hardware Scanner platform Optics Overlay/stage System (vacuum) Source Reliability and uptime Power Photoresist that meets requirements Resolution, sensitivity, LWR Etch interactions Reticles Defectivity Infrastructure (cleans, inspections, handling) Success of EUV in HVM will depend on progress on all these fronts 6
7 Exposure Tooling 7
8 External EUV Exposure Tooling Nikon EUV1 alpha tool 0.25NA full field scanner Currently installed at Nikon and SELETE ASML Alpha Demo Tool (ADT) 0.25NA full field scanner Currently installed at IMEC and SEMATECH Intel Internal MET small-field exposure tool Target application is resist development 8
9 EUV HVM Exposure Tooling Development ASML ADT printed wafer Nikon EUV1 printed wafer EUV Source Suppliers are competing towards HVM tool development Cymer beta source Philips beta source 9
10 Photoresists 10
11 0.3NA capability 600 x 600 µm field Low flare (3-6%) Intel MET Source: (XTREME DPF Source) 0.5mm x 2mm (FWHM) 35W EUV in 2π New EUV collector installed New outer shell extended σ outer from 0.55 to 0.65, 22nm HP resolution with quadrupole illumination First step in preparation for 0.5 NA MET projection optics (2010) that will enable ~10nm HP resolution 11
12 Intel MET Status J/cm MET Cumulative Dose (J/cm2) 200 2H '04 (Install/Qual) (through WW37) 1 J/cm2 per day J/cm2 per day 1000 Day J/cm2 per day 3.8 J/cm2 per day Uptime average: 67% in 07, 85% in 08, 65% through WW38 in 09 Continuous improvement in output efficiency 14J/cm 2 /day currently On track to deliver more dose in 2009 than in 2008 Improved resolution and expanded process window Long term upgrade path defined down to ~10nm HP > 250 Resists Screened in 08. Goal > 500 in 09 12
13 Intel EUV Resist Team New Materials Benchmarked 2H 07 - Present = = 424 (YTD) Albany emet Intel MET EUV Resists Benchmarked / Month JUL AUG SEP OCT NOV DEC JAN FEB MAR APR MAY JUN JUL AUG SEP OCT NOV DEC JAN FEB MAR APR MAY JUN JUL AUG SEP (F) OCT (F) SCHED INTEL-MET UPGRADE UNSCHED INTEL-MET DOWNTIME
14 Quadrupole Aerial Image Quality on Intel MET NA = 0.30, On-Axis Dipole vs Quadrupole Comparison Quadrupole 0.68/0.36 (max outer σ /inner σ) On-axis dipole On-axis dipole 0.68/0.36 SEM SEVR-115 Acrylic EUV resist; FT = 40 nm Test match between simulation and experiment; Nice way to experimentally probe contrast required for EUV platform Demonstration of meaningful CAR solution for EUVL at 22nm HP Attribute limitations to exposure tool, mask, or material 14
15 ILS (1/um), Contrast (%) MET Quad Source Enables 22nm HP ILS Contrast HP (nm) From mid-2009 Quad 0.68/ nm HP 28nm HP 26nm HP 24nm HP 22nm HP 20nm HP 15
16 New MET Dipole Source Enables 18nm HP Intel MET on-axis dipole capable of imaging 18nm HP Contrast begins to fall off at 17nm HP Currently mask and/or resist limited 20 nm HP 19 nm HP On-axis dipole 15 nm HP 16 nm HP 17 nm HP 18 nm HP 0.68/0.36 σ 16
17 Berkeley ALS-MET (Rotated Dipole) :: Champion RLS Summary for hp Resist D Esize = mj Min LWR = 4.8 nm UR ~ 28 nm HP SMT01 Esize = mj Min LWR = 6.2 nm UR ~ 24 nm HP Resist E Esize = 9.95 mj Min LWR = 6.3 nm UR~ 24 nm HP Resist F Esize = 6.85 mj Min LWR = 5.3 nm UR~ 26 nm HP 22 HP 30 HP Champion CAR platforms Nominally Meeting 22nm HP R/S Targets but Failing for LWR/PC 17
18 Pattern Collapse Margin Improvement Multiple approaches may be needed to address problem Modify Aspect Ratio Surface (Energy) Optimization: Hydrophobicity, Multilayer stacks Increased resist modulus, Negative Tone & Semi-organic Resists Decreased Surface Tension: Rinse agents, Organic Developers, Develop/Rinse/Spin Dry Process Optimization Pattern Collapse Mitigation is a key area of focus 18
19 LWR Reduction Techniques No Treatment Technique Etch/Trim Vapor Smoothing Hardbake Ozonation Rinse Etch/Trim Reduction (nm) Reduction (%) Vapor Hardbake Ozonation Physical (Etch/Trim, Hardbake) Photoresist chemistry independent Chemical (Vapor, Ozonation, Rinse Agent) Photoresist chemistry dependent Rinse Chandhok et al, J. Vac. Sci. Technol. B, (Nov 2008) Multiple techniques may be needed to address LF & HF roughness Largest LWR Improvement Seen with Rinse Agent 19
20 Current Target Improvement Required Resist and Tooling Gaps Source Power Current Target Improvement Required Photoresists (32/22nm HP) Power (W) ~ X Photospeed (mj/cm 2 ) 10/20 10 None/2X Current Target Improvement Required 3σ LWR (nm) 3.8/ /1.28 2X/5X Scanner Runrate Runrate (wph) X Summary: Good progress made to date Need continued work to bridge (or significantly reduce) gaps for both performance and COO 20
21 Reticles 21
22 HVM Reticle Infrastructure Requirements Reticle Requirements Mask Shop Mask Manufacturing Mask Cleaning Blank inspection Patterned inspection AIMS inspection Fab In-situ Inspection Patterned Inspection Need inspection capability in both the mask shop and the fab to ensure manufacturable operations 22
23 Intel s Mask Tool Pilot Line 1G & 2G Blank Inspection Flatness EUV Refl Film Dep 3G Actinic Blank Inspection Sorter Patterned mask inspection Mask Clean EUV AIMS 23
24 Mask Blank Yield Gap for Pilot Line and HVM Introduction Determine Defect Density Target defects/cm 18 nm is the historical defect free target However, recent data suggests only 10-20% of defects print The ultimate HVM defect density target might be nm Today: 1 defect/cm Gap to Pilot: > 25x Gap to HVM: >100x Mask yield with zero defects 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% Pilot Line Yield defects/cm 2 Today 10-20% of defects print 0.02 HVM Pilot HVM Yield 1% 10% 100% Percentage of defects that are printable Data from Sematech 24
25 Mask Blank Defect Trends 1.E+04 1.E+03 80nm defect size 50nm defect size RM-for blank need by 2012 RM-for blank need by G Actinic Inspection Defect counts 1.E+02 1.E+01 80nm 45nm 50nm 45nm 35nm 35nm 30nm 3G tool 25nm Actual Needed 25nm 20nm 1.E+00 1G inspection tool 2G tool Jan-06 Jan-07 Jan-08 Jan-09 Jan-10 Jan-11 Jan-12 Jan-13 Jan-14 Metrology Tool Gap Limits HVM Insertion! 25
26 New Blank Defect Inspection Capability M1350 M7360 Blank inspection tool Laser source λ > 98% capture rate Def. on quartz substrate Def. on ML blank G1 (M1350) 488 nm 2004-Q nm 80 nm Q nm 50 nm G2 (M7360) 266 nm Q nm 40 nm 2 nd -gen mask blank inspection tool successfully installed in June Inspectability will be further extended with spatial filter upgrade in Q4 Moving toward ultimate 25nm inspection requirement for
27 AIMS and Patterned Defect Inspections AIMS: Industry requirement: 22nm hp+ defect repair verification with scanner conditions Strategy for 2013 HVM: HVM tool requires commercial partner, but market is small Consortium model attempts underway July summit Patterned: Industry Requirement: Patterned defect inspection at 22nm HP KLA6XX will achieve 32nm and some 22nm HP performance Strategy for 2013 HVM: Market is sizeable and tool cost significant Suppliers unwilling to bear $250M NRE cost alone July summit SEMATECH contribution will be to broker funding model 27
28 July Semicon Meeting on EUV Reticles Meeting was held with good participation from suppliers, mask shops, IDM s, and consortia. Technical and business working groups have been busy Available data has been shared and leveraged as appropriate Some additional data collection underway to validate specs Stakeholders should provide clear feedback on funding models A benefit for assuming risk is equivalent to a penalty for standing by (e.g. ROFRs, royalties, etc.) Letters of Intent will be requested this year, commitments early 2010 Now is the time to get on board! 28
29 HVM Pilot Development EUV Mask Inspection Tools Summary Defect Size [nm] Substrate Blank Substrate & Blank Lasertec M1350 (1st Generation) M1350 & SEMATECH Lasertec M7360 (2nd Generation) 2.5 Generation Substrate Inspection Tool (2.5G) (Supplier TBD) (can also be used for destructive blank inspection) Table from Sematech SEMATECH Berkeley AIT Selete MIRAI 3 rd Generation Blank Inspection Bridge Tool (3G ) (Supplier TBD) Commercial 3G Inspection Tool (Supplier TBD) ABC = Existing Tools AIMS & Patterned SEMATECH Berkeley AIT 88 nm mask CD resolution Key for defect printability understanding SEMATECH Berkeley AIT2 60 nm mask CD resolution AIMS Bridge tool Commercial AIMS Tool (Supplier TBD) KLA 5XX KLA 6XX Actinic Patterned Inspection (Supplier TBD) = Actinic Inspection Tools 29
30 Particle-free Reticle Handling Progress 0.20 Average Adders spod Carrier Shipping Vacuum Storage Total He, et al. Proc. SPIE 6921, 69211Z (March 21, 2008) E152 standard compliant prototype (spod) shows reticle protection down to 0.1 added particles per nm. with Inner Pod Exposed 30
31 In-situ Inspection Need to verify reticle cleanliness AFTER loading into scanner and BEFORE printing wafers Repeater concern is serious due to lack of pellicles ArF scanners have in-situ reticle inspection capability Not having in-situ capability would require printing of defect look-ahead wafers Manageable in development and perhaps in pilot line mode Unacceptable for HVM Need focus from tool vendors to have capability avaialable in HVM tooling platforms 31
32 Reticle Technical and Infrastructure Gaps Current reticle defectivity gap is about X Need continuous improvement Relaxation of flatness spec might help bridge gap Inspection gaps Actinic blank inspection Patterned defect inspection spec vs. actual In-situ inspection AIMs inspection SEMATECH is adopting a bridge tool solution for actinic blank and AIMS inspection so that some capability will be available for pilot line in 2011 Production actinic inspection, AIMS, and patterned inspection will require industry-wide funding (July workshop) 32
33 Summing Up 33
34 HVM Gaps - Overall Full field production scanner Source Resist Mask Blank Multilayer Dep Actinic Blank Inspection Actinic Defect Review Mask Patterned Inspection Suppliers building solutions? Yes Yes Yes Yes No No No Estimated Cost for HVM Solution Funded Funded Funded Funded >50M >50M >100M Table data from Bryan Rice, Sematech SEMATECH s EUV mask infrastructure strategy is: Obtain support from various partners (public and private) Commit most of SEMATECH s Litho budget to mask infrastructure over next four years Need industry consensus on required funding to bridge gaps 34
35 EUV Cost-Effectiveness COO! 35
36 Conclusions Substantial progress made on resist and tooling Resists typically about 2X from goal for sensitivity/lwr Laser power about 10X from goal Overall tool runrate requires ~ 20X improvement to 100wph goal Reticle defectivity is a major concern Blank defectivity needs substantial improvement Relaxation of flatness requirement might provide some mitigation Reticle inspection capability has major gaps. Need industry funding to enable tooling to be developed in time for HVM Academic exercise is over!! EUV has moved from research to implementation mode Problems left to be solved are largely engineering in nature Need sustained focus and industry-wide commitment to solve Ultimately EUV insertion will be based on a COO decision vs. ArF 36
37 No Exponential is forever, but we can delay forever Gordon Moore Scaling + Yield Defect Density (Log Scale) Source: Will EUV performance and COO enable us to continue to delay forever? forever? 37
38
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