The Pennsylvania State University. The Graduate School. College of Engineering NON-VOLATILE FERROELECTRIC TRANSISTOR BASED MEMORY DESIGN:

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1 The Pennsylvania State University The Graduate School College of Engineering NON-VOLATILE FERROELECTRIC TRANSISTOR BASED MEMORY DESIGN: DEVICE-CIRCUIT ANALYSIS CONSIDERING GATE LEAKAGE A Thesis in Electrical Engineering by Sandeep Krishna Thirumala 2018 Sandeep Krishna Thirumala Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science August 2018

2 The thesis of Sandeep Krishna Thirumala was reviewed and approved* by the following: Sumeet Kumar Gupta Assistant Professor of Electrical Engineering Thesis Advisor Mehdi Kiani Assistant Professor of Electrical Engineering and Computer Science Kultegin Aydin Professor of Electrical Engineering Head of Electrical Engineering Department *Signatures are on file in the Graduate School

3 iii ABSTRACT Ferroelectric Field Effect Transistors (FEFETs) are emerging devices which have immense potential to replace conventional transistors due to their unique characteristics. They are realized by employing a ferroelectric in the gate stack of transistors with an optional metal layer in between the ferroelectric and dielectric. FEFETs can behave as volatile steep switching devices by virtue of their negative capacitance, beating the fundamental Boltzmann limit of 60mV/decade. On the other hand, with proper capacitance matching between the ferroelectric and the underlying transistor, FEFETs can also achieve non-volatile operation, by virtue of the retention of its polarization states in the absence of external electric field. Gate leakage in FEFETs due to the presence of the floating intermediate metal layer, plays a crucial role in determining the device-circuit operation. The effect of gate leakage in the context of steep switching FEFETs has been well understood. Similarly, there is a need to understand the impact of gate leakage in non-volatile FEFETs. This thesis extensively analyses the implications of gate leakage in non-volatile FEFETs and their memory designs. We show that the gate leakage shifts the device characteristics towards the left or right depending on the polarization stored in the ferroelectric. We observe that the robustness of long-term retention in non-volatile FEFETs enhances and becomes as high as that of standalone ferroelectric capacitor in the presence of gate leakage. We describe how distinguishability between the bi-stable polarization states can be lost in the presence of gate leakage. We propose work-function engineering in conjunction with a modified read operation to re-establish the lost distinguishability. We also showcase the implications of gate leakage on FEFET based 2T, 3T and 4T memory designs. We explain why the traditional operating bias conditions cannot be implemented in the presence of gate leakage. We use work-function engineering along with a new read scheme to overcome the drawbacks of gate leakage. FEFET memories with gate leakage showcase 33% increase in write time respect to memories neglecting gate leakage. At iso write time condition of 200ps, the write energy of FEFET memories with gate leakage increases by 43%. The read power of memories with gate leakage shows 4-6X increase compared to memories neglecting gate leakage. We showcase that the readwrite metric overheads attained due to gate leakage can be significantly reduced by tuning device and circuit parameters.

4 iv TABLE OF CONTENTS List of Figures... vi List of Tables... ix Acknowledgements....x Chapter 1 INTRODUCTION EMERGING MEMORY TECHNOLOGIES MOTIVATION FOR THIS WORK THESIS ORGANIZATION... 8 Chapter 2 FERROELECTRIC TRANSISTORS DEVICE STRUCTURE DEVICE OPERATION MODES OF OPERATION Steep Switching FEFETs: Non-Volatile FEFETs: Chapter 3 MODELING AND CALIBRATION DEVICE MODELING CALIBRATION SIMULATION METHODOLOGY Chapter 4 GATE LEAKAGE IN FEFETs FEFET DEVICE CHARACTERISTICS INFLUENCE OF GATE LEAKAGE P HOLD=+P P HOLD=-P INFLUENCE OF DRAIN VOLTAGE CURRENT-VOLTAGE CHARACTERISTICS P HOLD=+P P HOLD=-P Chapter 5 WORKFUNCTION ENGINEERING DEVICE CHARACTERISTICS P HOLD=+P P HOLD=-P HOLD MARGINS EFFECT OF T FE AND SUPPLY VOLTAGE V DD Thickness of FE (T FE) Supply Voltage (V DD)... 29

5 v Chapter 6 NON-VOLATILE MEMORY FEFET BASED MEMORY DESIGNS T Memory T Memory T Memory MODIFIED MEMORY OPERATION Write Read Hold PERFORMANCE ANALYSIS Write Time Write Energy Read Power INFLUENCE OF DEVICE-CIRCUIT PARAMETERS Thickness of Ferroelectric (T FE) Supply Voltage (V DD) Kinetic Coefficient (ρ) Read Voltage (V READ) Work-function Engineering (ΔΦ ML) Chapter 7 CONCLUSIONS AND FUTURE WORK REFERENCES... 53

6 vi LIST OF FIGURES Figure 1-1. Processor and Memory speed over time illustrating the memory wall problem Figure 1-2. Memory taxonomy with variety of emerging NVMs fromthe 2015 ITRS ERD chapter Figure 1-3. (a) Cross-section of two PCM cells, one cell is in low resistance crystalline state, the other in high resistance amorphous state (b) Basic STT-RAM cell structure (c) RRAM cell showing the set and reset state Figure 1-4. (a) schematic of a ferroelectric capacitor (b) polarization vs voltage hysteresis loop defining 0, and 1 states (c) Device structure of 1T-1C FERAM Figure 1-5. Physical gate length scaling of FeFET compared to the embedded NVM logic platforms Figure 1-6. Functional unit-level benchmarking of different logic devices; many device concepts exist only in simulation (from [16]) Figure 1-7. Device structure of FEFET (a) without and (b) with an internal metal layer. (c) FEFET schematic illustration gate leakage in the presence of internal metal layer Figure 2-1. (a) Cross section of an FEFET based on FinFET structure (b) 3D view of the FEFET device (c) Schematic showing the integration of ferroelectric capacitor with the MOS capacitance Figure 2-2. Polarization vs applied electric field of a ferroelectric capacitor illustrating the negative capacitance region used for steep-switching applications Figure 2-3. (a) Schematic of FEFET showing the internal metal potential and (b) Current- Voltage characteristics of an FEFET illustrating the sensed currents, resistance states and value of VINT for the two bi-stable states Figure 2-4. Device structure showing (a) inversion caused in the channel due to positive polarization and (b) accumulation due to negative polarization Figure 3-1. Simulation methodology of the self-consistent approach for FEFET based device and circuit simulations Figure 3-2. Calibration of the LK model with the experimental values for remnant polarization and coercive fields [38] Figure 3-3. (a) Initialization procedure for non-volatile FEFET for (a) neglecting gate leakage and (b) with gate leakage

7 vii Figure 4-1. (a) Polarization vs applied voltage characteristics for standalone FE capacitor and FEFET illustration larger hysteresis for the former. (b) Internal metal potential vs gate voltage for FEFET illustrating the two bi-stable states Figure 4-2. Transient simulations showing the polarization retention with the discharge of V INT due to gate leakage Figure 4-3. (a) Schematic of FEFET (b) Polarization and (c) internal metal potential characteristics versus gate voltage illustrating the shift in the characteristics for P HOLD=+P Figure 4-4. (a) Polarization and (b) internal metal potential characteristics versus gate voltage illustrating the shift in the characteristics for P HOLD=-P Figure 4-5. Internal metal potential versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P with the application of drain voltage illustrating the increase in V INT Figure 4-6. Drain Current versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P illustrating the loss in distinguishability for the case P HOLD=+P Figure 5-1. (a) Schematic of FEFET illustrating work-function engineering at the internal metal. (b) Polarization and (c) internal metal potential versus gate voltage of FEFET with work-function engineering, illustrating the increase in V INT Figure 5-2. (a) Polarization and (b) internal metal potential versus gate voltage of FEFET with work-function engineering, illustrating the increase in V INT Figure 5-3. Internal metal potential versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P with the application of drain voltage illustrating the increase in V INT Figure 5-4. Drain Current versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P illustrating the re-establishment of distinguishability for the case P HOLD=+P Figure 5-5. Hold voltage margins for polarization retention vs thickness of the ferroelectric showing V M;FE-CAP=V M-LT>V M>V M-ST Figure 5-6. Polarization vs gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P showing the influence of thickness on the non-volatile hysteresis Figure 6-1. Schematic of (a) 1T-1C FERAM (b) 2T (c) 3T and (d) 4T FEFET based memory designs Figure 6-2. Layouts of (a) 1T-1C FERAM, (b) 2T, (c) 3T and (c) 4T FEFET based memory designs

8 Figure 6-3. (a) Drain current vs gate voltage characteristics with gate work-fucntion engineering at the internal metal layer showing the different sensed currents in linear scale. (b) proposed 2-step read scheme Figure 6-4. Transient waveforms of the 3T memory Figure 6-5. Impact of GL on Write Time of 2T, 3T and 4T FEFET based memory designs; T FE=3nm; V DD=1V Figure 6-6. Impact of GL on Write Energy of 2T, 3T and 4T FEFET based memory designs at iso-write time of 200ps; T FE=3nm; V DD=1V Figure 6-7. Impact of gate leakage on Read Power of 2T, 3T and 4T FEFET memories. Normalized with respect to memories neglecting gate leakage. T FE=4nm; V DD=1V Figure 6-8. Write time and write energy comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different thickness of the ferroelectric T FE; V DD=1V Figure 6-9. Normalized read power comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different thickness of the ferroelectric material T FE; V DD=1V Figure Write time and write energy comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different supply voltage V DD; T FE=3nm Figure Write time and write energy comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different Kinect coefficient of the ferroelectric material; T FE=3nm; V DD=1V Figure Read power comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different read voltages V READ Figure Read power comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different work-function engineering of the internal metal layer viii

9 ix LIST OF TABLES Table 3-1. Extracted LK parameters after calibration of the model with experiments Table 5-1. The design space analysis of the FEFET in the presence of gate leakage with respect to two parameters: Thickness of the ferroelectric (T FE) and Supply voltage (V DD) Table 6-1. Operating bias conditions for the 3T FEFET based memory design in the presence of gate leakage Table 6-2. Value of polarization corresponding to the sensed currents in the 2-step read operation Table 6-3. Value of sensed currents at each step of the read operation corresponding to polarization (P FE) stored in the ferroelectric... 39

10 x ACKNOWLEDGEMENTS I would like to thank my academic advisor, Professor Sumeet Kumar Gupta wholeheartedly, for his excellent guidance and mentorship at every step during the entire duration of my graduate studies. I am immensely indebted to him for challenging me and providing me with an excellent research environment. Without his support and his supervision, this thesis would not have been possible. Besides my advisor, I would like to thank my thesis committee member, Professor Mehndi Kiani for generously offering his time, guidance and good will during the preparation and review of this document. I am thankful to him for his valuable feedback. I wish to thank my fellow lab mates in the Integrated Circuits and Device Laboratory. I have had a good fortune to work with them as my colleagues and my friends. I am specifically grateful to Atanu Kumar Saha and Sumitha George for their assistance during the development of this research work. I would like to thank to all my friends who gave me good advice and made this journey enjoyable. In particular, I would also like to express my sincere thanks to Sujata Khandare, Sakthi Kumar and Naveen Kumar for all their support in motivating and guiding me through my entire graduate studies at the Pennsylvania State University. Finally, the most special thanks goes to my sister Lalenthika Krishna for constantly supporting me during the course of my graduate studies. My deepest gratitude goes to my parents, Madhusudan Thirumala and Shanthy Madhusudan for their dedication, motivation and unconditional love throughout that provided the foundation for this work.

11 Chapter 1 INTRODUCTION One of the consequences of Moore s law and the performance improvement we expect it to follow is the so called Memory Wall [1]. Over the years it has been observed that the microprocessor performance is improving at the rate of ~2x every two years [2]. The memory capacity has also been observed to double every two years. However, the memory latency i.e., duration for a memory operation, has only been improving by only ~1.1x every two years [2]. This gap between the performance of the processor and memory is called the memory wall (as shown in Fig. 1-1), which causes a critical challenge for high speed computer system design in future technology generations. The ever increasing number of cores and performance of computing, require more on-chip data storage to meet their processing throughput. Several modifications to the SRAM/DRAM architecture have been made to reduce the gap between processor and memory performance including, adding multiple levels of caches, and designing processors to pre-fetch and tolerate latency [3]. However, the low density of the conventional SRAM technology limits the on-chip memory capacity. Moreover, the high leakage power consumption of traditional SRAM/DRAM architectures with technology scaling further impedes the memory hierarchy design [4]. Also, conventional memories become more and more vulnerable to radiation-based soft errors with scaling and extra overhead of error correction limits the improvement of performance and leads to Fig. 1-1 Processor and Memory speed over time illustrating the memory wall problem.

12 2 more power consumption [5]. Therefore it important to come up with novel devices for memory implementation which can mitigate the drawbacks of the traditional memory architectures. 1.1 EMERGING MEMORY TECHNOLOGIES With CMOS scaling approaching fundamental limits, various emerging nonvolatile memory (NVM) technologies have been proposed to replace/complement SRAM/DRAM architectures because of their intriguing advantages such as high density, zero standby power, fast access speed, non-volatility, etc. [1]. Although high-performance computing is still a key driver for technology innovation, consumer electronics is shifting toward mobile, pervasive connectivity, and data-centric applications. The changing market trends impose different hardware requirements, such as ultra-low power, high-density and low-cost data storage. Emerging NVMs with improved speed, scalability and retention may become important technology enablers for efficient and intelligent hardware systems in the near future. Fig. 1-2 shows the memory taxonomy from the 2015 ITRS Emerging Research Devices (ERD) chapter [6]. Both prototypical and emerging non-volatile memories are based on novel Fig. 1-2 Memory taxonomy with variety of emerging NVMs from the 2015 ITRS ERD chapter [6].

13 3 materials and mechanisms which are drastically different from the traditional CMOS based memories. The phase change memories (PCMs) are based on reversible transition between the amorphous phase (high resistance) and the crystalline phase (low resistance) of chalcogenides (Fig. 1-3(a))[1]. They demonstrate desirable characteristics such as longer retention, improved endurance and showcase functionality at scaled dimension. However, the large latency of transition between the two phases (~100ns) and their high read/write power consumptions hinders their direct implementation in circuit design [7]. STT- MRAM is another non-volatile memory which comes under the class of emerging technologies. It is based on a magnetic tunnel junction (MTJ) cell [1] with an architecture composed of one transistor and one resistor (1T-1R; Fig. 1-3(b)). The resistance of the MTJ depends on the relative magnetization of the free layer (FL) with respect to the pinned layer (PL). Parallel magnetization imply low resistance state (LRS) while anti-parallel magnetizations imply high resistance state (HRS). They showcase fast read/write latencies (~10ns) when compared to PCMs and also smaller device footprint for high integration densities [1,7]. However, the major disadvantage appears to be the high write current. While this technology has enough read current to guarantee a fast access time, it requires a very large write current (ma range), which increase power consumption [1]. Also, the distinguishability between the two nonvolatile states (HRS/LRS) is low (~7x [13]) when compared to other emerging technologies (~orders of magnitude), leading to challenges during current sensing [8]. Another class of emerging technologies are Resistive RAMs (RRAMs). They are normally referred as those NVM technologies built on the resistance changing mechanisms, other than PCM and STT-RAM. The storage mechanisms of RRAM devices can be categorized as (but not limited to) space-chargelimited-current (SCLC), filament, Schottky contact and traps (SCT), etc. [9]. RRAM switching is generally attributed to the formation and rupture of conductive filaments in insulating oxides (Fig. 1-3(c)) [9]. Tradeoffs exist among key RRAM parameters, e.g., speed-retention, power-speed, Fig. 1-3 (a) Cross-section of two PCM cells, one cell is in low resistance crystalline state, the other in high resistance amorphous state (b) Basic STT-RAM cell structure (c) RRAM cell showing the set and reset state.

14 4 Fig. 1-4 (a) Device structure and (b) schematic of 1T-1C FERAM (c) polarization vs voltage hysteresis loop defining 0, and 1 states. endurance-retention, etc. A major challenge of RRAM is reliability and mainly variability. The switching process is not controlled microscopically and is intrinsically stochastic, which is reflected in the large variation of device resistance and switching voltage from cycle to cycle and from device to device [1]. Ferroelectric capacitor based memories have been proposed and industrially implemented using their unique property of polarization retention in the absence of an external electric field [10]. The memory follows a 1T-1C architecture, where the binary states are encoded in the polarization state of the ferroelectric as shown in Fig. 1-4 [10]. They offer high endurance along with high integration densities close to DRAMs. However, their read operation is destructive and requires a write back operation, leading to read-write conflicts and large energy overheads [10, 13]. Also, they employ voltage based sensing, whose speed is limited by the bit line/ plate line capacitance and the low capacitance distinguishability between their bi-stable states [13]. Moreover, they require application of large operating voltages leading to high energy requirements [13], resulting in various issues during their integration with CMOS circuits. Therefore, there is a pressing need for novel non-volatile memory solutions to counter the limitation with the existing technologies. 1.2 MOTIVATION FOR THIS WORK Recent advancements with the possibility of direct integration of ferroelectric layer in the gate stack of FETs has led to the realization of a non-volatile ferroelectric field effect transistor (FEFET) [14]. Hafnium oxide based ferroelectrics showcase excellent compatibility with the CMOS process flow resulting in the possibilities of achieving FEFETs even at scaled technologies

15 5 Fig. 1-5 Physical gate length scaling of FEFET compared to the embedded NVM logic platforms (from [15]). [14]. Fig. 1-5 illustrates that the HfO 2 based ferroelectrics enable a scalable (CMOS compatible) emerging NVM that keeps pace with the scaling demands of leading-edge logic technologies [15]. In this memory device, the binary states are encoded in the form of the polarization of the ferroelectric. The direction (value) of polarization determines the resistance state of the underlying transistor. If the polarization points towards the channel region (+P), inversion of the channel occurs which results in the transistor turning ON (LRS) whereas accumulation is induced in case the polarization points into the opposite direction (-P), which corresponds to the transistor being OFF (HRS) [30]. FEFETs overcome the aforementioned problems faced in FRAMs (or FERAMs) by virtue of (i) control of drain current by the FE polarization and (ii) low voltage switching of polarization due to the capacitive coupling of ferroelectric and the underlying transistor [13]. Such unique properties allow the separation of read and write paths of the memory and mitigate the challenges of design conflicts faced in FRAMs [13]. Moreover, FEFETs are well positioned in the functional unit level benchmarking of various emerging technologies as shown in Fig. 1-6 [16]. Two device structures of ferroelectric transistor have been prominently studied over the past decade: (i) with an internal metal layer in between the ferroelectric and dielectric layers as shown in Fig. 1-7(b) [17] and (ii) featuring direct integration of ferroelectric layer on top of the dielectric layer as shown in Fig. 1-7(a) [18]. FEFETs without the internal metal layer can undergo remarkable deterioration in its performance due to its sensitivity to defects in the FE layer resulting in trapping and de-trapping process [19]. Non-uniform electric fields across the FE may also lead to performance and retention degradation along with variability [20]. On the other hand, FEFETs

16 6 Fig. 1-6 Functional unit-level benchmarking of different logic devices; many device concepts exist only in simulation (from [16]). with the internal metal layer are expected to have much better retention [20]. However, since the internal metal layer is floating, gate leakage can result in several issues. This work focusses on FEFET with IML and discusses the implication of gate leakage. Gate leakage in the context of Steep switching FEFETs (also known as negative capacitance FETs; NCFETs) with an internal metal layer has been studied in detail [21]. It has been shown that, unless properly engineered, leakage results in degradation of the NCFET performance [22]. Work-function engineering of the ferroelectric has been proposed, where metals of dissimilar work-functions are used as the external gate electrode and the intermediate metallic layer. This helps in mitigating the challenges associated with gate leakage in steep switching FEFETs [22]. However, the effects of leakage on cycling, imprint and circuit performance has yet to be analyzed. Fig. 1-7 Device structure of FEFET (a) without and (b) with an internal metal layer. (c) FEFET schematic illustration gate leakage in the presence of internal metal layer.

17 7 Similarly, there is a pressing need to study the impact of gate leakage in non-volatile FEFETs. Gate leakage in non-volatile FEFETs can potentially lead to loss in distinguishability of the bi-stable resistance states (at V GS=0V) for the bi-stable ferroelectric polarization states +P and -P. This might results in loss in the robustness of functionality in non-volatile FEFETs based circuits. Moreover, due to the discharge of internal metal potential over time (due to gate leakage), the device characteristics are also expected to change and it is important to understand such effects of gate leakage. In this thesis, we perform a detailed analysis of FEFETs with a focus on the impact of gate leakage on the device-circuit performance. We study the influence of gate leakage extensively, on various FEFET based 2T [13], 3T [23] and 4T [24] memory designs. The contributions of this work are as follows: We discuss the impact of gate leakage on the device characteristics of FEFETs. We showcase the offset in the polarization and internal metal potential characteristics, caused due to gate leakage. We showcase that the initial polarization stored in the ferroelectric determines the direction of offset. We point out the problem of loss in the current based distinguishability of the bi-stable states in FEFETs due to gate leakage. We propose gate work-function engineering of the ferroelectric by using metals with dissimilar work-functions across the ferroelectric layer to re-establish the lost distinguishability of the bi-stable states. We explain the implications of gate leakage on FEFET based 2T, 3T and 4T memory designs and propose a modified read operation in order to counter the problem caused by gate leakage and distinguish between the bi-stable polarization states. We compare the read-write performance metrics of FEFET based memories with and neglecting gate leakage. We also showcase the trends considering various material, device and circuit parameters, such as kinetic coefficient of ferroelectric, thickness of ferroelectric, power supply, read voltage and gate work-function of the intermediate metal layer.

18 8 1.3 THESIS ORGANIZATION This thesis is organized as follows: Chapter 2 familiarizes the reader with the basics of ferroelectric FETs. It describes the device structure and explains the two possible device variants achieved by the coupling of ferroelectric with the transistor. Chapter 3 describes the modeling and simulation framework used in this thesis. Chapter 4 elucidates the effect of gate leakage in FEFETs due to the presence of the floating intermediate metal layer. It explains the offset seen in the device characteristics in the presence of gate leakage. Chapter 5 and 6 proposes gate work function engineering and a new read scheme to overcome the challenges associated with gate leakage for FEFET based memories. Chapter 6 also describes the performance analysis of FEFET based memories considering various material, device and circuit parameters. The contributions, conclusion and scope for future work are presented in Chapter 7.

19 9 Chapter 2 FERROELECTRIC TRANSISTORS 2.1 DEVICE STRUCTURE Ferroelectric field effect transistors (FEFETs) are structurally similar to a regular MOSFET or FinFET, with an additional ferroelectric and metal layer integrated on the gate stack [25-26]. The schematic and 3D view of an FEFET is shown in Fig. 2-1(a, b). The metal layer in-between the ferroelectric and dielectric layer is optional. The capacitance of ferroelectric interacts with the underlying MOS capacitance (CMOS) resulting in unique characteristics (Fig. 2-1(c)). Previously investigated ferroelectric materials such as PZT for FRAMs tend to show incompatibility with the CMOS process flow [27]. In 2011, ferroelectric behavior in doped hafnium oxide (HZO) was published for the first time [28]. This was discovered due to the fact that hafnium oxide was already introduced as high-k dielectric in the gate stack of MOSFETs/FinFETs. Soon, preliminary works were published which could verify the functionality of HZO-based ferroelectric field effect transistors (FEFETs) [14]. The FE layer can be employed with both n-type and p-type transistors. Hence, depending on the circuit requirements in terms of employing the FEFET in the pull-down or pull-up network of the circuit, one or the other type of FEFET can be used. Over the years, rigorous research on ferroelectric materials, has led to the possibilities of achieving ferroelectric properties at thickness < 2nm, resulting in realization of FEFETs even at scaled technologies, such as FinFETs [29]. The high compatibility of HZO with CMOS processes has mitigated concerns regarding large-scale demonstrations of FEFETs at scaled technologies, which might have impeded industrial-scale realizations earlier. Fig. 2-1 (a) Cross section of an FEFET based on FinFET structure (b) 3D view of the FEFET device (c) Schematic showing the integration of ferroelectric capacitor with the MOS capacitance.

20 DEVICE OPERATION Two properties of FE integrated in the gate stack of a transistor make FEFETs unique: (i) negative capacitance of FE, which yields steep switching characteristics of FEFETs (volatile) for logic applications [29] and (ii) polarization retention capability in the absence of electric field, which combined with the transistor action leads to a built-in non-volatility in the transistor (useful for memory applications) [30]. While the former approach is being actively explored to enable ultra-low power operation [31], the latter design is of particular interest in this work. It has been shown that, by changing the capacitance matching between the FE and the underlying transistor, for instance by varying the FE thickness (T FE), one can operate the FEFETs in non-volatile or volatile mode [32]. Note that, for either of the operation modes, the device structure remains the same. Next, we briefly discuss about the two variants of FEFET devices. 2.3 MODES OF OPERATION Steep Switching FEFETs: The steep switching mode of FEFET was proposed conceptually in 2008 by Salahuddin and Datta [26]. It was envisioned that the ferroelectric insulator present on the gate stack of the transistor follows an S curve trajectory for polarization switching. The snap back of the S curve exhibits a negative capacitance (dq/dv) due to the negative slope as shown in Fig. 2-2 [26]. In reality, this corresponds to an unstable region of operation for ferroelectrics. However, with the capacitive coupling of the underlying transistor, this negative capacitance of ferroelectric can be stabilized [26]. This is made possible by ensuring that the net gate capacitance, which is the series combination of ferroelectric capacitance and the underlying MOS capacitance, is positive. Stabilizing the operation of the ferroelectric in the negative capacitance region, achieves a voltage step-up action, which reduces the sub-threshold swing below the theoretical limit of 60 mv/ decade limit, enabling low-voltage/low-power operations [26, 29]. Over the last 5-6 years, various experimental works have showcased the negative capacitance effect with steeper slopes in the transistor s transfer characteristics [14, 25].

21 11 Fig. 2-2 Polarization vs applied electric field of a ferroelectric capacitor illustrating the negative capacitance region used for steep-switching applications. Figure from [54] Apart from the steep slope characteristics, these negative capacitance FETs also showcase other unique features. NCFETs achieve higher ON current and exhibit negative differential resistance (NDR), both of which have a vast application space. For example, NDR can be used in designing hysteretic inverter characteristics, resulting in larger voltage margins for output transitions [REF] Non-Volatile FEFETs: As mentioned before, FEFET can be operated in the non-volatile mode with proper capacitance matching between the ferroelectric capacitor and the underlying CMOS capacitance [13, 32]. In this mode, the ferroelectric operates with hysteretic polarization versus gate voltage characteristics spanning over positive and negative gate voltages (unlike NCFETs, where the FE is operated in the non-hysteretic S curve /negative capacitance region). It has been showcased that due to the interaction of the MOS capacitance (when FE is placed in series with a transistor), the effective hysteresis of the polarization versus gate voltage of the FEFET decreases when compared to the hysteresis exhibited by a standalone ferroelectric capacitor [13, 23]. Nevertheless, Fig. 2-3 (a) Schematic of FEFET showing the internal metal potential and (b) Current- Voltage characteristics of an FEFET illustrating the sensed currents, resistance states and value of V INT for the two bi-stable states.

22 12 Fig. 2-4 Device structure showing (a) inversion caused in the channel due to positive polarization and (b) accumulation due to negative polarization. sufficiently thick layer of ferroelectric preserves the hysteresis and bi-stable polarization states. As mentioned in chapter 1, positive polarization in the FE corresponds to a positive V INT, which is greater than the transistor threshold voltage (V TH). This causes inversion of the channel, leading to the FEFET turning ON (low resistance state/lrs; Fig. 2-3(b) and Fig. 2-4(a)). A negative polarization corresponds to a V INT <0 (which is also <V TH), resulting in accumulation in the channel of the underlying FET. This corresponds to the OFF state (high resistance state/ HRS) of the FEFET as shown in Fig. 2-3(b) and Fig. 2-4(b). In the absence of any electric field, due to the intrinsic property of the ferroelectric material, the FE layer retains its polarization. Polarization retention directly corresponds to the resistance state of the FEFET also being retained, leading to built-in non-volatility in the transistor. Such devices with a unique property of in-built non-volatility have a vast application space in non-volatile circuits and systems. From a systems perspective, on-chip non-volatile memory can help in reducing the long-distance transmission overheads, leading to reduced check-pointing operations encountered with the traditional CMOS systems [33]. This can in turn help in achieving a significant boost in the forward progress of computation [13]. In this work, we primarily focus on non-volatile FEFETs and their memory implementation. With the basic understanding of the FEFETs mentioned above, we proceed forward to the modeling and calibration approach for the non-volatile FEFETs used in this work, in the next chapter.

23 13 Chapter 3 MODELING AND CALIBRATION 3.1 DEVICE MODELING To understand the interaction of ferroelectric layer with the underlying transistor in FEFETs, transistor equations must be solved self-consistently with the Landau-Khalatnikov (LK) equation of the ferroelectric [34]. The approach for modeling of FEFETs for device and circuit design, strongly depends on the absence or presence of the internal metal layer. In this study, we consider FEFETs with an intermediate metal layer between ferroelectric and dielectric layers of the gate stack. To understand the impact of the intermediate metal layer, let us first consider the multidomain LK equation [35]: E ρdp/dt = αp + βp 3 + γp 5 + [ 1 K 2 P d 2 P/dx 2 ] (1) where P is the polarization, E is the electric field and α, β, γ are static co-efficients of the LK equation. The term ρ corresponds to the kinetic coefficient of the ferroelectric, which determines the polarization switching speed. The term K P is called the domain interaction parameter. In the presence of the internal metal layer (which acts as an equipotential surface), screens out the non-uniformity of electric field across the ferroelectric and on the underlying transistor. Ignoring other non-idealities, this corresponds to equal polarization in all the domains and the term in the parenthesis becomes equal to 0 [36]. Now, the updated LK equation (2) can be treated as a single domain LK equation. E ρdp/dt = αp + βp 3 + γp 5 (2) Fig. 3-1 Simulation methodology of the self-consistent approach for FEFET based device and circuit simulations

24 14 To evaluate the ferroelectric-based device and circuit designs, we employ a physics-based circuit compatible SPICE model for ferroelectric transistors (FEFETs) based on time-dependent Landau Khalatnikov equation with single domain approximation, coupled with predictive technology models for the transistor [36] (Fig. 3-1). The presence of internal metal layer in our work justifies the use of the single domain approximation as explained above. In our model, the transistor equations (Poisson s equation and the drift-diffusion current continuity equations) are solved self-consistently with the Landau Khalatnikov (L-K) equation of the FE. Depolarization fields due to the presence of non-ideal contacts have been considered in the model. Implementation of the model entirely in SPICE enables efficient monitoring of the device variables, such as internal metal potential, polarization of FE, device currents etc. We employ a predictive technology model of 10nm high performance FinFET (with gate length=14nm, fin thickness=8nm, fin height=21nm) as the underlying transistor (of FEFET) in this work, showing the device-circuit designs in scaled technologies [37]. However, similar approach can be used for the evaluation of planar/bulk CMOS devices, which might have their own advantages. 3.2 CALIBRATION Hafnium Zirconium oxide (HZO) has recently been an emerging candidate for ferroelectric devices. It showcases ferroelectric properties along with easy CMOS process compatibility [27-28]. Therefore, in our study we use experimental data of Hf 0.7Zr 0.3O 2 with remnant polarization (P R) =3μC/cm 2 and coercive field (E C) =1.4MV/cm [38], to calibrate our FEFET model (Fig. 1(a)). The static coefficients (α, β and γ) of the LK equation were extracted from the polarization versus voltage (P-V) loop measured from experiment [36] and are shown in Fig. 3-2 To reflect different polarization switching speeds in the FEFET model, the kinetic coefficient ρ is varied from 0.05 to 0.5 ohm-m, which corresponds to a polarization switching time of 50ps (ρ = 0.05 ohm-m) to 200ps (ρ = 0.5 ohm-m) [39]. Our model captures the trends shown in non-volatile FEFET experiments [40].

25 15 Fig. 3-2 Calibration of the LK model with the experimental values for remnant polarization and coercive fields [38]. Table. 3-1 Extracted LK parameters after calibration of the model with experiments. 3.3 SIMULATION METHODOLOGY Initialization of polarization is an important step before simulating FEFET based devices and circuits. SPICE based simulations consider all voltage parameters to start with 0V. Since the ferroelectric model used in this work is based on a voltage controlled voltage source, the initial polarization of the FE, before the application of any external signals is also 0. This can be thought of as unpoled state of the FE. However, after poling, the polarization of FE is either +P or P for non-volatile FEFETs (unlike NCFETs, which are stabilized in the negative capacitance region). It is important to note that the LK path traverses through (0,0) which is an unstable but valid solution. Therefore, it is import to initialize the polarization of FE (P FE) before non-volatile FEFET based device-circuit simulations. The initialization process varies for the two different FEFET device structures (as mentioned earlier) which is discussed as follows: For FEFETs without an IML, we drive V GS of the device to V DD in order to attain a negative polarization (-P). This corresponds to the device being OFF with a negative V INT, which is retained, (does not discharge through the FE or DE) due to the absence of IML. Therefore, the initial conditions are: P FE=-P and V INT<0V at V GS=0V and V DS=0V (Fig. 3-

26 16 3(a)). Subsequent application of voltage cycles (-V DD V DD -V DD) yields the P-V GS hysteresis loop. Note that, this initialization process can be used for FEFETs with IML if gate leakage is neglected. FEFETs with IML undergo a slightly different initialization process. In our simulations, we start with V GS to -V DD to drive the polarization to P. Then, we let the negative V INT achieved, to discharge (to 0V) due to gate leakage through the FE and DE layers before proceeding with the device-circuit simulations. In this case, the initial conditions are: P FE=- P and V INT=0V at V GS=0V and V DS=0V (Fig. 3-3(b)). Subsequent voltage cycles (-V DD V DD -V DD) leads to the hysteretic polarization versus voltage characteristics. Note, that the initial polarization can be driven to +P as well. However, in our simulations we keep the devices in the OFF state by driving it to -P. Fig. 3-3 (a) Initialization procedure for non-volatile FEFET for (a) without gate leakage and (b) with gate leakage.

27 17 Chapter 4 GATE LEAKAGE IN FEFETs 4.1 FEFET DEVICE CHARACTERISTICS In order to understand the influence of gate leakage (GL) in FEFETs, we first describe the device operation and characteristics without GL. As described before, FEFETs are realized by integrating an FE capacitor with a MOSFET [21-26]. With proper capacitance matching, FE interacts with the underlying MOS capacitance (C MOS) resulting in unique non-volatile features [13, 30]. Fig. 4-1(a) illustrates the polarization (P) versus applied voltage (V FE) for a stand-alone FE capacitor. The remnant polarizations (+/-P R; polarizations at V FE=0V) represent the non-volatile b- stable states in the absence of an external electric field. The coercive voltages (+/-V C-FE) determine the critical voltage required for polarization switching in FE. The degree of non-volatility of the FE, can be obtained by the area under the hysteretic curve multiplied by the cross-sectional area of the FE (to the first order) [23]. Lower magnitudes of P R and/or V C-FE corresponds to lower degree of non-volatility in FE. On the other hand, in an FEFET, the FE layer is integrated in the gate stack of a transistor (Fig. 3-1) and therefore, the FE capacitance (C FE) is connected in series with C MOS. The series C MOS (which is non-hysteretic) reduces the coercive voltages (V C-FE), as well as P R of the overall structure thereby, reducing the overall hysteresis in FEFET. This can be observed in the P versus gate voltage (V GS) characteristics for an FEFET in Fig. 4-1(a). As a result, FEFETs tend to exhibit lower degree of non-volatility compared to a stand-alone FE capacitor. The polarization of FE in the FEFET corresponds to an internal metal potential (V INT) i.e, the voltage driving the gate of the underlying transistor. When polarization is positive (+P), V INT attained is also positive and greater than the threshold voltage of the transistors (V TH). This results in the FEFET being in the ON state, i.e., application of drain voltage (V DS) will correspond to a flow of current in the device (I LRS; Fig.2-3(b)). Similarly, when the polarization of the FE (P FE) is negative (-P), V INT attained is also negative which is less than V TH, corresponding to the device being OFF and extremely low current flow (I HRS; Fig.2-3(b)). Now, due to the bi-stability of the

28 18 Fig. 4-1 (a) Polarization vs applied voltage characteristics for standalone FE capacitor and FEFET illustration larger hysteresis for the former. (b) Internal metal potential vs gate voltage for FEFET illustrating the two bi-stable states. polarization at V GS=0V, V INT of the FEFET also achieves bi-stability, thereby retaining its resistance state (HRS or LRS) in the absence of any gate voltage as shown in Fig. 4-1(b). The currents corresponding to the two states, showcase excellent distinguishability, I LRS/I HRS~10 6. This makes FEFET a very unique transistor, which possess the ability of performing logic operations along with built in non-volatility. 4.2 INFLUENCE OF GATE LEAKAGE The presence of the floating internal metal layer in the FEFET device structure. can lead to GL thorough the FE and DE layers in non-volatile FEFETs. This results in the discharge of V INT to 0V over time. In our simulations the leakage is modeled and captured by resistances of ferroelectric and dielectric (R FE and R DE) as shown in Fig. 1-7(c). V INT discharge due to GL results in loss in distinguishability between the LRS and HRS corresponding to (stored) polarizations +P and P, respectively. This is because, the transistor remains OFF for both +P and -P stored in the FE after V INT discharges to 0V (which is less than V TH of the underlying transistor). However, it is important to note that the polarization of FE is not affected due to its unique intrinsic property of polarization retention in the absence of an electric field. This retained polarization stores the bit information of the FEFET. In our further discussion, the retained polarization after V INT discharge (to 0V) will be referred to as the hold polarization, P HOLD. Now, two possible cases of P HOLD exists: (i) +P and (ii) -P. We will look into these cases one by one, next.

29 19 Fig. 4-2 Transient simulations showing the polarization retention with the discharge of V INT due to gate leakage P HOLD=+P In this case, the initial conditions are P FE =P HOLD=+P, V INT=0V at V GS=0V and V DS=0V. Considering these as the initial conditions for subsequent access of the device in a circuit, we perform the analysis of the device characteristics by first sweeping gate voltage, V GS from 0V to a negative value (0V -1V). Since P FE is initially positive and V INT = 0V, the polarization switching from +P -P will occur at V GS = V FE = -V C-FE (since, V FE = V GS - V INT). Recall, -V C-FE is the coercive voltage of FE A capacitor for +P -P switching, (Fig. 4-1(a)). This corresponds to the critical V GS for polarization switching to be as high as that of standalone ferroelectric capacitor, which is higher (i.e., V GS is lower) than the case in which GL is not considered (see Fig. 4-3(b)). Recall that V INT >0V for P FE=+P when gate leakage is not considered. However, since V INT=0V in the presence of Fig. 4-3 (a) Schematic of FEFET (b) Polarization and (c) internal metal potential characteristics versus gate voltage illustrating the shift in the characteristics for P HOLD=+P;T FE=3nm

30 20 gate leakage, +P -P switching yields a more negative V INT when compared to the case neglecting gate leakage (see Fig. 4-3(c)). More negative V INT in turn, results in a lower critical value of V GS for the subsequent -P +P switching cycle (Fig. 4-3(b)). Therefore, the net effect of GL in this case (P HOLD=+P) is to shift the device characteristics towards the left with respect to the case when GL is not considered. Note that the value of V INT in this case always remains less than or close to 0V P HOLD=-P In this case the initial conditions are: P FE =P HOLD = -P, V INT = 0V at V GS = 0 and V DS = 0V. Sweeping V GS from 0V to a positive value (0 +1V) results in polarization switching from negative to positive value (-P +P) at V GS=V FE=+V C-FE, which is the coercive voltage of a standalone ferroelectric capacitor. Recall that V INT <0V for P FE=-P when gate leakage is not considered. However, since V INT=0V in the presence of gate leakage, -P +P switching yields a more positive V INT when compared to the case neglecting gate leakage (see Fig. 4-4(b)). More positive V INT corresponds to a less negative value of V GS for the subsequent +P -P switching. Therefore, the effect of GL in this case (P HOLD=-P) is to shift the device characteristics towards the right. Note that in this case the value of V INT always remains close to or greater than 0V. Fig. 4-4 (a) Polarization and (b) internal metal potential characteristics versus gate voltage illustrating the shift in the characteristics for P HOLD=-P. T FE=4nm

31 21 Fig. 4-5 Internal metal potential versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P with the application of drain voltage illustrating the increase in V INT;T FE=3nm 4.3 INFLUENCE OF DRAIN VOLTAGE Application of a positive drain voltage corresponds to an increase in the internal metal layer potential. This is attributed towards the capacitive coupling between the drain terminal and the internal metal [31]. Due to the increase in V INT on the application of V DS, the critical gate voltage which is given by V GS=V FE+V INT becomes more positive for -P +P polarization switching compared to the case when drain voltage is not applied. Similarly, in the reverse direction, due to the higher V INT, the critical gate voltage required for +P -P switching is less negative than the case when V DS=0V. Therefore, the net effect of the application of V DS is to shift the V INT vs V GS characteristics towards the right (and upwards; Fig. 4-5 (b)). Also, the polarization versus V GS characteristics shifts towards the right (Fig. 4-5 (c)). 4.4 CURRENT-VOLTAGE CHARACTERISTICS The drain current (I DS) of the FEFET is used to sense the state of polarization stored in the FE layer, as mentioned before. However, due to gate leakage, distinguishing the non-volatile states based on the current might be challenging. To understand this further, we discuss the drain current versus gate voltage characteristics of FEFETs now. Let us perform the analysis case by case for P HOLD = +P and P, like before.

32 P HOLD=+P As discussed in the previous section for P HOLD=+P, V INT always remains less than or close to 0V for the entire range of V GS (-1 +1). With the application of drain voltage, V DS=0.3V, the value of V INT increases, which corresponds to its characteristics shifting upward. However, even with this upward shift, the magnitude of V INT always remains less than the transistor threshold voltage, V TH (~0.25V) as shown in Fig. 4-5(a). This corresponds to the FEFET remaining in the OFF state for the entire range of V GS, leading to loss in distinguishability of its bi-stable states as shown in Fig. 4-6(a). Note, polarization switching does occur as explained before, but V INT always remains less than V TH, leading to the FEFET being in the HRS state for both P FE= +P and -P P HOLD=-P For P HOLD=-P, V INT remains close to or greater than 0V for the entire range of V GS in the absence of V DS as discussed before. When a positive V DS is applied, V INT value increases and shifts upward as explained above. In this case, application of V DS corresponds to V INT>V TH for P FE=+P and V INT<V TH for P FE=-P. Therefore, the FEFET remain in the OFF state (HRS) for P FE=-P and ON state (LRS) for P FE=+P as shown in Fig. 4-6(b). This leads to excellent distinguishability between the bi-stable states, which is in the order of ~10 4. Now, even though the case P HOLD =-P retains the traditional FEFET characteristics as described above, the usage of this device is not feasible for circuit applications. This is because of Fig. 4-6 Drain Current versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P illustrating the loss in distinguishability for the case P HOLD=+P; T FE=3nm

33 23 the other case P HOLD=+P, showing a loss in distinguishability of the states because of V INT remaining less than V TH for both P FE=+P and P (due to gate leakage). This leads to loss in robustness of non-volatiles FEFETs, leading to no practical application possible. However, it is very important to note that, the information of the FEFET is still retained in the polarization state of the ferroelectric (if not V INT) which can be further harnessed for the implementation of this device in circuit applications. Therefore, it is important to re-design and engineer this device in order to revive the distinguishability of the bi-state states, especially for the case P HOLD=+P. In the next two chapters we propose a solution using work-function engineering along with a new read scheme for sensing the polarization of the ferroelectric, to overcome this issue with FEFETs in the presence of gate leakage.

34 24 Chapter 5 WORKFUNCTION ENGINEERING The inability of FEFETs to showcase current distinguishability between their bi-stable states in the presence of gate leakage (especially with the case P HOLD=+P), leads to loss in the robustness of non-volatility, for their direct implementation in circuits. Therefore, device level design changes are required in order to mitigate the issues faced due to gate leakage. The main challenge is with the case P HOLD=+P as discussed before. Therefore, we need a targeted solution to tackle the problem which exhibits V INT < V TH for the entire range of V GS. We propose work-function engineering at the internal metal layer and the gate in order to counter the effect of gate leakage in non-volatile FEFETs. This helps in lowering the threshold voltage such that, sufficient current is obtained for P FE = +P for the FEFET starting with P HOLD=+P. Workfunction reduction by ΔΦ ML can be thought of as the effective gate voltage of the underlying FET (V INT-EFF) to increase by the value ΔΦ ML, i.e V INT-EFF=V INT+ΔΦ ML. In other words, V INT-EFF versus V GS characteristics, shift upwards with respect to the case when there is no gate work-function engineering. Note that work-function engineering does not change the polarization vs V GS characteristics. This is because V FE, which determines the polarization stored in FE, remains equal to V GS-V INT. Only the effective voltage seen by the underlying transistor, V INT-EFF changes. Let us try to understand the impact of work-function engineering on the device characteristics case by case. 5.1 DEVICE CHARACTERISTICS P HOLD=+P As described above, the effect of gate work-function engineering at the intermediate metal layer is to shift the V INT-EFF characteristics upward when compared to the case without workfunction engineering as shown in Fig. 5-1(a). We use ΔΦ ML = 0.14eV, which shifts the characteristics upward by 0.14V in our analysis to showcase the trends. Now, with the application

35 25 Fig. 5-1 (a) Schematic of FEFET illustrating work-function engineering at the internal metal. (b) Polarization and (c) internal metal potential versus gate voltage of FEFET with work-function engineering, illustrating the increase in V INT; T FE=3nm of drain voltage V DS, these characteristics further shift upward as shown in Fig. 5-3(a). This results in re-establishment of distinguishability of the bi-stable states for the case P HOLD=+P as shown in the current characteristics in Fig. 5-4(a). This is because, we attain V INT-EFF < V TH for P FE=-P and V INT-EFF > V TH for P FE=+P. Therefore, the process of work-function engineering at the internal metal layer has successfully mitigated the problem of non-distinguishability of states for the case of P HOLD=+P due to the impact of gate leakage. However, it is important to also understand the impact of work-function engineering in the other case, P HOLD = -P, before the implementation of FEFETs in circuits P HOLD=-P Recall, that during this case, the FEFET achieves excellent distinguishability between P FE=+P and -P in the presence of gate leakage. However, with the incorporation of work-function Fig. 5-2 (a) Polarization and (b) internal metal potential versus gate voltage of FEFET with work-function engineering, illustrating the increase in V INT; T FE=3nm

36 26 Fig. 5-3 Internal metal potential versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P with the application of drain voltage illustrating the increase in V INT;T FE=3nm engineering at the internal metal, the device characteristics have to be re-analyzed. As mentioned earlier, the polarization versus V GS characteristics remain unchanged because, V FE remains equal to V GS-V INT. ΔΦ ML only influences in changing the effective gate voltage (V INT-EFF) seen by the transistor. Therefore, with the incorporation of gate work-function engineering, the V INT-EFF curves shift upwards when compared to the case without work-function engineering. Additionally, with the application of V DS it further shifts upward. This causes a concern in the operation of FEFETs with the case P HOLD=-P. The V INT-EFF turns out to be always greater than V TH (Fig. 5-3(b)), resulting in the device remaining in the ON state, i.e., in the LRS for the entire range of V GS. This is illustrated by the current vs voltage characteristics shown in Fig. 5-4(b). Therefore, even though work-function engineering has mitigated the issue faced with the case P HOLD=+P in the presence of gate leakage, it induces loss in distinguishability in the case P HOLD=-P by keeping the device ON for both P FE= +P and -P. However, it is very important to note Fig. 5-4 Drain Current versus gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=- P illustrating the re-establishment of distinguishability for the case P HOLD=+P; T FE=3nm

37 27 that, the loss in distinguishability occurs in its ON state. This leads to a significant difference in the currents for the two cases P FE =+P and -P which can be easily detected by the sense amplifiers. Another distinguishability problem arises for the case when the current I B is sensed as shown in Fig. 5-4 (b). I B corresponds to two cases: P FE=+P (P HOLD=+P) and P FE=-P (for P HOLD=-P). This makes it challenging to distinguish between the actual bit information stored as the polarization of FE. Therefore work function engineering doesn t completely solve the distinguishability issue and it is important to implement novel operation schemes to overcome this problem which is discussed in the next chapter. Note that we use the different currents I A, I A, I B, I B and I C (as shown in Fig. 5-4(b)) for sensing the different states as described in the circuits analysis performed in the next chapter. Before looking into the circuit implementation of FEFETs, let us discuss about another important metric of interest, the hold margins for non-volatility. 5.2 HOLD MARGINS Apart from distinguishability, another metric of interest is the hold voltage margin. Hold voltage margin is defined as the voltage required to disturb the bit information stored in the FEFET, i.e, the critical gate voltage required for polarization switching in the FE layer. Due to the presence of gate leakage, we consider two types of retention scenarios: (i) long term (LT) retention where the device is in the hold state for a long time before its access such that the internal metal layer potential (V INT) discharges to 0V and (ii) short term (ST) retention where the FEFET is in the hold state for a short amount of time before its access such that V INT is also retained (doesn t discharge Fig. 5-5 Hold voltage margins for polarization retention vs thickness of the ferroelectric showing V M;FE-CAP=V M-LT>V M>V M-ST

38 28 to 0V) along with the polarization. Gate leakage plays an important role in improving the hold margins of long term retention (V M-LT). This is because, the critical gate voltage required for polarization switching (+-V C=V FE=V GS-V INT) during the case of access after long time is as high as that of a standalone ferroelectric capacitor (V M; FE-CAP; Fig. 5-5), since V GS=V FE (with V INT=0V). On the other hand, when the FEFET is accessed after short time, the hold margins (V M-ST) degrade, in the presence of gate leakage. This is because of lower critical gate voltages required to disturb (switch) the polarization states stored in the FEFET when compared to the case neglecting gate leakage which is attributed to the shifting of the characteristics as mentioned before (Fig. 5-2, 5-5). 5.3 EFFECT OF T FE AND SUPPLY VOLTAGE V DD Thickness of FE (T FE) It is well known that increasing T FE increases the hysteresis width of the polarization vs gate voltage characteristics in FEFETs [13, 23]. This in turn increases the robustness and the degree of non-volatility as mentioned before. However, it is important to understand the impact of gate leakage with respect to thickness of the ferroelectric. As described above, gate leakage causes the device characteristics to shift towards left or right depending on the value of P HOLD. The device characteristics for thickness ranging between 3nm, 4nm and 5nm is shown in Fig We notice that for T FE=2nm, the device achieves volatile hysteretic behavior. This results in loss in non-volatility and therefore implementation of FEFETs in circuits, such as, non-volatile memory becomes challenging. Therefore, T FE>2nm is required to Fig. 5-6 Polarization vs gate voltage characteristics for (a) P HOLD=+P and (b) P HOLD=-P showing the influence of thickness on the non-volatile hysteresis

39 29 achieve non-volatility for both cases, P HOLD=+P and P. This is a necessary but not a sufficient condition for its implementation of FEFETs in non-volatile memories. Recall the dependency of drain voltage on FEFETs with gate leakage. Application of V DS shifts the device characteristics towards the right due to the interaction between the parasitic capacitances as explained in chapter 3. Therefore, as an additional condition for FEFET s implementation in non-volatile applications, we should ensure that the device exhibits nonvolatility after the application of V DS. Our simulation results reveal that T FE>3nm is required for designing FEFETs, which showcases non-volatility for both P HOLD=+P and P with the application of V DS=0.3V Supply Voltage (V DD) Supply voltage V DD, also plays an important role in determining the functionality of circuits based on FEFETs. It is necessary that the magnitude of V DD must be higher than the critical voltage required for polarization switching from P +P during the case P HOLD=-P (see Fig. 5-2). Table 5-1 shows the design space for memory implementation with FEFETs, with respect to T FE and V DD. For T FE<3nm, we notice that the FEFET loses its non-volatile functionality due to the shifting of the device characteristics. To avoid repetition let us consider the case with T FE=6nm to understand the design space. We notice that the hysteresis width at T FE=6nm constraints the selection of supply voltage V DD, because for V DD<1.0V, the FEFET losses its functionality. This is attributed to the fact that the critical gate voltage required to switch the polarization in >1.0V for the case with T FE=6nm. FEFET with T FE>7nm do not showcase the desired functionality for V DD<1.2V because of their large hysteresis. Table. 5-1 The design space analysis of the FEFET in the presence of gate leakage with respect to two parameters: Thickness of the ferroelectric (T FE) and Supply voltage (V DD)

40 30 As discussed in this section, work-function engineering mitigates but does not entirely solve the distinguishability issue. This is because, if FEFET is read after a long time, the drain current is same for P HOLD =+P or P since V INT=0 (V INT-EFF=0.14V) as shown in Fig.5-4 (b). Moreover, for the case with P HOLD= -P, the device is ON for both P FE=+P and P. We address this problem with innovations at the circuit level via a new read scheme. In the next chapter, we discuss the different flavors of memory designs and the impact of gate leakage during their operations. We also showcase the modifications required at circuit level for the memory operations.

41 Chapter 6 NON-VOLATILE MEMORY Conventional silicon based static random-access memory (SRAM) has been used for onchip applications for the past few decades [33]. However, they face growing challenges with scaling such as short channel effects, higher leakage and lower integration densities [1, 4, 7, 41]. Also, the memory wall problem discussed earlier imposes several hurdles in their direct implementation with scaling technologies. Over the last decade there has been immense interest in quest for emerging memory technologies which possess huge advantages over the traditional silicon-based memories [1, 4,7]. The unique opportunities ushered by non-volatile emerging technologies has triggered an immense interest in enhancing the computation capability of systems with the possibility of on-chip data storage [1, 4, 7]. This has led to the opening of new avenues for architectural/system designs with low power operation and significant improvements in the forward progress of computation [13, 33]. Emerging non-volatile memory devices, showcase zero stand by leakage and high integration densities [1]. However, their direct deployment is not straight forward due to presence of several design conflicts, issues associated with reliability, robustness and high write power [1, 4, 7, 13, 23]. Several attempts have been made to use the emerging technologies for memory application. Spin-based memories based on magnetic tunnel junctions (MTJs) [42] look promising in most aspects such as endurance, non-volatility and high integration densities but the poor distinguishability between their bi-stable states yields very low read sense margins [43]. They also face unavoidable failures due to inherent statistical switching of MTJs, influence of thermal noise in the switching behavior and read disturb failures due to accidently switching of MTJs during the read operation [44]. At the circuit level MTJs face several issues, major one being source degeneration of the access transistors [45]. SHE-MTJ devices have been proposed as a solution for the challenges faced in conventional MTJs. They overcome the read-write conflict by having separate terminals for both the operations [33]. They also possess lower write current requirement leading to lower write energies. However, large area overheads and reliability of spin currents with scalability is a concern [46]. Phase change memory (PCM) is an emerging memory which have

42 32 been explored recently [1, 4, 7]. While researches have projected that PCM scaling mechanism is more robust than DRAMs thereby providing a clear road map for increasing main memory density and capacity [47], they possess critical drawbacks which preclude them from direct implementation on a large scale. PCM consumes high write energy and has a large write time which leads to low write bandwidth [1,7]. Moreover, multi-level PCM implementations results in orders of magnitude increase in write energy and latency [48, 49]. Resistive RAMs have higher density, lower write energy and improved distinguishability compared to PCMs [1,4]. But poor endurance and sneak currents following through the cells in the crossbar architecture leads to number of challenges which have to be addressed [50]. Ferroelectric capacitor memories (FERAMs) offer high endurance with polarization retention and high densities close to DRAMs [10, 13]. Texas Instrument s FRAM microcontrollers [11] and Cypress s ExcelonTM FRAM [12] are the best examples of industry efforts to leverage the ferroelectric properties for memory applications. However, they also face major drawbacks like DRAMs, with respect to read disturb failures, requiring periodic refresh operations [13]. Moreover, they require application of large operating voltages leading to high energy requirements [13], resulting in various issues during its integration with scaled CMOS circuits. FEFET based memory designs offers a unique feature of direct integration with the CMOS process flow. The ON or the OFF state of FEFET is retained in the absence of an electric field (as discussed before). Moreover, non-volatile FEFETs exhibit advantages over other memory technologies, such as (i) better distinguishability between their bi-stable states (~10 6 ) [13] compared to spin-based memories (ii) higher endurance (~10 7 cycles) and lower write energies [51] compared to resistive RAMs and phase change memories (PCMs) respectively. These intriguing features make them outstanding candidates for non-volatile memory applications. 6.1 FEFET BASED MEMORY DESIGNS The hysteretic characteristics of FE capacitor leads to its direct application in non-volatile memory designs [10]. FERAM employs a 1T-1C architecture where the read and write operations are performed using the same path through the bit lines (Fig. 6-1(a)) [10]. Though they offer very high integration densities, read-write conflict possesses a severe challenge [13]. Moreover, since the read operation occurs by sensing the polarization of FE, FERAMs might showcase very low

43 33 distinguishability between their bi-stable states [13]. FEFET based memory designs have been explored to mitigate the drawbacks faced in FERAMs. The read-write paths are decoupled leading to read operation being robust and disturb free [13]. Also, the currents sensed through the drain terminal of FEFET has orders of magnitude of distinguishability between their bi-stable states. FEFET based memories have also showcased significant improvements in the forward progress of computation when implemented in a non-volatile processor [13]. Several FEFET based nonvolatile memories have been proposed recently. In this work we focus on three types of FEFET memories as discussed next T Memory The schematic and layout of the 2T memory design are shown in Fig. 6-1(b). The gate of the FEFET is connected to a write access transistor. 2.5X area penalty is incurred compared to IT-IC cell [13, 23]. The drain terminal of the write access transistor is driven by the write bit line (WBL) while the gate is controlled by the write word line (WWL). The drain of the FEFET is driven by the read bit line and the source is connected to the virtual ground (V.GND) [13]. The memory array is formed by connecting WWL of the cells in a row and WBL, RBL and GND of the cells in a column. Let us discuss the memory operation next. To write into the bit-cell, WWL is asserted with RBL driven to 0. Then WBL = -V DD or V DD is applied to order to write 0 (LRS) or 1 (HRS) into the bit cell, corresponding to P or +P respectively. For reading the value of the bit-cell, RBL is asserted to a voltage V READ with WWL asserted and WBL driven to 0. The current through the bit-cell is sensed and information stored is read-out T Memory The main drawback of the 2T memory design is infeasibility of a selective read operation which leads to large leakage energy during the read operation [23]. To overcome this issue, an addition access transistor can be included making it a 3T memory cell. The schematic and layout of the 3T memory design are shown in Fig.6-1(c). The gate and drain terminals of the FEFET is connected

44 34 to a write access transistor and read access transistor respectively. Compared to an FERAM, the FEFET-based 3T memory leads to 3.5X area penalty. The drain terminal of the write access transistor is driven by the write bit line (WBL) while the gate is controlled by the write word line (WWL). The drain of the read access transistor is driven by the read bit line (RBL), while the gate is driven by the read word line. The source terminal of the FEFET is grounded. The memory array is formed by connecting WWL and RWL of the cells in a row and WBL, RBL and GND of the cells in a column. The write operation for 3T memory is similar to that of 2T. WWL and RWL are asserted with RBL driven to 0. V DD or +V DD is applied at WBL in order to write 0 (-P/LRS) or 1 (+P/HRS) into the bit-cell. For the read operation, WBL and WWL are driven to 0. RWL is asserted along with V READ applied at RBL. The read access transistor helps in selectively accessing the bitcell unlike 2T memory, thereby achieving lower leakage energy. The current through the FEFET is sensed and the polarization stored in the FEFET is determined. Fig. 6-1 Schematic of (a) 1T-1C FERAM (b) 2T (c) 3T and (d) 4T FEFET based memory designs

45 T Memory Both the 2T and 3T operate with the usage of negative voltages. This can be avoided by having a control over the source terminal of the FEFET. Inclusion of an additional source access transistor can help in achieving operation of the memory with only positive voltages. The schematic and layout of the 4T memory design are shown in Fig. 6-1(d) [24]. Compared to the 1T-1C cell, the 4T FEFET memory has 4X area penalty. The gate, drain and source terminals of the FEFET is connected to a write access transistor, read access transistor and a source access transistor respectively. The drain terminal of the write access transistor is driven by the write bit line (WBL) while the gate is controlled by the write word line (WWL). The drain of the read access transistor is driven by the read bit line (RBL), while the gate is driven by the read word line (RWL). The gate of the source access transistor is driven by the source word line (SWL) while the drain terminal is driven by the source bit line (SBL). The memory array is formed by connecting WWL, RWL and SWL of the cells in a row and WBL, RBL and SBL of the cells in a column. As describes above, with the help of the additional access transistor at the source of the FEFET, the 4T memory achieves memory operation with positive voltages. For writing 0 (LRS) into the bit-cell, WWL, SWL and RWL are asserted. WBL and RBL are driven to 0, while SBL is driven to V DD in order to attain V GS=-V DD in the FEFET. This ensure P stored in the FE layer corresponding to state 0. For writing 1 (LRS), WWL, RWL and SWL are asserted. RBL and SBL are driven to 0 while WBL is driven to V DD in order to achieve V GS=+V DD for the FEFET. This results in +P stored in the FE corresponding to the state 1. For reading the bit information, WWL, SWL and RWL are asserted with WBL and SBL driven to 0V. VREAD is applied at RBL and the current through the FEFET is sensed to determine the state stored. All these memory designs have their own advantages and trade-offs. One of the main advantages of FEFET based memories over the FERAMs is the low voltage operation leading to lower power consumption. Recall form chapter 4 (Fig. 4-1), that the hysteresis width of FE capacitor is larger than that of an FEFET which leads to requirement of larger critical voltages for switching of polarization in FERAMs. Another important feature of FEFET based memories is the ease of read operation through the decoupled read and write operation unlike FERAMs.

46 36 As mentioned earlier, FEFETs can be realized with or without an intermediate metal layer. Both the device structures have their own advantages and trade-offs as discussed in chapter 1. In this study we primarily focus on FEFETs with internal metal layer. In chapter 3 we discussed the implications of gate leakage in FEFETs (due to internal metal) and the loss in distinguishability of the bi-stable states. Chapter 4 described a device-level solution to over this problem with gate workfunction engineering at the internal metal to overcome this problem. We noticed that even though re-establishment of distinguishability for the case P HOLD=+P was achieved, the device remained in the ON state for the entire range of V GS, for P HOLD=-P. Moreover, if FEFET is read after a long time, the drain current is same for P HOLD =+P or P since V INT=0 (V INT-EFF=0.14V) as shown in Fig This hinders the implementation of FEFETs (with gate leakage) in the memory designs (2T, 3T and 4T) mentioned above. Fig. 6-2 Layouts of (a) 1T-1C FERAM, (b) 2T, (c) 3T and (c) 4T FEFET based memory designs.

47 37 Table. 6-1 Operating bias conditions for the 3T FEFET based memory design in the presence of gate leakage. In the following sub-sections, we showcase important circuit level innovations to address the problems due to gate leakage for the implementation of FEFET based non-volatile memories. To avoid repetition, we showcase the modified memory operation for the 3T memory cell (bias conditions in Table. 6-1). However, similar operating conditions can be followed for the 2T and 4T memory designs. 6.2 MODIFIED MEMORY OPERATION Write The write operation for 3T FEFET based memory in the presence of gate leakage has no significant impact when compared to the case neglecting gate leakage. The WWL and RWL are enabled and RBL is driven to 0. WBL is driven to +V DD/-V DD in order to write 1 / 0, which corresponds to P FE=+P/-P. Note the only condition while selecting the supply voltage V DD is that, it should be higher than the coercive voltage of the standalone ferroelectric capacitor. This is because, for polarization switching after long term retention, the hold voltage margins for a state is equal to the coercive voltage for both P HOLD=+P (-V C-FE) and P HOLD=-P (+V C-FE). Note, as mentioned before, the state of the FEFET is stored as the polarization of the ferroelectric layer and not as the resistance state of the FEFET during hold, in the presence of gate leakage. For FEFETs neglecting gate leakage, similar write opertion is followed however, citical voltages for polarization switching decreases due to no shifting of device characteristics as mentioned before. This corresponds to the possibility of lower write voltages leading to lower write

48 time and decrease in write energy compared to FEFET with gate leakage. These aspects are discussed further in the subsequent sections Read As discussed in the previous chapter, gate leakage in FEFETs leads to loss in the distinguishability of the polarization states of the ferroelectric. Work-function engineering can reestablish the distinguishability between the bi-stable states P FE=+P and -P for the case P HOLD=+P. However, if FEFET is read after a long time, the drain current is same for P HOLD =+P or P since V INT=0 (V INT-EFF=0.14V) as shown in Fig. 5-3 which obstructs their direct implementation in memories. Therefore, to distinguish between the bi-stable states (P FE=+P and P), we require a modified read operation which is proposed next. The proposed read operation consists of two steps. Step-1 is the assertion of RWL to V DD in order to enable the read access transistor. Along with this RBL is driven to a read voltage, V READ. The drain current versus gate voltage characteristics of the FEFET (in linear scale) is shown in Fig Now, if the current sensed (I SL) is low, i.e I SL=I C, this corresponds to the case P FE=-P (with P HOLD=+P). Therefore, a low current sensed directly implies that the polarization state of the FEFET, P FE=-P ( 0 ). Now, consider that the current sensed is high, i.e., I SL=I A or I B. This can corresponds to 3 possibilities: (i) P FE=+P (with P HOLD=+P; I SL=I B) (ii) P FE=+P (with P HOLD=-P; I SL=I A) and (iii) P FE=-P (with P HOLD=-P; I SL=I B). To distinguish these cases, we require the second step of read operation as illustrated in Table 6-2. In step-2, WBL and WWL are asserted to V DD to force the polarization of the ferroelectric to be positive (+P). For the case when P FE is already = +P Fig. 6-3 (a) Drain current vs gate voltage characteristics with gate work-fucntion engineering at the internal metal layer showing the different sensed currents in linear scale. (b) proposed 2-step read scheme

49 39 Table. 6-2 Value of polarization corresponding to the sensed currents in the 2-step read operation ( 1 ), marginal increase in I SL (ΔIs L: I A -I A or I B -I B) is sensed due to no polarization switching in the ferroelectric. And for the case with initial P FE=-P ( 0 ), polarization switching of the ferroelectric from an initial negative value to a positive value (-P +P) leads to a significant change in I SL (ΔI H: I A -I B). Therefore, ΔI L or ΔI H can be sensed to determine the value of the P FE ( 0 / 1 ). Table. 6-3 illustrates the step-2 of read operation. It is important to note that for the case P FE=-P (with P HOLD=-P), the read operation is destructive as we force the polarization of the ferroelectric to a positive value in step-2. Therefore, a write back operation is required to restore the initial information (stored in terms of the polarization of the ferroelectric) of the bit cell. This is done by asserting WWL and driving WBL to -V DD. For FEFETs memory design neglecting gate leakage, 1-step read operation is sufficient as explained before. This is because, in such memories, the internal metal potential does not discharge thereby retaining the resistance state of the FEFET corresponding to the polarization stored in the Table. 6-3 Value of sensed currents at each step of the read operation corresponding to polarization (P FE) stored in the ferroelectric

50 40 Fig. 6-4 Transient waveforms of the 3T memory ferroelectric layer. This resistance state is read to sense the bit information. RBL is applied along with the assertion of RWL. Depending on the resistance, high current (I LRS) or low current (I HRS) can be sensed by a sense amplifier which determines the value stored in the bit cell. Therefore, FEFETs considering gate leakage might go through performance degradation with high read power overheads. These aspects are discussed further later. It may be important to mention that the 1T-1C FERAM (or FRAM) architecture also showcases a destructive read operation like FEFETs in the presence of gate leakage. However, their read operation can be only be achieved by employing voltage based sensing whose speed is limited by the bit line/ plate line capacitance and the low capacitance distinguishability between their bi-stable states [13]. Moreover, the change in V INT (ΔV INT) achieved in FEFETs is much larger than FE capacitors due to the lower CMOS capacitance.

51 Hold The hold operation is performed by all the signals being driven to 0V. For the case with gate leakage, the retention of polarization in the absence of electric field results in storing the state of the bit cell as P FE and V INT=0V after a long time as discussed before. For the case neglecting gate leakage, the polarization and the corresponding V INT, both are retained, which holds/stores the information of the bit cell. Therefore, when there is a power outage (all signals =0V), the FEFETs automatically store the information as the polarization of the ferroelectric layer due to their nonvolatile nature. The transient waveforms of the memory operation are shown in Fig 6-4. We showcase the waveforms for both short term and long-term retentions. Next, we look into the performance analysis and the cost of the modified read operation compared the case when gate leakage is not considered for different FEFET based memory designs. 6.3 PERFORMANCE ANALYSIS Gate leakage in FEFET based memories can severely affect the performance of the memory operation which needs to be investigated. The presence of the intermediate metal layer leads to loss in the distinguishability of the bi-stable states due to gate leakage as discussed before. However, the polarization of the ferroelectric layer is still retained in the presence of gate leakage, which can potentially be used for reading the bit information. Device and circuit level innovations with workfunction engineering of the internal metal layer along with a modified read operation in FEFET based memory designs was proposed in chapter 4 and 5 to overcome the problems associated with gate leakage in non-volatile memory implementation. In this section we perform an extensive analysis by comparing the read-write performance of FEFET based memory designs (2T, 3T and 4T) with and neglecting gate leakage. We also showcase the impact of material-device-circuit parameters on the read-write metrics of the memory designs. In our analysis we consider a 256 X 256 memory array with 64-bit words.

52 42 Fig. 6-5 Impact of GL on Write Time of 2T, 3T and 4T FEFET based memory designs; T FE=3nm; V DD=1V Write Time As mentioned before, polarization switching from +P -P corresponds to writing 1 0 and polarization switching from -P +P corresponds to writing 0 1. Write time of the memory is defined as the duration of polarization switching (10% to 90%) in between the two bi-stable states. In our analysis we have considered the maximum of +P -P and -P +P switching as the write time for memories. The 2T, 3T and 4T FEFET based memories with gate leakage tend to showcase higher write latency during the write operation compared to their counterparts, i.e., FEFET memories neglecting gate leakage. This is because of the shifting of device characteristics as explained in chapter 3, resulting in larger magnitude of critical voltages required for polarization switching (for both +P -P and P +P). Fig. 6-5 shows write time comparison for 2T, 3T and 4T FEFET based memories with and neglecting gate leakage. As observed from the figure, for the memories considering gate leakage, 33% increase in write time is observed compared to their corresponding memory designs neglecting gate leakage. Also, notice that write time is similar for the 2T, 3T and 4T memory designs with (~200ps) and neglecting gate leakage (~150ps). This is because, for all the memory designs the process of writing into the bit cell is the same i.e, turning ON of the write access transistor along with application of write bit line voltage, to drive the gate of FEFET for polarization switching.

53 43 Fig. 6-6 Impact of GL on Write Energy of 2T, 3T and 4T FEFET based memory designs at iso-write time of 200ps; T FE=3nm; V DD=1V Write Energy Write energy is the total average energy consumed by the memory associated with writing either 1 or 0 into the bit cell. In our analysis, we consider average write energy corresponding to an entire word with 64 bits, in which 32 undergo write 1 operation and the other 32 undergo write 0 operation. We consider an iso-write time of 200ps, achieved by decreasing the supply voltage of memories neglecting gate leakage for write energy comparison. We notice ~43% increase in write energy across the 2T, 3T and 4T FEFET based memory designs with gate leakage (Fig. 6-6). This is attributed to the large critical gate voltage (equal to the coercive voltage of a standalone ferroelectric capacitor) required for polarization switching during the write operation unlike the case with FEFET memory designs neglecting gate leakage whose critical voltage for polarization switching is less than the coercive voltage of a standalone ferroelectric capacitor as discussed in chapter 3. Write time and energy depends on various material, device and circuit parameters such as kinetic coefficient (rho) of the ferroelectric material, thickness of the ferroelectric layer (T FE) and supply voltage (V DD). We discuss the influence of these parameters on the write operation metrics, later on.

54 44 Fig. 6-7 Impact of gate leakage on Read Power of 2T, 3T and 4T FEFET memories. Normalized with respect to memories neglecting gate leakage. T FE=4nm; V DD=1V Read Power As discussed before, non-volatile FEFETs with gate leakage lose distinguishability between their bi-stable states causing loss in the robustness of their operation. We proposed device level innovation and circuit level modifications, harnessing the unique property of polarization retention in the ferroelectric material, in the absence of an external electric field to re-establish functionality which was lost due to gate leakage (discussed in chapter 4 and 5). It is important to understand the drawbacks of such modification during the memory operation. We perform a current based read sensing in our analysis. Fig. 6-7 showcases the normalized read power for the memories considering the 2-step read operation, with respect to memories neglecting gate leakage (1-step operation). As observed in the figure, the read power increases by 4X-6X for the different memory designs when T FE is varied from 4nm to 6nm. This is mainly attributed to the 2-step read operation required to mitigate the issues with loss in distinguishability of the states of FEFETs with gate leakage. Also, the 2T design showcases a higher read power overhead compared to 3T and 4T designs. This is because of the absence of the read access transistor resulting in the entire RBL voltage driving the drain of FEFET unlike the 3T and 4T designs which undergo a threshold drop across the access transistor resulting in lower sensed currents. It is important to mention that the maximum contribution for the read power comes from the sensing of the high currents I A and I A. In the later sections, we propose techniques to decrease the magnitude of these currents, in order to mitigate the high read power overheads. The read power overheads mentioned above for FEFET based memories with gate leakage, can be reduced by performing a device-circuit co-design of the memory parameters such as read

55 45 voltage (V READ), Thickness of FE (T FE), work-function engineering (ΔΦ ML), etc. In the following section, we showcase the possibilities of reducing overheads on the performance metrics (write and read) by considering the aforementioned device-circuit parameters. 6.4 INFLUENCE OF DEVICE-CIRCUIT PARAMETERS Thickness of Ferroelectric (T FE) T FE plays an important role in determining the device characteristics. Increasing T FE corresponds to larger hysteresis width in the polarization vs gate voltage characteristics (nonvolatile) [13]. Large hysterysis window corresponds to stronger polarization retention ability in the ferroelectric material resulting in increase in the robustness of the non-volatility. As a result, the switching of polarization becomes harder and takes a longer time. Fig. 6-8(a) shows the influence of T FE on the write time of different FEFET based memroy designs with gate leakage. As T FE increases the critical gate voltage required for polarization switching increases (due to larger hysterysis) which leads to increase in write time. Write energy across different T FE remains almost similar (slight increase with T FE) for the respective memory designs as shown in Fig. 6-8(b). This is because of the negligible change in the gate capacitance of the FEFET for small range of T FE variation [36]. Fig. 6-9 showcases the T FE dependence on the normalized read power for 2T, 3T and 4T FEFET based memories with gate leakage, with respect to their corresponding memory designs Fig. 6-8 Write time and write energy comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different thickness of the ferroelectric T FE; V DD=1V

56 46 Fig. 6-9 Normalized read power comparison for 2T, 3T and 4T FEFET based memories considering gate leakage for different thickness of the ferroelectric material; V DD=1V neglecting gate leakage. We observe that with decreasing T FE, the read power decreases. This is because, with increase in T FE, the resistance ratio increases. This leads to higher read power for larger T FE due to higher I LRS sensed Supply Voltage (V DD) It is well known that increasing supply voltage helps in running the circuit faster, i.e., the write time of the memory operation decreases [52]. But this comes with a penalty of increased energy consumption. Fig shows the write time and write energy dependence on the supply voltage V DD of 0.8, 0.9 and 1.0V for the 2T, 3T and 4T FEFET based memory designs with gate leakage. Since the read power doesn t rely on the choice of supply voltage, we perform this analysis only for the write operation metrics. It is important to note that, supply voltage plays a crucial role in determining the feasibility of the memory operation as explained in chapter 4. Fig Write time and write energy comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different supply voltage V DD; T FE=3nm

57 47 Fig Write time and write energy comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different Kinect coefficient of the ferroelectric material; T FE=3nm; V DD=1V Kinetic Coefficient (ρ) Kinetic coefficient of the ferroelectric material directly corresponds to its polarization switching time [36]. Therefore, it is very important material parameter which determines the write time in FEFET based memory implementation. As shown in Fig. 6-11(a), when ρ is varied from between from 0.05 to 0.5 ohm-cm, the write time increase. However, since the gate capacitance of the FEFET remains unchanged due to the variation in ρ, the write energy remains the same across various ρ values for respective memory designs as shown in Fig. 6-11(b). Recent experiments have shown promising trends in achieving ferroelectrics with lower kinetic coefficients [38] which can potentially reduce the write time in FEFET based memories. It is noteworthy that, in all the above analysis, write energy of 3T is greater than 2T memory design. This is because of the additional switching capacitance of the read access transistor during the write operation of 3T. The energy is lowest for 4T design because of the use of only positive voltages during the write operation unlike 2T and 3T which requires a negative voltage for writing 0 into the cell.

58 48 Fig Read power comparison for 2T, 3T and 4T FEFET based memory designs considering gate leakage for different read voltages V READ; T FE=3nm; V DD=1V Read Voltage (V READ) Read voltage directly corresponds to the magnitude of current sensed during the read operation. Lowering the read voltage can help in realizing low read power at the cost of distinguishability. Since FEFETs have high distinguishability we perform our simulations by ensuring at least 3 orders of magnitude (>10 3 ) margin for I LRS and I HRS in our simulations (with I LRS>1uA and I HRS<1nA). However, this is not a strictly enforced limit. We can further reduce the read voltage and achieve lower sensed currents i.e, I LRS<1uA (which corresponds to lower read power). However, this would require design innovations of sense amplifiers with improved sensitivities, which is outside the scope of this work. Fig shows the decrease in read power across different FEFET based memory designs with decrease in read voltage. Note that, the maximum contribution of the (high) read power due to the modified read operation, comes from sensing of the currents I A and I A as shown in Fig Lowering V READ will decrease the sensed I A and I A significantly, thereby reducing the read power of FEFET memories with gate leakage compared to the memories neglecting gate leakage Work-function Engineering (ΔΦ ML) Gate work-function engineering alleviates the problem of loss in distinguishability due to gate leakage in FEFETs with intermediate metal layer. As discussed in chapter 4, work-function

59 49 Fig Read power comparison for 2T, 3T and 4T FEFET based memories considering gate leakage for different work-function engineering; T FE=3nm; V DD=1V engineering increases the effective potential (V INT-EFF) realized at the gate of the underlying transistor, which in turn increases the I LRS, such that the two bi-stable states P FE =+P and -P for the case P HOLD=+P, can be distinguished. ΔΦ ML can determine how strong or weak the channel of the underlying transistor is inverted. Lower ΔΦ ML leads to weaker inversion. This corresponds to lower current drives for a particular V READ, in turn leading to lower read power metrics at the cost of distinguishability (however, in our simulations we ensure it to be >10 3 ), compared to the FEFET memories neglecting gate leakage. Fig shows the influence of ΔΦ ML on the read power for the different memory designs. Therefore, by co-designing read voltage (V READ) and ΔΦ ML and ensuring the required distinguishability (I LRS/I HRS>10 3 ), we can potentially mitigate the high read power overheads of the FEFET based memories with gate leakage. Improved design of sense amplifiers can also help in realizing FEFET based memories with the intermediate metal layer and overcome the drawbacks it possess due to gate leakage through the ferroelectric and dielectric layers.