Steep Slope Transistors beyond the Tunnel FET concept. David Esseni, University of Udine
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1 Steep Slope Transistors beyond the Tunnel FET concept David Esseni, University of Udine
2 Overcome Boltzmann s Tyranny Sub-threshold swing may be expressed as V g = φ s V S/D G In MOSFETs: - second term is limited at 60mV/dec by the thermionic emission; - m corresponds to a paraelectric-capacitance voltage divider m V B In TFETs: - BTB Tunneling, NO therm. emission Source BTBT Drain second term can be < 60mV/dec - m corresponds to a paraelectric-capacitance voltage divider m In NC-FETs: - second term is limited at 60mV/dec by the thermionic emission; - exploiting negative capacitances (e.g. FeFET) m Settembre, 2017 David Esseni, Giornata IUNET, Perugia 2
3 Outline Energy filtering at source Super-lattice, steep slope FET (no exper. proof) Device concepts not relying on energy filtering Negative-capacitance transistors (NC-FETs) based on ferroelectric dielectrics Piezoelectric FETs (no exper. proof) Phase change based FETs (Mott transistors) 3
4 Outline Energy filtering at source Super-lattice based, steep slope FET Device concepts not relying on energy filtering Negative-capacitance transistors (NC-FETs) based on ferroelectric dielectrics Piezoelectric FETs Phase change based FETs (Mott transistors) 4
![1E-01 Drain current [A/m] 1E-03 1E-05 1E-07 1E-09 1E-11 1E-13 GaN/Al_(0.15)Ga_(0.](/docs-images/84/89550056/images/5-3.jpg "85)N GaN/Al_(0.25)Ga_(0.")
5 Superlattice based steep slope FET (P. Maiorano et al., Solid State Electr., Volume 101, November 2014) To achieve steep slope filtering of high-energy electrons 1E-01 Drain current [A/m] 1E-03 1E-05 1E-07 1E-09 1E-11 1E-13 GaN/Al_(0.15)Ga_(0.85)N GaN/Al_(0.25)Ga_(0.75)N InGaAs/InAlAs InGaAs/InP 1E-15-0,3-0,2-0,1Gate 0 voltage 0,1 0,2[V] 0,3 0,4
6 Outline Energy filtering at source Super-lattice, small slope FET Device concepts not relying on energy filtering Negative-capacitance transistors (NC-FETs) based on ferroelectric dielectrics Piezoelectric FETs Phase change based FETs (Mott transistors) 6
7 NC-FET concept [S. Salahuddin et al., Nano Letters, 2008] The Negative Capacitance concept can in principle reduce S below 60mV/dec V g C ins C MOS D C D C DPL C S S in conventional MOS with ins > 0 Ferroelectric materials (BaTiO 3, Si:HfO 2, Hafnium Zirconium Oxide - HZO) show a negative capacitance C FE branch, such that charge increases for decreasing voltage: CFE CFE MOS C ins = C FE = - C FE 7
8 NC-FET: where does the negative C FE stem from? Ferroelectrics are usually described by the Landau-Khalatnikov Equation (LKE): Energy U fe Q U fe U fe V 0 = 0V < V 1 < V 2 Polarization [µc/cm 2 ] LKE is an Energy-Minimization Approach Experiment LK TD LK S.S. C Si: HfO E fe [MV/cm] 1) Ferroelectric alone is unstable in small E FE region and it has hysteric behavior 2) Ferroelectric with positive capacitance in series should can be stabilized in small E FE region (around E FE =0) and exhibit a negative capacitance behavior C FE < 0 [S. Salahuddin et al., Nano Letters, 2008] 8
9 Negatve capacitance FETs: voltage gain > 1 t z Gate Ferroelectric Silicon fe fe fe Q P + E fe <0-9
10 Negatve capacitance FETs Is there experimental evidence of sub-threshold swing below 60mV/dec in NC-FETs? [P.Sharma et al., VLSI Symp. 2017] 10
11 After P.Sharma et al., VLSI Symp Gate last process with Hf 0.5 Zr 0.5 O 2 (HZO) as ferroelectric (FE) dielectric in a metal/ferroelectric/insulator/semiconductor (MFIS) configuration Long channel FETs (around 2m) Asymmetric and hysteretic I DS -V GS characteristics Measurements at low frequency and still too large voltages 11
12 Negatve capacitance FETs IUNET: Possible synergy between ab initio analysis of ferromaterials, device-level modelling, circuit exploitation. Contacts (Udine-Pisa) for the H2020 Call back in April 2017 Europe: NamLab (T. Mikolajick), AMO/Aachen (Waser, Lemme), Jülich (Qing-Tai Zhao) Germany A.Ionescu at EPFL U.S.A: Berkeley: S.Salahuddin, C.Hu et al. LEAST Center in Notre Dame: S.Datta et al. 12
13 Outline Energy filtering at source Super-lattice, small slope FET Device concepts not relying on energy filtering Negative-capacitance transistors (NC-FETs) based on ferroelectric dielectrics Piezoelectric FETs Phase change based FETs (Mott transistors) 13
14 Piezoelectric FETs Basic idea (T. van Hemert, and R. J. E. Hueting, IEEE Trans. on Electr. Dev., pp. 3265, 2013) The converse piezoelectric effect in the piezo-layer is used to enforce a gate controlled strain in the channel material. If the strain is such that the V T is increased when V G is reduced (n-type FET) and viceversa, a sub-v T swing smaller than 60mV/dec can achieved In the turn-on characteristic the transistor effectively switches from an unstrained to a strained I DS -V GS curve Settembre, 2017 David Esseni, Giornata IUNET, Perugia 14
15 Piezoelectric FETs: possible device architecture The gate controlled strain in the semiconductor implies a gate controlled electron affinity that results in the simplified SS expression SS 1 log I ln10 10 V G D K q B T 1 ( Φ qv SCT G M ) 1 15
16 Piezoelectric FETs Simulations suggest that one can in principle obtain SS values below 60mV/dec but it is necessary to have 1. Large piezoelectric coefficients (d z3 ) preserved at small piezo thickness 2. Device architectures able to trasfer strain from the piezo to the semiconductor 3. Semiconductor sensitive to strain: large deformation potentials and optimal crystal orientation Is there experimental evidence of sub-threshold swing below 60mV/dec in Piezo-FETs? not to my knowledge 16
17 Piezoelectric FETs IUNET: Possible synergy between ab initio analysis of piezomaterials, device-level modelling, circuit exploitation. Europe: R.Hueting at Twente University: contacts with Global Foundries in U.S.A. 17
18 Outline Energy filtering at source Super-lattice, small slope FET Device concepts not relying on energy filtering Negative-capacitance transistors (NC-FETs) based on ferroelectric dielectrics Piezoelectric FETs Phase change based FETs (Mott transistors) 18
19 Phase transition based FETs (1) Strongly correlated functional oxides exhibit a metalinsulator transition. Vanadium dioxide (VO 2 ), in particular, exhibits high contrast in conductivity between the two states and the possibility to induce the phase change by electrical excitations VO 2 -based 2-terminal switches fully investigated [1,2,3] VO 2 -based 3-terminal devices was attempted in which VO 2 is used as the semiconductor material, but with small transconductance an I ON /I OFF ratio [4,5]. [1] J. Leroy et al., APL, vol. 100, no. 21, p , [2] W. A. Vitale et al., in DRC 2014, pp [3] W. A. Vitale et al., in IEEE EDL, vol. 36, no. 9, pp , Sep [4] D. Ruzmetov et al., J. Appl. Phys., vol. 107, no.11, p , 2010 [5] N. Shukla et al., Nature Commun., vol. 6, p. 7812,
20 Phase transition based FETs (2): «Hybrid Phase-Change Tunnel FET (PC-TFET) Switch...» A:Casu et al, IEDM 2016 Vanadium dioxide (VO 2 ) is used in series with a FET or a Tunnel FET and results in step-like transitions Device concept tightly related to non-volatile type of switching: applications for digital or analog circuits are unclear 20
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