Ferroelectric Field-Effect Transistors Based on MoS 2 and

Transcription

1 Supplementary Information for: Ferroelectric Field-Effect Transistors Based on MoS 2 and CuInP 2 S 6 Two-Dimensional Van der Waals Heterostructure Mengwei Si, Pai-Ying Liao, Gang Qiu, Yuqin Duan, and Peide D. Ye These authors contributed equally to this work. School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907, United States * Address correspondence to: yep@purdue.edu (P.D.Y.) 1

2 1. Synthesis of Bulk CuInP 2 S 6 Figure S1. (a) Powders of Cu, In, P, and S. (b) The mixture of the four elements in stoichiometry ratio. (c) Bulk CIPS crystals synthesized under vacuum at 600 o C after two weeks. Fig. S1 shows the growth of the CIPS crystals by solid phase reaction 1. Fig. S1(a) shows the powders of Cu (246 mg, 3.87 mmol, Sigma-Aldrich, %), In (441 mg, 3.84 mmol, Sigma-Aldrich %), P (244 mg, 7.88 mmol, Sigma-Aldrich, %), and S (752 mg, mmol, Sigma-Aldrich, 99.5%). Powders of the four elements were mixed and placed in an ampoule with the same ratio of the stoichiometry, as shown in Fig. S1(b). The ampoule was sealed as vacuum with high-temperature torch. After being evacuated, the ampoule was heated in a furnace at 600 o C for 2 weeks to obtain the CIPS crystals, as shown in Fig. S1(c). 2

3 2. Crystal structure of CuInP 2 S 6 Figure S2. Crystal structure of CIPS from (a) top-view and (b) side-view. Fig. S2 shows the crystal structure of CIPS from (a) top-view and (b) side-view. It is based on an ABC sulfur stacking and separated by a van der Waals gap as a 2D ferroelectric insulator. 1 3

4 3. Gate Leakage in MoS 2 and CuInP 2 S 6 2D vdw Heterostructure FeFETs Figure S3. Gate leakage current of the same MoS 2 /CIPS 2D heterostructure Fe-FET in Fig. 4(a) in the main text. Fig. S3 shows the gate leakage current of the same MoS 2 /CIPS 2D heterostructure FeFET in Fig. 4(a) in the main text. The gate leakage current was simultaneously measured with the I D - V GS measurement. The gate leakage current is smaller than the minimum drain current in transfer characteristics, indicating the gate leakage current through CIPS thin film does not affect the transfer characteristics. 4

5 4. Temperature dependence of polarization-voltage characteristics of CIPS Figure S4. Temperature dependence of polarization-voltage characteristics measured on a ferroelectric CIPS MIM capacitor (Ni/0.6 µm CIPS/Ni). Fig. S4 shows the polarization-voltage characteristics measured at different temperatures from 290 K to 330 K on the ferroelectric CIPS MIM capacitor (Ni/0.6 µm CIPS/Ni). The CIPS shows weaker ferroelectric hysteresis loop at temperature higher than 310 K. 5

6 5. Temperature dependent I-V characteristics of MoS 2 and CuInP 2 S 6 2D vdw heterostructure FeFETs Figure S5. Temperature dependent I D -V GS characteristics at V DS =0.1 V of a MoS 2 /CIPS 2D heterostructure Fe-FET measured at room temperature with back-gate floating. The thickness of CIPS and MoS 2 are 0.5 µm and 8 nm, respectively. Fig. S5 shows temperature dependence of I D -V GS characteristics at V DS =0.1 V of a MoS 2 /CIPS 2D heterostructure Fe-FET measured at room temperature with back-gate floating. The thickness of CIPS and MoS 2 are 0.5 µm and 8 nm, respectively. The device has a channel length of 2 µm and channel width of 4.1 µm. It s clear to see that the ferroelectric hysteresis loop becomes smaller at higher temperature close to the Curie point, which is consistent with temperature dependent P-V measurement. 6

7 6. Landau coefficients from P-E measurements Figure S6. Experimental P-E measurement of a MIM capacitor with 500 nm thick CIPS and the fitting curve for Landau coefficients. The Landau coefficients can be extracted using L-K equation of ferroelectric insulator and the procedure described in ref. 2. The L-K equation is written as = + + (1) where V FE is the voltage across the ferroelectric capacitor, t FE is the thickness of ferroelectric insulator, Q is the total charge density in the ferroelectric capacitor. Landau coefficients are extracted based on eqn. (1) as shown in Fig. S6 to be α=-3.35e8 m/f, β=1.14e11 m 5 /F/coul 2, and γ=1.35e12 m 9 /F/coul 4. C FE can be calculated at zero charge condition as 3.73e-7 F/cm 2 with t FE =400 nm. While the semiconductor capacitance in MoS 2 can be estimated as C S =ϵ MoS2 ϵ 0 /d, where d is the distance between carrier electron and CIPS/MoS 2 interface and ϵ MoS2 ~4. The C S can be estimated as between 3.54e-6 F/cm 2 to 5.06e-7 F/cm 2, corresponding to d between 1 nm and 7 nm. As C FE and C S is comparable, the tuning of C S can effectively modulate the capacitance matching so that affects the Fe-FET operation. 7

8 7. Band diagrams of CIPS MIM capacitors in different polarization states Figure S7. (a) Schematic of a CIPS MIM capacitor. Band diagram of the CIPS MIM capacitor in (b) no polarization, (c) polarization down, and (d) polarization up states. Band diagram of the CIPS MIM capacitor in polarization down with (e) positive and (f) negative voltage bias. 8

9 Fig. S7(a) shows the schematic of a CIPS MIM capacitor. Fig. S7(b) shows the band diagram of a CIPS MIM capacitor without polarization, and flat band conditions are assumed for simplicity so that no charge distribution when no voltage is applied. Fig. S7(c) shows the band diagram of a CIPS MIM capacitor in polarization down state, the polarization charges lead to an increase in top metal/cips Schottky barrier height. Thus, CIPS is in low-resistance state when voltage is positive (as shown in Fig. S7(e), corresponding to 2 in Fig. 5(b)) and is in highresistance state when voltage is negative (as shown in Fig. S7(f), corresponding to 3 in Fig. 5(b)). Fig. S7(d) shows the band diagram of a CIPS MIM capacitor in polarization up state, the polarization charges lead to an increase in bottom metal/cips Schottky barrier height. Thus, CIPS is in high-resistance state when voltage is positive (corresponding to 1 in Fig. 5(b)) and is in low-resistance state when voltage is negative (corresponding to 4 in Fig. 5(b)). 9

10 REFERENCES 1. Maisonneuve, V.; Evain, M.; Payen, C.; Cajipe, V. B.; Molinié, P. Room-temperature Crystal Structure of the Layered Phase Cu I n III P 2 S 6. J. Alloys Compd. 1995, 218, Si, M.; Su, C.-J.; Jiang, C.; Conrad, N. J.; Zhou, H.; Maize, K. D.; Qiu, G.; Wu, C.-T.; Shakouri, A.; Alam, M. A.; Ye, P. D. Steep-Slope Hysteresis-Free Negative Capacitance MoS 2 Transistors. Nat. Nanotechnol. 2018, 13,