Realistic Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits

Transcription

1 Realistic Faults Mapping Scheme for the Fault Simulation of Integrated Analogue CMOS Circuits Michael J. Ohletz Institut für Theoretische Elektrotechnik - Universität Hannover - Germany mo@tet.uni-hannover.de Abstract A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault 1 Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical local layout structures of analogue designs. Specific defects are assumed and their electrical failure modes are evaluated and mapped onto appropriate model faults. It is shown that some assumed hard faults at the schematic level are unrealistic and unlikely and that new types of fault constellations emerge including multiple or complex faults. Beside the different distribution of faults the overall number of faults decreases whereof additional realistic soft faults emerge. For an operational CMOS amplifier the overall number of 47 single hard faults assumed at schematic level dropped to 7 realistic and likely hard faults. 1 INTRODUCTION Commonly, analogue testing is understood as testing based on predefined specifications [DUHA79, BAND85] which must be met. If a specification is not met the device under test, DUT, is either graded or discarded. Since an out-of-specification response can be due to any defect this allows for a defectoriented view of testing [SAC95]. In contrast to specificationoriented testing the defect-oriented testing approach starts off from assumed defects or failure mechanisms, e.g. obtained from the production line. Due to the variety of possible defects/failure mechanisms the local electrical characteristic of a device can be altered in many ways. In fault analysis this is characterised by electrical failure modes [FAN87], e.g. an electrical short between two metal lines or the performance degradation of a transistor. In order to simulate the faulty behaviour of an integrated analogue circuit an appropriate and more abstract description of the respective electrical failure modes is necessary [TUCK76]. But, the variety of possible electrical failure modes makes this task of analogue fault modelling a difficult but key issue within analogue testing. In 1 This research was performed within the ESPRIT III project ARCHIMEDES and supported by the European Union under grant common use is the distinction into two (abstract) fault models: the hard fault model, HFM, and the soft fault model, SFM. In general the "Single Hard Fault Model (SHFM)" and the "Single Soft Fault (SSFM)" are assumed, respectively. An appropriate fault model representing electrical failure modes and defects, respectively, is always a trade-off: the abstract model fault assumption (further referred to only as fault) should be based upon realistic data e.g. obtained from failure analysis, but, on the other hand the fault model must be still manageable within an automatic fault simulator, i.e. the number of faults simulated must be restricted and the representation of the faults, referred to as fault simulation model, must be as simple as possible but still adequately realistic. The fault simulation model (FSM) is one possible electrical network representing one model fault, e.g. the FSM resistor for the abstract model fault short. Another aspect to be considered is the simulation time for realistic circuit sizes [LIP88, MIL89, OHL89]. Traditionally, the fault assumption is made at the schematic level i.e. for a transistor single six hard faults are assumed and two for passive elements. These assumptions are made irrespective whether or not they are realistic. Soft faults are predominately chosen intuitively with respect to the parameters and the values of deviation. This paper deals with a layout-based scheme to obtain a more realistic fault assumption for either hard and soft faults. STATE-OF-THE-ART Fault modelling for analogue circuits is a relatively recent topic in current analogue testing. Nevertheless fault models have been used for more than two decades, namely the sixties and seventies. But, due to the nature of analogue circuits fault modeling has been and still is a controversial issue. But nevertheless it is in common use [DUHA79, PLI79, BAND85, OHL91] to classify faults in analogue circuits into two categories: - Catastrophic Faults or Hard Faults - Deviation Faults or Soft Faults Catastrophic faults, often also referred to as Hard Faults, are caused by random defects e.g. dust particles and can cause short and open circuits or large scale deviations of design para-

2 meters like e.g. the aspect ratio of MOS transistors [MIL89]. Deviation faults, also denoted as Soft Faults, are representing parameter deviations of the nominal value which left their attributed tolerance band. These faults are caused by statistical fluctuations in the manufacturing process and are also referred to as parametric faults [MIL89]. Among soft faults are socalled matching faults which are caused by process gradients and effect matched devices like for instance the gates of a differential pair. SHFM and SSFM are applied to either bipolar and MOS circuits. From reliability investigations a lot on defects and failures mechanisms are known [FAN87], [FAN85], [AME87]. It turned out that many electrical failure modes are short and open circuits or leaky junctions which could be represented by hard faults. Within a study of the Integrated Circuit Engineering Corp. [ICEC77], [DIC78] an ensemble of digital, memory and analogue ICs was investigated. It is reported that 54% of all faults observed at the input and output pins were electrical shorts and opens. An amount of 8% of the failures was denoted as "mal-functions" which in turn could possibly emanate from "internal" electrical shorts or opens. Others report that 75% [GAL80] and 83.5% [STAP83], respectively, of all failures observed could be attributed to catastrophic faults. Currently in most cases the fault assumption for a CMOS transistor comprises six single hard faults: Shorts between gatedrain, gate-source and drain-source and opens on the gate, the drain and the source. On passive elements like resistors and capacitors two faults, an open and a short fault, are assumed. This assumption is made on the basis of the schematic irrespective whether this assumption is realistic or not. One way to circumvent this problem is to run a so-called Inductive Fault Analysis, IFA where spot defects are springled over the layout and then defect simulations are performed e.g. using the defect simulator VLASIC [WAL86]. IFA has been proposed for digital circuits [SHEN85]. Later applications of IFA were reported for an analogue neural CMOS circuits [FEL91] and for mixed-signal ICs [MEI91]. But there are some restrictions associated with this approach: First, the fault list for the fault simulation can only be obtained at the end of the design cycle after the layout has been finished.whereas the layout for small analogue ICs might be available soon after the design has been started this is not true for complex mixed-signal ICs. Late modifications in the layout may directly effect the fault list which then in turn requires an update by re-running IFA. Such alterations could be provoked by testability considerations itself during the design process. Secondly, the effort to perform a complete IFA can be fairly time consuming. But, some conclusion about realistic faults can be already drawn prior to the precise knowledge of the actual final layout. This paper describes such a scheme called Local Layout Realistic Fault Mapping, L RFM [OHL96-1], [OHL96- ] for analogue CMOS circuits. Since this scheme focuses on local layout structures it is complementary to IFA. Currently the scheme is also applied to analogue bipolar and BiCMOS ICS. The next paragraph describes the L²RFM scheme. 3 THE L²RFM SCHEME As pointed out in the previous paragraph, at least hard faults must be taken into account. At the beginning of a design the only information available for the selection of particular faults is that of the circuit schematic (net list, e.g. SPICE). Only very limited conclusions can be drawn whether or not the fault assumptions made are realistic. From fig. 1 it is obvious that the short fault between gate and drain on Q1 and Q6, respectively, are necessary by design and thus, the additional short fault assumption is superfluous. Consequently, this fault assumption could be considered as unrealistic. Note, that the term "realistic fault" and unrealistic fault only refers to the possibility for defects that could be represented by such a fault. But, it does not further imply that the assumed fault is realistic with respect to its likelihood. The likelihood of a fault depends on several different parameters e.g. how many defects are covered by the respective fault or how realistic is the assumed defect itself. Beyond this point no further conclusions can be drawn from the schematic description at that time. In order to prove whether or not the remaining faults assumed are realistic the layout of the circuit must be investigated. One way is the inductive fault analysis another one is the proposed Local Layout Realistic Faults Mapping scheme further described. The L²RFM scheme is based on the fact that integrated analogue circuits (also of course as part of a mixed-signal ICs) are frequently composed of only a few recursively occurring primitive macros such as current mirrors, differential pairs, Darlington configurations etc.. These configurations can be easily identified in the schematic and netlist. Beside these macros there are typical layout structures. Due to matching considerations it can be supposed that for these small macros, or primitive macros typical layout structures will be encountered. The limitation of this scheme is directly related to the fact that the actual overall design will vary from case to case. But on the other hand, there is some evidence that investigating typical layouts of integrated analogue circuits could yield more realistic and to some extend versatile fault assumptions. This will become true the more layouts are investigated. Currently this work in planned and partially already on the way within new research projects. The idea of L RFM now is to search for typical layout structures of different integrated analogue circuits and then to systematically assume different types of defects. In the next step the impact of the particular defects is investigated and mapped back onto respective faults at the schematic level.

3 A very typical analogue circuit frequently encountered is the operational amplifier. The example chosen for the sake of simplicity, shown in fig. 1, is a low current operational amplifier [HAS88] in n-well CMOS technology. It comprises eight enhancement mode transistors (n- and p-channel) and one poly-si - Al capacitor for the internal frequency compensation. Figure depicts the layout of the amplifier. The biasing of the V dd I bias International Test Conference, pp , October 1996 After this first part of the scheme in the second part faults previously assumed at the schematic level can now be verified and conclusions about the likelihood and versatility of a fault can be drawn. This process is aimed at a reduction of the contact defects simulation time, e.g. using the analogue fault simulation tool polysilicon and metal cracks AnaFAULT [SEB95], by excluding non-realistic faults from pin holes and other defects and by updating of the initial fault list with realistic faults. The initial fault list within these investigations is the complete SHFM set. Since the later layout of the overall circuit may vary only defects on single elements/structures are considered. Especially, such defects are excluded impacting devices which are topologically close but electrically not connected to each other directly. This is done since the occurrence of these defects is layout dependent and therefore can not be generalised. The proposed scheme can be easily extended to analogue library cells. Unlike the case above the cell layout is known and fixed. Thus, L²RFM could be used to determine the set of realistic faults for each cell without the restriction to characteristic layout structures only. As a synergy L²RFM allows to investigate layout in order to make them more robust. In the following paragraph the L²RFM scheme will be illustrated for an example. 3.1 APPLICATION OF LRFM Q1 Q Q3 For the investigation [OHL93] the following defects are considered: I bias +I - I n-well n+ Q1 100/5 well contacts p+ Q4 50/5 Q5 50/5 n+ Implant p+ Implant Poly Al Q 100/5 Q3 100/5 C comp. Q6 50/5 Q7 50/5 Q8 90 /5 p+ = 0.7 pf out substrate contacts Fig. Layout of the operational amplifier of fig. 1 in n-well technology The results of the latter defects will be described in more detail in a further paper. Here it will be discussed only briefly. Before the L²RFM is applied the possible single faults at the schematic level should be considered. This initial fault list will then be compared against the layout realistic faults. Looking at the schematic of fig. 1 it appears that the complete initial list of "schematic faults " comprises 5 possible open faults. One open on each terminal of the transistor and one for the capacitor. Furthermore, there are possible schematic short faults. This takes into account that two short faults on Q1 and Q6 are irrelevant since they are identical with the designed short circuits between gate and drain and that the short fault on the capacitor is equivalent with the gate-drain short on Q8. Q4 C + V in Q5 -- OUT V in Q8 V Q6 Q7 ss Fig. 1 Schematic of a standard CMOS operational amplifier with external biasing input and output stage can be adjusted by an external biasing cell e.g. from an analogue cell library CONTACT DEFECTS The first class of defects addressed are "missing contacts" in the course of which it is assumed that the defect at least impacts one contact. Figure 3 shows the different defect locations within the layout. Each defect is denoted by a letter and a number related to the number of contacts associated with the considered contact configuration. There are four different types of open faults: The term schematic fault will be further used to distinguish between faults assumed at the schematic and those derived from the layout investigation.

4 gate open (floating gate) drain open source open floating substrate/n-well I bias +I - I A1 C1 K3 B1 O31 D H4 I4 E M31 N9 J8 L9 Fig. 3 Layout with assumed contact defects Some missing contact situations cause open or floating gate configurations. In the cases B1 and C1 only one transistor gate is effected corresponding to single gate open faults as would Type Device (Defect) D G S Single Open Q1 (K3) 3 G9 Q4 (H4; B1) 4 1 Q5 (I4; C1) 4 1 Q6 (H4) 4 Q7 (I4) 4 Multip. Open Q1-Q3 (A1) 1 Q6-Q7 (D) Node Open Q8, C (E) Tab. 1 Output (4 contacts) (F4) Types of open faults due to missing contacts if at maximum four defect contacts are assumed (D: Drain, S: Source, G: Gate) have been assumed at the schematic level anyway. But there are instances where multiple open gate faults are caused, e.g. if contact A1 is absent such a multiple fault occurs. In this particular case all three gates of the transistors Q1 - Q3 are floating. But note, that due to the layout of the gate connection F4 out of Q1 - Q3 their gates remain connected to each other. This layout configuration is a typical structure which can be encountered very often whenever gates of transistors are connected in series as in case of active loads and biasing configurations. Since only single faults were assumed originally, this type of fault did not emerge in the initial schematic fault list. This fault situation can only be identified by the inspection of the layout. But, since it is a typical structure it can now be assumed also from the schematic without knowing the layout. The different types of faults due to contact defects are collocated in tab.1. For the cases D and E the absence of two contacts is required to cause a floating gate fault. The D defect again causes a multiple open gate fault, whereas E causes a socalled DC-open gate fault. DC-open refers to the fact that due to the capacitor configuration the Q8-gate remains capacitively connected to the output. Contact defects on the drain side contacts (G9-I4) only cause drain open faults if all 4 and all 9 contacts, respectively are absent. Especially in the case of defect G9 (= 9 contacts!) it seems reasonable to assume that this fault is less likely compared with contact defects of lower contact count. Since the contact count for defect J8 is also relatively high its likelihood of occurrence seems to be not very high. Thus, due to the contact counts the drain open K3 on Q1, defect H4 on Q4 (6) and defect I4 on Q5 (Q7) are more likely to occur. Knowing the aspect ratio of the particular transistors as well as the feature size of the contacts it can easily be decided from the net list information how many contacts will be implemented and thus how likely a respective open fault due to such contact defects will be. The decision about the likelihood could either be established upon reliability data or more intuitively by referring to the number of contacts. As shown in fig. 3 a contact fault on the output (defect F4) could be assumed due to the number of contacts. But on the one hand an output open is a trivial fault which does not need to be addressed and on the other hand the number of four contacts is arbitrary and can not be considered as a typical layout structure for an output node. Thus, this defect is not further regarded. Finally, transistors with sources connected to the power rails + are considered. These transistor terminals are made from n or + p diffusion. All respective source terminals are furthermore also connected through the respective type of diffusion. These diffusion leads are "nailed" by chains of many contacts (9-31!! in this example) to the power rails. Due to this implementation open faults caused by missing contacts appear to be extremely unlikely. From this circumstance the following rule for the fault assumption at the schematic level could be stated: Open faults on transistor sources connected to the power rails are unrealistic and can therefore be discarded from the initial fault list. If contact defects do not impact all contacts which are necessary to yield an open fault this defect can potentially produce a soft fault. This type of fault diminishes the overall

5 dynamic performance of the circuit. If the characteristic of the particular contact is known this type of soft fault can be included in the fault list as a realistic soft fault. Due to what has been described before the number of open faults which must be addressed has decreased and furthermore depends on the assumed number of missing contacts. As can be seen from fig. 4 and table 1 only 3 faults must be taken into account if the absence of only one I bias Q +I J - I Y W H P R S L V D Failure Cases 4 contacts 3 contacts contacts 1 contact Shorts (schematic) Opens (schematic) No. Failures A B I C X K Z M T F N E U O G 5 Fig. 4 Distribution of faults versus different number of contact defects (Bottom bars are faults from the schematic) contact is assumed. This case includes single gate as well as multiple gate open faults. Even in the case of four missing contacts the number of open faults is still significantly lower than in case of the assumed complete initial schematic fault list. 3. CRACKS IN THE POLYSILICON AND METAL LEADS This paragraph deals with cracks, e.g. micro cracks, within the polysilicon and metal leads. Cracks within the diffusion are not considered to the same extend since they seem to be very unlikely. Figure 5 shows the layout along with assumed cracks for the example. Fig. 5 Layout with assumed cracks in the polysilicon and metal layer Again there are different types of defects depending on where the defect is located: out polysilicon cracks over gate oxide area polysilicon cracks over field oxide area metal cracks soft fault 3..1 CRACKS WITHIN THE POLYSILICON LAYER At first polysilicon cracks within the active area (gate) of a transistor will be considered. Since in the self-aligning gate technology the polysilicon structure is used as a mask during the diffusion process, a gap in the polysilicon yields a conducting channel. Thus, the transistor exhibits a defect which could be represented as by the model fault short (Note: The fault simulation model in this case could be a resistor whereas the model short fault is abstract!). But depending on the location and the width of this gap the transistor operation might only be more or less diminished. If the resistance of the created channel is low enough the transistor does not operate anymore at all and it is realistic to assume a single short fault. But, if the gap occurs more closely to the site where the gate is connected to other components (gate input), the defect situation could be described by a short fault accompanied by a gate open (floating gate) on the same transistor. As a result a double fault situation on the particular transistor occurs which comprises of a drainsource short and a gate open fault. In general this type of fault constellation can occur on all transistors. In the operational amplifier example crack C results in such a multiple fault only effecting transistor Q3. The same fault constellation can be assumed on all other transistors, e.g. like in case of defect D. The only difference is the number of additional open faults on other transistors which depends on the location of the defect. If the gap is located closely at the opposite side of the gate connection terminal, the defect could cause a leaky transistor with a diminished performance. This situation can be described by a respective soft fault. In case of defect A on Q1 it can be easily recognised from fig. 5 that in addition to the situation on transistor Q1 the gates of Q and Q3 are disconnected from Q1. A similar fault situation is caused by the failure B on transistor Q. These situations are described by multiple faults (tab. ). Both types of fault did not occur in the initial fault list. As already pointed out before, it is the special gate configuration often encountered along with biasing transistors which causes these new types of faults. Again this can be derived from the schematic since this layout situation is typical in analogue design. Another type of defect denoted F (fig. 5) causes a similar fault. Here the assumed failure e.g. due to any lithographic defect provokes that the width of the respective transistor gate becomes too small. As a result the respective transistor is shunted by this defect. Depending on the amount of misalignment the transistor either behaves like a leaky transistor which can be described by either a soft fault or a short if the transistor operation is negligible. From a comparison with the layout it is obvious that the defect causing a too short gate only can occur on the transistors Q3 - Q7. Due

6 OPEN SHORT Device (Defect) D G S G D G S D S I Q3 (I) 1 Q4 (J) 1 Q5 (K) 1 A Q6 50/5 B Q7 50/5 Q6 (L) 1 Q7 (M) 1 II C (G) III Q1-Q3 (H) 3 Q-Q3 (type I) IV Q8, C (N) V Q3 1 1 Q4 (D) 1 1 Q5 (type D) 1 1 Q6 (type D) 1 1 Q7 (type D) 1 1 VI Q1-Q3 (A) 3 1 Q-Q3 (B) 1 IV Q8, C (E) 1 1 Tab. Fault situations due to cracks within the polysilicon layer (I: single open, II: C open; III: multiple opens; IV: add. C Open; V: DS-short & single gate open; VI: DS-short & multiple opens) to the gate configuration on Q1 - Q and on Q8 this type of defect is not possible. A special situation occurs along with the transistor configuration Q6-Q7. In the layout shown in fig. 5 the above mentioned defect only causes a multiple fault constellation on a single device. But there is an alternative design possible as depicted in fig. 6. In this case the fault situation is the same as in case of crack C and D, respectively (cf. tab. ). In the original design this defect was neither possible. Since the actual layout is not known this failure situation should be taken into consideration, too. Fig. 6 Alternative design of the common gate configuration for the active load transistors Q6 and Q7 of the original layout from fig. Defect E shorts the transistor Q8 simultaneously connecting the capacitor to Vss potential. This type corresponds to the combination of a drain-source short with a gate open. From the previous consideration it can be summarised: Cracks within the gate area of a transistor can be described by a multiple fault constellation consisting of a drain-source short and one or more gate opens. Even though a single open fault on the capacitor can be easily assumed it is obvious from the layout that an open capacitor seems to be very unlikely. The capacitor s one electrode is a metal plate whereas the other one is made from polysilicon directly "integrated" into the gate of transistor Q8. An open due to a polysilicon crack only is possible if the crack is located in the small area right at the end of the gate of transistor Q8 (defect G) or if the crack is large. In consequence the likelihood for such a defect could be considered to be not too high. Polysilicon cracks outside the gate areas normally cause defects which can be described by open gate faults (I - M). Among these the defect J and K seem to be the most likely ones. The likelihood for the cracks I and L, M seems to be very low since the area to establish a single open is very small. A situation described already before occurs with the crack N which again can be described by a DC-open fault on Q8. That type of fault neither was assumed in the initial fault list, since faults were attributed only to elements rather than to nodes. Crack defects can further cause failure situations which are described by multiple open faults. In case of defect H e.g. the defect can be described by a triple open fault effecting Q1 - Q3. Since the respective area is very small a respective fault is unlikely. 3.. CRACKS WITHIN THE METAL LAYER The metal layer is the most sensitive layer with respect to defects causing electrical opens and especially shorts (bridging). Since metal is predominantly used for wiring shorts are much more depending on the global layout structure. Most of these shorts can be covered by assuming shorts between two

7 OPEN Fault Type Device (Defect) D G S Single Open Q1 (P) 1 Multiple Opens Tab. 3 Q4 (R; type Q) 1 1 Q5 (type R; Q) 1 1 Q1-Q3 (Q) 1 3 Q6-Q7 (S) Add. C Open Q8, C (T) Node Open Output Open Fault situations due to cracks within the metal layer terminals of an element. Moreover these shorts could be automatically extracted by an automatic fault extraction tool e.g. like LIFT [SEB95] [TEI91]. Thus, even though this type of fault is important it is not further considered here explicitly. As in the previous defect cases metal cracks cause failure situations which can be described by single as well as multiple open faults (tab. 3). Cracks in the leads which are connected to only one gate cause single gate open faults on the respective transistors. Crack P causes a situation which corresponds to a single drain open fault. Some metal cracks of gate-connected transistor configurations provoke multiple gate opens. In the CMOS amplifier example crack Q e.g. yields a fault constellation where the biasing transistors Q1-Q3 are disconnected from the external biasing. In consequence the gate-connected transistors Q1 - Q3 along with the drain to gate connection is left uncontrolled. A similar situation results from crack S causing floating gates (Q5, Q6). The assumed crack T in the metal lead disconnects the common node of gate Q8 and the polysilicon side of the compensation capacitance C from the preceding input stage. Except for the drain-source short this failure is an equivalent fault to the one caused by the previously described crack N. As mentioned the operational amplifier is assumed to be processed in an n-well technology using two types of enhancement transistors: n-channel devices on p-type substrate and p-channel devices located within the n-well. Connections between transistors of the same type are normally made through diffusion or polysilicon. In some cases especially for the global wiring metal is used. In contrast to that any connection between transistors of different type must be made in metal to prevent parasitic transistors. In consequence all connections between devices within the well and those on the substrate will be metal connections. Due to the associated contacts and steps the chance for a defect e.g. crack R (insufficient step coverage) is higher compared with an open (e.g. defect Z) of a "simple" diffusion line. For wide transistors the probability for an open fault may be less than for narrow transistors. Thus, in this case drain open faults on the transistors Q4 - Q7 (W=50µm) should be reasonably assumed whereas for the transistors Q3 (W=100µm) and Q8 (W=90µm) the open (defect U) seems to be less likely. Finally, the power supply rails are considered. Here the impact of a crack e.g. due to electro-migration strongly depends on its actual location. If the power supply rail is broken outside the contact row area like depicted e.g. by crack W for V or Y dd for V ss, all sources connected directly to the power supply rails are disconnected. Thus, the whole circuit is effected and the behaviour of the circuit becomes fuzzy since all potentials are undefined and the well diodes are no longer reversed. Even though this type of defect might occur it does not need to be added to the initial fault list since this catastrophic malfunction of the circuit can be easily detected. If the defect occurs within the contact rows (V, X) then the location of the crack again effects the overall behaviour of the circuit but now with respect to the performance. Such defects do not cause source opens on the transistors connected to the power rails because the sources are also connected together through diffusion. In general the described defect diminishes the overall dynamic performance and could be the reason for an early aging. Thus, it can be stated: All source open faults on transistors directly connected to the power supply rails are very unlikely and therefore are no candidates for the fault list. Figure 7 depicts the distribution of the different types of Schematic Poly-Si Cracks Metal Cracks Aggregated Failure Cases Single Opens Single DS-Shorts Single Shorts Else Multiple Opens DS-Short/Single Open DS-Short/Multiple Opens Fig. 7 Distribution of schematic and layout realistic faults due to cracks faults as previously described with respect to the assumed defect. In the most right hand group all faults have been aggregated. Note that different defects can establish the same fault situation. As it can be seen from this diagram the number of faults has significantly decreased. For example the originally assumed number of 5 single open (schematic) faults now reduces to 9. Overall the number has reduced from

8 schematic faults to layout realistic faults. Within the of the capacitance in general is much larger. Thus, if an oxide resultant fault distribution two new fault situations namely the breakdown occurs this defect should be described by a single multiple gate open and the combination of drain-source short soft fault. The corresponding fault simulation model could be and gate open either single and multiple have emerged. Due to a capacitor in parallel with a resistor. contact and crack defects there is no single short fault any further. Within the next paragraph oxide breakdowns in the overlap region of the gates are assumed (F-M). These areas are + relatively small, e.g. for a depth of the n diffusion area of about 3..3 OXIDE AND OTHER DEFECTS 0.1µm µm the overlap ranges between 0.08µm µm. From this it is obvious that the likelihood of such The last class of defects considered are defects causing gate defects could be considered as not too high. If these defects are oxide breakdowns and defects changing the gate shape. The assumed to be the only source for gate-source and gate-drain occurrence of oxide breakdowns can either be due to electrical short then the overall occurrence for this type of short faults can overstress, EOS, or to electrostatic discharge, ESD [Ame87]. also be considered low as well. Consequently the assumption During normal operation a time-dependent breakdown could of such short faults can only be verified from "global shorts" either within the polysilicon or the metal layers. These faults are realistic only if the final layout of a circuit is known and an automatic fault extraction has been performed. Hence, it seems to be reasonable to include these shorts within the initial fault M I bias A list in order to be on the save side. Further, the fault simulation I N model should be derived for briding defect rather than for pinholes in the overlap area. Provided that oxide breakdowns of +I L B - I H the above mentioned type are considered it appears that they poly-al cap. out should be described by single short faults. F J C Fig. 8 Layout with oxide breakdown defects within gate and capacitor area along with transistor gate length deformation occur if the circuit is exhibited to radiation. Generally the probability of such defects depends on the quality of the gate oxide. In fig. 8 the defects considered are depicted. The first case deals with breakdowns assumed in the center of a transistor gate (pin holes). Such defects yield a resistive connection between the gate and the channel or substrate. Does the defect occur on a gate of a transistor with no other gates connected to it (B) then this defect can be considered as a single short fault (the corresponding fault simulation model could be e.g. a resistor). If the transistor gate is connected to other gates like in case A and C than more than one transistor is effected. The strength of the impact on the defect-free transistors depends on the properties of the pin hole. Whenever the resistive nature of such a defect is taken into account it will impact the behaviour of the concerned transistors and thus the overall performance of the circuit. In consequence this defect can be a candidate for a realistic soft fault. A similar case emerges if the breakdown occurs in the oxide of a capacitor (E). In the particular example the capacitor has been designed as a polysilicon - metal capacitance. Compared with the gate areas of the transistors the area of the electrodes D E G K Finally deformations of the transistor gates will be discussed. Shortened gates have already been addressed before. Deformations changing the length of gates as depicted in fig. 8 (N) are considered. Defects during the formation of the polysilicon resulting in a unintended variation of the channel length L are defects responsible for soft and matching faults. Since the drain current is I d ~ W/L, a reduction of the length L increases the drain current while an increased L decreases the drain current. As a result the biasing conditions are invalidated and the performance of the circuit is diminished. Depending on the location of the defect as well as the size this type corresponds to single or multiple faults. For the occurrence of a multiple soft fault on gate connected transistors the variation of the whole polysilicon line with respect to the lengths of the gates must be assumed. 3.3 FAULT MAPPING Chapter 3.3 describes the process of mapping the layout realistic faults onto the schematic circuit description level. Only those faults are mapped which to some extend can occur independently of an actual layout. This assumption can be made since frequently characteristic layout structures of primitive analogue macros or building blocks are encountered. Faults originating from global defects like shorts between adjacent metal or polysilicon lines are not included in the mapping since the occurrence of these defects are too layout specific (cf. previous paragraph). Before the mapping for the example is performed the fault distribution from the layout investigation shall be compared with the original fault distribution of the initial fault list.

9 are possible. But as described previously the inclusion of such FAULT DISTRIBUTION faults appears to be not justified with respect to the very small area available to establish the respective defect. Thus, if the In fig. 9 the distribution from the schematic to possible and consideration is restricted to single elements as it is assumed finally to the realistic faults is shown for the operational for this investigation, such faults must be attributed as realistic amplifier example. It appears that the number of single gate but unlikely. Consequently they do not appear anymore in the open faults dropped from eight schematic to five possible and final fault list. But due to the likelihood of occurrence within in the end to only two realistic single gate open faults. Also the "global layout" it could be reasonable to keep these faults dramatic is the drop of single drain or source open faults by included in the initial fault list. Comparing the three different 69% from 16 to five. All of them are likely. The open on the distributions of faults with respect to the overall number of capacitor assumed at the schematic level disappeared. Even faults it turns out that in the initial schematic fault list 47 though it is realistic it is not very likely. Not included in the different faults, 5 single open and single short faults were schematic initial fault list are multiple gate open constellations. accommodated. From that the number changes to overall 45, But there are four cases of such fault situations which remain whereof 11 faults are single opens, are single shorts and 1 realistic. faults are multiple or complex faults. Finally, the number of faults further decreases to overall 7 if the likelihood of the Considering short faults it immediately is conspicuous that realistic faults is introduced. Only seven single open faults and non of the eight initially assumed single drain-source shorts is eight single gate to channel short faults remain but no other realistic. The inversion of the statement that there are no drain- single shorts. The remaining 1 faults again are multiple or complex faults Single Gate Opens Single Capacitor Open Single GD/GS Shorts Sing. Gate-Channel Short Schematic Possible Realistic Single D or S Opens Multiple Gate Opens Single DS-Shorts Open/Short Combination Fig. 9 Comparison between initially assumed schematic faults and likely realistic faults source short at all is not correct but this type of short always is accompanied by at least one gate open if assumed on the transistor. Thus, all eight schematic single drain-source shorts are transformed into eight open-short combinations, including combinations with multiple open gates. Due to their considered likelihood all such fault combinations must be included in the fault list. Another type of short fault which was not included in the initial schematic fault list is the gate to channel short, whereof eight situations due to the number of transistors in the operational amplifier example are possible. This type of short appears to be more difficult to model (w.r.t. fault simulation model) and is one example of a realistic soft fault CONCLUSION A new fault modelling scheme for integrated analogue circuits referred to as Local Layout Realistic Fault Mapping has been introduced. The scheme has been demonstrated for an example of a CMOS operational amplifier, but is especially intended for mixed-signal ICs. It was shown that by studying typical layout structures realistic fault assumptions can be derived. It turned out that some versatile conclusions about realistic fault assumptions can be drawn. These assumption can than be used for other circuits prior to the final layout. Specific defects were assumed comprising contact defects, cracks in the polysilicon and metal layer as well as oxide defects and geometrical perturbations of gates. It was shown that some originally assumed hard faults at the schematic level are unlikely or even unrealistic and that new types of fault constellations emerge including multiple or complex faults. Beside the different distribution of faults the overall number of faults decreased and in addition realistic soft faults emerged. For the operational CMOS amplifier it was discussed how the overall number of 47 single hard faults assumed at schematic level dropped to 7 realistic and likely hard faults. [AME87] 5 REFERENCES E. A. Amerasekera, D. S. Campbell, Failure Mechanisms in Semiconductor Devices, John Wiley & Sons, [BAND85] J. W. Bandler, A. E. Salama, Fault Diagnosis of Analog Circuits, Proc. IEEE, Vol. 73, No.8, 1985 Finally, shorts between gate and drain and gate and source, respectively will be considered. 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