10-1. Yield 1 + D 0 A e D 0 A

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1 ASIC Yield Estimation At Early Design Cycle Vonkyoung Kim Mick Tegetho* Tom Chen Department of Electrical Engineering Colorado State University Fort Collins, CO e{mail: TEL: (970) , (970) FAX: (970) *Hewlett{Packard Company Manufacturing Test Division Loveland, CO e{mail: TEL: (970) ABSTRACT This paper describes an ASIC yield model based on the CMOS bridge fault model. The model predicts defect sensitive area early in the design cycle as a function of number of gates and nets. 1 INTRODUCTION The semiconductor industry has continuously been looking for ways to improve yield and reduce manufacturing cost. Although chip yield is the key element of IC manufacturing economics, the estimation of yield early in the design cycle still remains a challenging problem. Early prediction of yield is important for costing and capacity estimations. An early warning of low yield may trigger design modications while there is still time, thus meeting the cost and quality goals. Previous research proposed various IC yield models, and Cunningham [1] summarized popular IC yield models. Popular yield models include Poisson, Murphy, Seeds, Moore, Price, and negative binomial. Table 1 summarizes chip yield models. All the above yield models are function of defect spectrum(defect density) D 0 and chip area A. Therefore, the accuracy of chip yield estimation mainly depends on the estimation accuracy of the chip area since the defect spectrum information is usually given by the fabrication line defect statistics. Figure 1 shows the yield graphs of ve popular IC yield models according to the average number of defects D 0 A. According to gure 1, Poisson yield model becomes more pessimistic as D 0 A value increases. The third column of table 1 shows the result for D 0 A = 4. Cunningham suggested to use Poisson yield model for IC chips where die sizes are relatively small ( 0.25 cm 2 or mil 2 ) or D 0 A products below 1. And yield of large VLSI chips which have large average number of defects value are better predicted by the negative binomial yield model because it considers the clustering of defects. An improvement in yield modeling was proposed [9] by Domer, Foertsch and Raskin. Their model es Table 1: Basic IC Yield Models Name Model Yield Poisson Y = e?d0a h i 2 Murphy [2] Y = ?e?D 0 A D 0A Seeds [3] Y = 1+D 1 0A Moore [4] Y = e?p D 0A Price [5] Dingwall [6] Neg. bin [7][8] Y = Q n i=1 Y = 1 + D0A 3 Y = 1 + D0A 1 1+D ia?3? n/a n/a timates the area which is sensitive to defects rather than using the whole die area. In their paper, an effective area 1 is estimated by three dierent types of circuit block such as logic, IO, and memory. The effective area is dened as an area which is sensitive to CMOS bridge faults, and more accurate yield prediction is possible by determining the eective area of the chip. They introduced a layout such SRAM is LOGIC is I=O is The eective area is dened as a product of total layout area and factor. However this eective area model does require chip layout information, and it neglects variation among the same circuit type. In our work, we propose a total sensitive area(tsa) model that can be used early in the design cycle, and that is not limited to circuit type, thus it is more accurate than the previous work. The sensitive chip area is estimated as a function of simple circuit parameters, which are usually available early in design cycle. Consequently, manufacturing chip yield can be estimated by the sensitive chip area obtained from the TSA model. 1 Eective area, sensitive area, critical area are used interchangeably in this paper.

2 1 Yield e D 0 A 1 + D 0 A 3 3 e D 0 1 A D 0 A 1 1+ D 0 A D 0 A 2 e D 0 A Figure 1: Chip Yield versus D 0 A for Five Yield Models 2 SENSITIVE AREA MODEL In the development of this model, we limited the scope to standard cell design, random logic, and inter{ gate routing bridge fault. However, we believe that the results are easily extendible to other circuit types. A bridge fault is modeled as a formation of low resistance path between two circuit nodes which forces circuit malfunctioning or performance degrading. The stuck{at fault model has been widely used as a standard fault model in IC industry, but recent work by Ferguson and Shen [10] showed conventional stuck{at fault model is not sucient to model all CMOS IC faults. Also Fritzemeier, Hawkins and Soden's paper [11] depicts the eectiveness of detecting CMOS bridge fault by using I DDQ test. And Shen, Maly and Ferguson's work on inductive fault analysis [12] proved bridge fault is the dominant fault type in VLSI chips. Sensitive area is dened as the area that is sensitive to bridge fault while rest of chip area is not sensitive to bridge fault. Since defect density is determined by IC process used, sensitive area remains the only variable that can be controlled by chip designers. Our objective was to develop a model which accurately estimates sensitive area of a circuit early in design stage with minimum number of circuit parameters. Consequently, a more accurate chip yield can be estimated by using the total sensitive area, TSA, rather than the whole area A. The proposed TSA model is shown in equation (1) which is a function of number of gates and number of nets. T SA = c 0 + c 1 gates 2 + c 2 p nets (1) Figure 2 shows three dimensional TSA model. The polynomial combination of parameter X(number of gates) and Y(number of nets) approximates extracted TSA(Z axis) data points, therefore estimated TSA function is mapped into three dimensional plane which Z Y 2500 Figure 2: Sensitive Area Model X is represented by parameter X and Y. The c 0, c 1, c 2 are layout dependent coecients, and these coecients will be changed according to the dierent CAD layout design packages such as automatic placer, router, layout compactor. 3 TSA Model Development Procedure The model was generated by determining the sensitive area of a number of circuits via inductive fault analysis, establishing a model to t the data as a function of circuit variables, and then validating with a number of dierent circuits. 3.1 Layout Generation We used the ISCAS 85 benchmark circuits and several internal CSU circuits to develop the model. The layouts of ISCAS 85 benchmark circuits and other benchmark circuits have been generated by automatic layout synthesis tools. 3.2 Sensitive Area Extraction Inductive Fault Analysis (IFA) methodology has been used to extract the sensitive area from the layouts. IFA is a systematic approach to extract all possible faults in an IC chip. Previous work [12][13] by Shen and Ferguson, Corsi and Morandi in IFA has proven eective to extract realistic CMOS bridge faults from a given circuit layout. 3.3 Parameter Selection Mapping the extracted TSA data into the optimum subspace consists of minimum number of circuit parameters among the possible circuit parameters which are number of gates (referenced structure, represents total number of gates) number of nets (including internal net, input pin, and output pin)

3 gate ratio (gates divided by area) logic depth (the longest logic path from an input to an output) cell size (transistor feature width) routing ratio (routing area as a percentage of the total block/ chip area) average fan{in/fan{out Among the possible circuit parameters, number of gates and nets showed good correspondence with experimental TSA data extracted from IFA, hence these two parameters are selected as model parameters. 3.4 Model Building Extracted TSA data are used to build the model through the curve tting of selected circuit parameters. As a result, an empirical rst order TSA model shown in equation (1) has been obtained. The behavior of a circuit's sensitive area could be better understood by a number of circuit parameters such as the number of gates, nets, I/Os, logic depth, routing ratio (ratio of routing area over total layout area), physical layout design rule of routing, etc. However, in real cases, not all of these circuit parameters are available in early design cycle, therefore the circuit parameters of the TSA model are selected in order to satisfy the following conditions. First, the selected circuit parameters need to be available early in the design phase. Second, the number of selected circuit parameters need to be minimized to reduce the redundancy. Even though TSA is a multi{dimensional function of many circuit parameters, it is possible to map the TSA into a smaller subspace by eliminating redundant circuit parameters. For example, the number of I/Os and the number of nets have positive correlation, therefore the number of I/Os is treated as a redundant circuit parameter. The rationale of these two constraints are following: The rst constraint makes early chip yield estimation possible, while the second constraint simplies the TSA model by reducing the number of variables. The proposed TSA model is obtained empirically through analysis of the experimental data and the curve tting method. The following procedure depicts the sensitive area estimation model development process. The proposed TSA model selects the most signicant circuit parameters among the possible circuit parameters. Among the possible circuit parameters, the number of gates and nets showed good correspondence with experimental TSA data extracted from Carafe IFA simulations. Therefore, these two parameters are selected as model parameters. The TSA model is shown in equation (2). T SA = c 0 + c 1 gates 2 + c 2 p nets (2) Where c 0 = , c 1 = ?5, c 2 = This TSA model equation is obtained empirically. TSA is proportional to the square of the number of gates, and proportional to the square root of the number of nets. In this work, the number of gates is the number of primitive gates which does not include complex gates. This equation can be understood in the following rationale. The physical area of the circuit increases in a square term for a linear increasing of the gates because placing a gate enlarges the layout dimension in both x and y directions. On the other hand, a linear increasing of the nets does not aect the layout in a square term, because the eect of increasing the number of nets can be absolved in the routing area since a single routing channel can be shared by multiple signal nodes. Therefore, its physical area impact is less signicant than that of the gate. The square and square root terms are obtained from curve tting. TSA / gates 2 TSA / p nets gates % ; T SA %% nets % ; T SA % The gates % implies that the number of gates has been increased while other parameters keep their values. And nets % implies that only the number of nets has been increased. The %% symbol denotes that TSA is more sensitive to the number of gates increase than the number of nets. 4 CHIP YIELD MODEL The next step in predicting the yield, is the selection of the actual yield model to be used. The Poisson yield model can be expressed as equation (3). Y = e?d0t SA (3) D 0 represents defect distribution statistics(defect density) per unit area. Another popular yield model is negative binomial that is dened in equation (4). Y = 1 + D? 0 T SA (4) where is usually referred to as the cluster parameter, and generally, increases with decreasing variance ( 2 ) in the distribution of defects. By selecting different values, various yield models such as Poisson, Murphy, Dingwall, and Seeds can be closely emulated [1]. Table 2 shows emulated yield models with corresponding values. The yield of the chip will be decreased exponentially by increasing TSA, or D 0 the defect density. This relationship is clear because the increasing of TSA implies the chip has more probability to be defective, while the increasing of D 0 implies poor process technology. Therefore, a high yield can be achieved by low defect density and small TSA.?T SA Y / e Y / e?d0 T SA % Y & D 0 % ; Y &

4 Table 2: Emulated Yield Models by Values Fab. Statistics Defect Density 10 to 1 Poisson 4.2 Murphy 3 Dingwall 1 Seeds Yield Model Circuit Parameters Sensitive Area Estimation Model Estimated TSA Chip Yield Model Predicted Chip Yield Figure 3: Chip Yield Estimation Process Figure 3 summarizes chip yield estimation process. The sensitive area estimation model estimates TSA of a chip and a selected yield model estimates the yield of the chip for a given defect density. 5 EXPERIMENTAL RESULTS The sensitive area model estimation result is shown in table 3. Ten ISCAS 85 benchmark circuits and nine other circuits selected from an edge detection chip are used to build the TSA model. Total ten benchmark circuits are used to build the TSA model and nine benchmark circuits are used to evaluate the model. The circuits used to build the model are not used to evaluate the model. In table 3, `xxx' indicates the circuit is used to build the model, hence it is excluded from calculating the estimation error. All of the benchmark circuits are fully combinational, with numbers of gates ranging from 100 upto The TSA column shows extracted TSA from the layout, and model column depicts estimated TSA by the model. Error column shows sensitive area estimation errors compared with layout extraction result. The TSA model estimation error is within 30% range which is acceptable for a rst order approximation without circuit layout and netlist data. Also note that the estimation error is small compared to the error incurred if one was to use the whole die area. Table 4 shows estimated yields of ve popular yield models based on the previous TSA results. Since real chip yield and defect statistic data are not available, detailed error analysis is omitted. The defect density D 0 is assumed to 1/cm 2 to simplify the scaling computation. Correct yield can be estimated by multiplying Table 3: Sensitive Area Extraction Results Name Gate Net TSA[10?4 cm 2 ] Extracted Model Error C C xxx xxx C C xxx xxx C C xxx xxx C C xxx xxx C C xxx xxx CIR xxx xxx CIR CIR xxx xxx CIR CIR xxx xxx CIR xxx xxx CIR CIR CIR xxx xxx Error.2851 real defect density data to the results. The yield model was used to predict the yield of a production part described in [14], which is a fully static standard cell design with 8577 gates and nets. Based on the number of gates and nets in the part without knowing its layout, the model predicted 0.63 cm 2 in total sensitive area. Using a defect density of 1/cm 2 and Seeds' yield model [3], the model predicted part's yield to be 61.3%. The actual yield of the part is 68.5%. Therefore, the model prediction error is 10.5% which we believe is a good rst order approximation useful for yield prediction at early design stages. The prediction accuracy may vary with dierent yield models used. For example, with increasing clustering (=4 as suggested in [14]), the predicted yield will be 55.7% which results in an 18.7% error. Table 4: Estimated Yield of Popular Yield Models Estimated Yield Name Pois Murp Seed Moor Ding Average C C499 xxx xxx xxx xxx xxx xxx C C1355 xxx xxx xxx xxx xxx xxx C C2670 xxx xxx xxx xxx xxx xxx C C5315 xxx xxx xxx xxx xxx xxx C C7552 xxx xxx xxx xxx xxx xxx CIR 1 xxx xxx xxx xxx xxx xxx CIR CIR 3 xxx xxx xxx xxx xxx xxx CIR CIR 5 xxx xxx xxx xxx xxx xxx CIR 6 xxx xxx xxx xxx xxx xxx CIR CIR CIR 9 xxx xxx xxx xxx xxx xxx

5 6 CONCLUSION We have proposed a model for early yield prediction, a sensitive area estimation model with minimum circuit parameters has been developed. A rst order chip yield prediction is obtained by utilizing the estimated sensitive area along with a given fabrication line defect statistics. The accuracy of this model is acceptable as a rst order approximation, and shows the possibility of early chip yield estimation. The TSA model depends upon design technology, and design tools including automatic placer, router, compactor as well as defect statistics. For a given design environment, a reasonably accurate TSA model can be obtained. The prediction accuracy of the model could be signicantly lower for a dierent design environment. This dependency is reected by the coef cients c 0, c 1, and c 2 in the model. Furthermore, the number of gates in a digital circuit is often proportional to the number of nets in the circuit and vice versa. Therefore, most of the data points for model t concentrate on the diagonal line of the model space shown in gure 2. The prediction accuracy for circuits whose gate/net ratios are signicantly o the diagonal line in the model space may be signicantly lower. 7 ACKNOWLEGEMENT We would like to acknowledge Hewlett Packard for funding this research, Wes Higaki for research support, Peter Maxwell, Je Rearick and Rob Aitken for technical consulting. We also acknowledge Alvin Jee and Jon Colburn of UCSC for the support of test CAD tools. References [1] J. Cunningham, \The Use and Evaluation of Yield Models in Integrated Circuit Manufacturing," IEEE Transactions on Semiconductor Manufacturing, vol. 3. No. 2, May 1990, pp [2] B. T. Murphy, \Cost{Size Optima of Monolithic Integrated Circuits," Proc. IEEE, vol. 52, December pp [3] R. B. Seeds, \Yield and Cost Analysis of Bipolar LSI," IEEE International Electron Devices Meeting, Washington D.C., October [4] G. E. Moore, \What Level of LSI is Best for You?," Electronics, vol. 43, Febrary pp [5] J. E. Price, \A New Look at Yield of Integrated Circuits," Proc. IEEE (Lett.), vol. 58, August pp [6] A. G. F. Dingwall, \High{Yield{Processed Bipolar LSI Arrays," IEEE International Electron Devices Meeting, Washington D.C., October [7] T. Okabe, M. Nagata and S. Shimada, \Analysis of Yield of Integrated Circuits and New Expression for the Yield," Electrical Engineering in Japan, vol. 92, December pp [8] C. H. Stapper, \Defect Density Distribution for LSI Yield Calculations," IEEE Trans. Electron Devices (corresp.), vol. ED20, July pp [9] S. Domer, S. Foertsch, G. Raskin, \Model for Yield and Manufacturing Prediction on VLSI Designs for Advanced Technologies, Mixed Circuitry, and Memories," IEEE Journal of Solid{ State Circuits, Vol. 30. No. 3, March pp [10] F. J. Ferguson and J. P. Shen, \Extraction and Simulation of Realistic CMOS Faults using Inductive Fault Analysis", International Test Conference, pp [11] R. R. Fritzemeier, C. F. Hawkins, J. M. Soden, \CMOS IC Fault Models, Physical Defect Coverage, and I DDQ Testing," IEEE 1991 CICC Proceedings, pp [12] J. P. Shen and F. J. Ferguson, \Inductive Fault Analysis of MOS Integrated Circuits," IEEE Design and Test, December 1985, pp [13] F. Corsi and C. Morandi, \Inductive fault analysis revisited," IEE Proceedings, G. Vol No. 2, April pp [14] P. C. Maxwell, R. C. Aitken, V. Johansen, I. Chiang, \The Eectiveness of I DDQ, Functional and Scan Tests: How Many Fault Coverages Do we Need?," Proc. of International Test Conference, pp , [15] A. Jee and C. Bazeghi, \Carafe User's Manual Release Alpha.4," University of California, Santa Cruz, UCSCCRL9420, June 13, [16] M. Abramovici, M. Breuer, A. Friedman, \Digital Systems Testing and Testable Design," Computer Science Press, New York, pp

incidence log(fault weight)

incidence log(fault weight) Fault Modeling and Defect Level Projections in Digital ICs J.T. Sousa, F.M. Goncalves, J.P. Teixeira, T.W. Williams INESC/IST, 117 Lisboa CODEX, PORTUGAL IBM, Boulder, Colorado 831-9191, USA Keywords: