A Compact Gate Tunnel Current Model for Nano Scale MOSFET with Sub 1nm Gate Oxide

Transcription

1 A Compact Gate Tunnel Current Model for Nano Scale MOSFT with Sub 1nm Gate Oxide Ashwani Kumar 1, Narottam Chand 2,Vinod Kapoor 1 Department of lectronics and Communication nineerin Department of Computer Science and nineerin National Institute of Technoloy, Hamirpur Hamirpur , India ABSTRACT As the CMOS devices are scaled down to nano domain and below in order to take the advantae of hiher density, hih speed, lower cost etc, ate tunnelin current throuh ate oxide becomes important because of continued reduction of ate dielectric at nanoscale reime. Consequently, accurate analysis of ate tunnelin current is very important especially in context of low power application. In this paper, an efficient analytical model has been developed for channel and source/drain overlap reion ate tunnelin current throuh ultra thin ate oxide n channel MOSFT with inevitable nano scale effect (NS).The results obtained have been compared and contrasted with simulated and reported experimental results for the purpose of validation. The areement found was ood, thus validatin the developed analytical model. The simplicity of the proposed model is suitable enouh to use it for circuit simulator. It is observed that nelectin nanoscale effect may lead to lare error in the calculated ate tunnelin current. The results provide a uideline to the severity of nano scale effects from the point of view of standby power consumption. It is found that temperature, substrate bias and halo dopin has almost neliible effect on ate tunnelin current. The ate tunnelin current variation with ate bias, ate oxide thickness and source/drain overlap reion have also been assessed. Keywords Gate tunnelin current, analytical model, ate dielectrics, non uniform poly ate dopin, MOSFT, frinin field effect and imae chares. 1. Introduction The Advancement of VLSI technoloy has resulted in continuous scalin down of MOS based devices whose feature size in current IC desin has reduced from deep sub micrometer to nano scale domain. As MOS devices quickly approach nano scale domain, the aressive scalin of the ate dielectric is an essential requirement[1]. As the thickness of ate oxide layer decreases, the ate current increases in an exponential manner. This increase in current not only adversely affects the performance of the device but also increases the off state power dissipation of a hihly interated chip. Thus, predictin the ate tunnelin current is important for the development of advanced MOS devices in nano reime. The first principle computation are based upon the self consistent solution of Poison s and Schrodiner equation, ives a valuable insiht into the underlyin physics of the tunnelin mechanism [1] [4]. However, a full solution of above mechanism is hihly computationally intensive and hence 175

2 not feasible within a compact modelin context where hih computational efficiency is required. The ate leakae current caused by carrier tunnelin is believed to be one of the most constrainin limits for continued down scalin of silicon dioxide as a ate dielectric [5]. In ultra short nano scale MOSFTs, the source/drain extension (overlap reion) under poly silicon ate represents a sinificant fraction of the device as they do not scale with the same rate as the ate lenth [6]. The overlap component of the ate tunnelin current dominates over the small ate bias since the ate oxide field is much stroner in the overlap reion as compared to the channel reion. Hence accurate estimation of this ate leakae current component is essential to appreciate the total off state power dissipation. Numerous models have been developed numerically [4], [7] in the past for calculatin the tunnelin current, but this approach is not always practical and is timin consumin. Schueraf et al [8 9] have derived a simple analytical formula to represent direct tunnelin throuh a trapezoidal barrier. However, this model suffers from various limitations such as (i) ate current dies not approach to zero as ate voltae oes to zero and does not fit experimental data at sub 1 V ate bias rane (ii) the assumption of constant effective mass for all eneries is not accurate (iii) non consideration of quantum effects. Lee and Hu [10 11] proposed a semi empirical model by introducin the correction function to Schueraf s analytical model to take care of above mentioned secondary effect. However, this model has not considered the ede direct tunnelin current (DT). In [12], direct tunnelin current expressions have been developed both for channel ate tunnelin current and DT includin poly depletion effect and quantization effect with a four adjustable parameter. This model does not include (i) the non uniform dopant profile in poly ate in vertical direction resulted due to low enery ion implantation, (ii) additional depletion layer at the ate edes due to ate lenth scalin down and (iii) ate oxide barrier lowerin due to imae chares across the Si/SiO 2 interface.these nano scale effects (NS) are inevitable for nano scale devices operatin into deep sub 50 nm reime. Therefore, it is mandatory to include these NS effects in nano scale MOSFT to achieve an accurate estimation of ate tunnelin current. In present work, an effective and compact model has been developed for analyzin the ate tunnelin current of nano scale NMOSFT throuh sub 1nm ate oxide by considerin the NS effect that are difficult to inore at nano scale reime.the rest of the paper is oranized as follows. In Section II, the impact of the inevitable nano scale effect(ns) on ate tunnel current are presented. In Section III, modelin of the ate tunnelin current is established. The device structure and desin used for simulation set up is presented in Section IV. The results obtained are discussed in Section V. Finally, concludin remarks are offered in Section VI. 2. Impact of Nanoscale ffect (NS) on Gate Tunnelin Current This section evaluates the impact of nanoscale effect on ate tunnelin current as these effect are inevitable when MOSFT is driven in nano domain. 2.1 Impact of nonuniform Dopant profile in Poly ate 176

3 It is discussed in [13] that with device scalin low enery implants are prevalent to attain ultra shallow source/drain junctions and to prevent dopant penetration throuh thinner polysilicon ate. As a result the dopant activation anneals are constrained to minimize dopant diffusion throuh ate oxide. This, in turn, can potentially cause a hihly non uniform vertical dopant distribution in poly silicon ate due to limited dopant diffusion. An estimate of the potential drop due to the non uniform raded dopant profile in vertical direction in poly silicon ate has been made in [13]. A similar assessment is bein shown below. A nonuniform distribution of the dopants in poly silicon ate, as a function of position from the top to the ate oxide interface with the correspondin enery band diaram is shown in Fi. 1. nery G ate D opin ( N po ly ) Vertical Distance X 1 X 2 V i F q V p 1 C X X 1 X 2 x Uniform Profile O xide N N poly x 1 p oly x 2 Non uniform Profile Depletion oxide S i Fiure 1. Nonuniform, raded dopant distribution in vertical direction and correspondin band diaram, showin built in electric field ( x ) and potential drop in poly ate reion. Due to the variation of dopant density and carrier concentration, a built in field x exist between two position (x 1 and x 2 ) and thereby leadin to a built in potential V p1 as shown in Fiure 1. Under thermal equilibrium, there is no current flow and the built in field x for an n type poly silicon ate can be expressed as dφ kt 1 dn d x = dx q N d dx (1) kt dn d d φ q N d (2) where φ is the potential, N d the position dependent dopin concentration, q is the electronic chare and T is the temperature. The potential drop ( V p1 ) thus established at the interface can be iven by kt N d, x 1 V p1 = φx1 φ x 2 = ln q N d, x 2 (3) For instance, if N d chanes by two orders of manitude with a constant slope (say from cm 3 to10 20 cm 3 ), the potential drop based on (3) is about V. This is an additional voltae drop across the poly silicon ate as compared to voltae drop of uniform dopin profile at cm 3, even thouh both the profiles have the same dopant concentration at the oxide interface. This additional voltae drop ( V p 1 ) needs to be included in the modelin of the ate leakae current. 177

4 2.2 Impact of Gate Lenth ffect (Frinin Field ffect) on ate The effect of ate lenth on the poly silicon depletion is shown in Fi 2. Subsequently, additional depletion effects arise at the ate edes as the ate lenth scales down due to frinin ate fields. This results in an additional chare ( Q) to the total chare (Q + Q) thereby ivin rise to wider depletion widths and hence additional potential drops for scaled ate lenths. This additional potential drop, needs to be included in the modelin of the ate leakae current, further reduces the control of ate on channel and hence enhances the ate leakae power. L 1 L 2 P o ly ate Deple tio n in ate ed e s P oly a te A = A rea D elp etion C ha re Frin in Fie lds O xide X O xide d 1 X d 2 S i L >> L X < X 1 2 d 1 d 2 D elp etion C ha re Fiure 2: Gate lenth effect on poly depletion, showin that an effective depletion width is wider for the shorter ate lenth Let A denote the trianular area of the additional chare, then the additional potential drop ( V p2 ) [13] due to the sidewall depletion is approximated as 1 A 2 Q qnd ( C / cm ) 2 L (4) S i (5) TF T ox 3 cos π ε T ox F C d = δ ln π TF T 0 x 1 + π T F (6) where L is the ate lenth, C d is the depletion capacitance in the sidewalls[14],ε ox is the permittivity of the silicon dioxide, T F is the thickness of the field oxide, T ox is the thickness of the ate oxide and δ is fittin parameter equal to 0.95 normally. This implies that potential drop increases in inverse proportion to ate lenth (L ) and V p2 is added to reflect further poly depletion for very short ate lenths. 2.3 Impact of Imae Force Barrier Lowerin 178

5 The emission of electron from Si to SiO 2 causes build up of imae chare at the oxide side of the Si SiO 2 interface as carrier approaches the Si SiO 2 interface. The potential associated with these chares reduces the effective barrier heiht. This barrier reduction tends to be rather small compared to the barrier heiht itself. Nevertheless, this barrier reduction is of interest since it depends on the applied voltae and dopin in the semiconductor. The barrier lowerin increases with an increasin external field applied across the oxide and dopin level of the substrate. The imae force induced barrier lowerin is usually small in non deenerate semiconductors, as well as in relatively thick insulator layers. Note that this barrier lowerin is only experienced by a carrier while approachin the interface and will therefore not be noticeable in a capacitance voltae measurement. The band diaram showin the imae force induced barrier lowerin is shown in Fiure 3. J CB C i F φ b φ b _ eff φ J VB V C = F V J HVB n+ Polysilicon Oxide P type Fiure 3: Imae force induced barrier The calculation of the barrier reduction assumes that the chare of an electron close to the oxide semiconductor interface attracts an opposite surface chare, which exactly balances the electron's chare so that the electric field surroundin the electron does not penetrate beyond this surface chare. The time to build up the surface chare and the time to polarize the semiconductor around the movin electron are assumed to be much shorter than the transit time of the electron. This scenario is based on the assumption that there are no mobile or fixed chares around the electron as it approaches the metal semiconductor interface. The electron and the induced surface chares are shown in Fiure Surface Chare Oxide Semiconductor lectron Imae Chare Oxide Semiconductor lectron Fiure 4: lectron chares Fiure 5: Induced surface chares 179

6 It can be shown that the electric field in the semiconductor is identical to that of the carrier itself and another carrier with opposite chare at equal distance but on the opposite side of the interface. This chare is called the imae chare. The difference between the actual surface chares and the imae chare is that the fields in the metal are distinctly different. The imae chare concept is justified on the basis that the electric field lines are perpendicular to the surface of a perfect conductor, so that, in the case of a flat interface, the mirror imae of the field lines provides continuous field lines across the interface. Since the experimental results [5] exhibit a behavior proportional to the square root of the applied oxide field, the classical imae force theory is considered to be valid. Therefore, The reduction in the barrier heiht at the Si SiO 2 interface from Φ b = 3.15 ev by an amount Φ is iven [16,17] by φ = q ox 4 πε ox = qv ox 4 πε T ox ox eff bs 2 3 π ε ox 2 q N φ = 16 (7) Therefore, effective ate oxide barrier becomes φ = φ φ where is the permittivity of b _ eff b SiO 2 and φ b is the oxide barrier heiht without imae force induced barrier lowerin. This is called the imae force induced barrier lowerin effect. Since it modulates the barrier heiht, it also modulates the ate tunnelin current, as the tunnelin exponentially depends on barrier heiht of ate oxide (Φ ox ). 3. Analytical Model for Gate Tunnelin Current In ultra short channel MOSFTs, in addition to ate to channel direct tunnelin current, the source/drain extensions (overlap reions) direct tunnelin current known as ede direct tunnelin current (DT) has been identified as the principal source of off state power dissipation in VLSI chips because source/drain extensions (overlap reions) under polysilicon ate represent a sinificant fraction of the device as they do not scale at the same rate as ate lenth [18]. Therefore, the evaluation of DT is critical for state of the art MOSFTs. Modelin of the direct tunnelin current analytically have been larely based on the WKB approximation [8].The discrepancies that were present in the oriinal WKB approximation [8] has been rectified in [10],[11] by introducin few adjustin parameters. This model is more consistent and covers the entire ate bias rane. The robustness of the model has been verified with experimental and numerical data. In our work, we adopt this model to evaluate the direct tunnelin current from channel and overlap reion in nano scale reime where poly ate dopant non uniformity, ate lenth effects and ate oxide barrier lowerin due to imae chares across the Si/SiO 2 interface can not be inored. In this scheme, the value of α for channel and overlap reion has been used as 0.6 and 0.45 respectively to match the overall best fit with Santaurus simulation and also with the experimental results reported in [12].The T ox refers to the physical oxide thickness and effective mass of the carrier in the oxide has been used as 0.40m o throuh this work. The total ate leakae current is iven by I = I + I + I (8) c so do 180

7 where I c is the ate to channel tunnelin current, I so is the ate to source overlap reion ate tunnelin current and I do is the ate to drain overlap reion tunnelin current. Since drain to source V ds is taken to be zero for simplification, so I can be modified as below I = I c + I ov ; Iov = 2 I so (9) The channel current I c and DT current I ov per micrometer can be written as: I c = J ch x L eff; I ov = J ov xl ov. The L eff =L 2L ov, where L is the total ate lenth, L ov is the overlap ate lenth and L eff is the effective ate lenth The channel current density (J ch ) and overlap current density (J ov ) are modeled as follows. J = AC T (10) ( ch, ov) F ( ch, ov) WKB( ch, ov ) Where A=q 3 /8πΦ b ε ox, C F(ch,ov) is the correction term incorporated in [10],[11] and T WKB(ch,ov) is the modified WKB transmission probability and are modified for channel and overlap reion as follows: α ( ch, ov ) 20 Vox( ch, ov ) φ b V ox ( ch, ov ) V CF ( ch, ov) = exp N (11) DTC ( ch, ov ) φ b φ bo φ b T ox T WKB( ch, ov ) N 3/ 2 V 3/ 2 ox( ch, ov ) 8π 2m oxφ b 1 1 φ b = exp 3 hq ox( ch, ov ) DTC ( ch ) ( V V FB ) ε ox naccv t.ln 1 + exp Tox naccv t forv < 0 = ε ( Ve V th ) ox ninvv t.ln 1 + exp Tox ninvv t forv > 0 (12) (13) 181

8 ε ox V naccv t.ln 1 + exp Tox naccv t forv < 0 N DTC ( ov ) = (14) ε V ox e naccv t.ln 1 + exp Tox naccv t forv > 0 Where α is the fittin parameter dependin upon channel or source/drain overlap tunnelin, φ bo is the Si / SiO 2 barrier heiht (e ev for electron), φ b is the actual tunnelin barrier heiht (e for ev for CB ), n inv and n acc are the swin parameters, V FB represents the flat band voltae, N DTC ( ch, ov ) denotes the density of carrier in channel /overlap reion dependin upon MOSFT biasin condition and V e is the effective ate voltae excludin poly ate non uniformity and ate lenth effect and is equal to ( V V poly ) values of n inv and n acc are t C ) and transmission probability ( T WKB ( ch, ov ) S v (S is the sub threshold swin) and 1 respectively. The default. The correction factor( F ( ch, ov ) ) are different for channel and source/drain overlap reion because both channel and overlap component have different value of V ox( ch, ov ) and N DTC ( ch, ov ) It is because of the fact that overlap reion has almost zero flat band voltae as both SD reion and overlyin poly ate Si are heavily doped n + reions. The N DTC ( ch, ov ) has been iven differently for both reion as above. The ate oxide voltae ( V ox ) for the channel and SD overlap are calculated as follows. Case (i): when V > 0 In this biasin condition MOSFT device, there is a depletion layer in the poly ate thereby causin an additional potential drop across the ate. The SD reion enters into accumulation and substrate reion enters into the week inversion below V and stron inversion beyond V th.therefore both the channel and DT component are present and are comparable. Case (ii): when V < V < 0 FB Here, ate tunnelin current is dominated by the DT where electric field is such that electron are directed from the accumulated poly ate into the overlap reion. On other hand, substrate is in depletion /weak inversion and constitutes neliible tunnelin current. This reion of biasin is primarily responsible for off state power dissipation. Thus, DT plays an important role in the evaluation of off state power dissipation Case (ii): when V < V FB th 182

9 In this reion of operation, substrate oes into accumulation. As a result both current components become comparable. The voltae across the ate oxide for different reion of operation is as follows. V ox ( φ ) ( φ ) V s VFB forv < 0 = Ve s VFB forv > 0 (16) Where φ s is the surface band bendin of the substrate and are calculated for channel and overlap reion dependin upon the biasin condition of the MOSFT device includin the poly non uniformity, ate lenth effects and imae force barrier lowerin. The accurate surface potentials expressions in case of channel in weak inversion/depletion, stron inversion and in accumulation can be taken from [19]. The surface potential in accumulation in the overlap reion has been derived as follows. This expression excludes the effect of minority carrier in the heavily doped overlap reion. ( V V ( ) ) FB ov β ov ov φ s( acc ) = β ov 1 2 v t (17) where βov = γ p v t ; (18) γ = p (19) The 2 ε si qn Poly C ox φ s takes a sin of positive or neative dependin upon the band bendin in the substrate/overlap reion. The ate effective voltae includin the effect of nonuniform dopant distribution in the ate is derived as follows. (20) This equation includes the non uniformity in the ate dopant profile throuh a term and frinin field effect i.e ate lenth effect throuh a term.the φ so, by takin the quantisation effect into account, is iven [20] as follows QM φ = 2 φ + φ V so B s BS (21) 183

10 QM where φ s can be taken from [19] 4. Simulation Set Up Fiure 6 shows the schematic of device structure of N MOSFT used in this study. The deep S/D reion is composed of a heavily doped silicon and a silicide contact. The dopin of the silicon S/D reion is assumed to be very hih, 1x10 20 cm 3, which is close to the solid solubility limit and introduces neliible silicon resistance. The dimension of the silicon S/D reion is taken as 20 nm lon and 50 nm hih. This ives a lare contact area resultin in a small contact resistance. Poly ate S S 1 D 1 D Fiure 6: NMOSFT device structure used in simulation The heavily doped silicon called deep S/D reion extend into the silicon film at both ends and constitute the extended S/D for the device (labeled by S and D in Fi. 6). The lenths of these extended reions at both ends are equal and are denoted by S 1 and D 1. S/D implantation is performed after definin the ate and the oxide spacer. Boron ions were implanted into the channel reion to reduce the leakae current and to keep a low accepter concentration in the non overlapped channel reion.the dopin concentration of the acceptors in silicon channel reion is assumed to be raded due to diffusion of dopant ions from heavily doped S/D reion with a peak value of 1x10 18 cm 3 and 1x10 17 cm 3 near the channel. The halo implantation done around the S/D also reduces short channel effects such as the punch throuh current, DIBL and threshold voltae roll off, for different non overlap lenths. The MOSFT has a 50 nm thick n+ poly Si ate with metallurical ate lenth of 25 nm and a 1 nm ate oxide. The oxide spacer has been assumed to reduce the ate capacitance. Here, Lo represents the overlap lenth, which is controlled by the S/D implantation enery. Lo = 5 nm optimized with off current is used in this work. The MOSFT with L met of 25 nm was desined to have a V T of 0.23 V. We determined V T by usin a linear extrapolation of the 184

11 linear portion of the I DS V GS curve at low drain voltaes. The operatin voltae for the devices is 1V. The simulation study has been conducted in two dimensions, hence all the results are in the units of per unit channel width. MOSFT devices in nano reime are characterized by several aspects typical of the nanometer scale: short channel effects, quantum confinement in the channel, tunnel current throuh the ate dielectric, source to drain tunnel current, inelastic scatterin alon the channel and far from equilibrium transport. From this point of view TCAD models [21] that are adequate to represent the device physics appropriately durin simulation at nano reime are included. There are several model in literature that addresses the problem in different way. Alon the transport direction, however, Santarus ( TCAD simulator) provides the choice of four different transport models: (i) drift diffusion model, (ii) thermodynamic transport model (iii) hydrodynamic transport model and (iv) Quantization models. Amon them driftdiffusion model simulation runs the fasters, however, does not take care of quantum effect for nano devices. Thermodynamic transport (TDT) model is suitable for the simulation of power devices. Hydrodynamic transport (HDT) is especially useful in simulatin devices ranin from deep submicron MOSFTs beyond 0.18µm eneration and hetrostructure. It includes the simulation of non local effects such as velocity overshoots and substrate current levels. Quantization model Density radient transport(dgt) on the other hand has three different models: (i) van Dort model(vd)model, (ii) density radient (DG) model and (iii) modified local density approximation (MLDA) model. They differ in physical sophistication, numeric expense and robustness. The van Dirt model is numerically robust, fast and well describes the terminal characteristics but does not ive correct density distribution in the channel. Density radient (DG) model is numerically robust but sinificantly slower than the van Dort model. It, however, ives reasonable description of the terminal characteristics and chare distribution inside the device and also describe the 2D and 3D quantization effects. The modified local density approximation (MLDA) model is numerically robust and fast model but it sometimes fails to calculate the accurate carrier distribution in the saturation reion because of its one dimensional characteristics. Comparison of some of these transport models can be found elsewhere [21] Scatterin inside the intrinsic device is treated by a simple Brooks Herrin model, which ives a phenomenoloical description of scatterin. This simple model can capture the essential physics realistically. Due to heavy dopin of the extended S/D inside the intrinsic device and due to its raded nature alon the channel, a dopin dependent mobility is expected. For this reason, the Canali model which oriinates from the Cauhey Thomas formula, but has temperature dependent parameters, is used. Thus, the simulation of the device is performed by usin the Santarus desin suite with drift diffusion, density radient correction and advanced physical model bein turned on. 5. Results and Discussion Computation have been carried out for a n channel fully depleted nanoscale MOSFT to estimate the ate tunnelin current due to overlap of source/drain reion with ate area overlap in addition to ate to channel component of ate tunnelin current. The impact of nanoscale effect (NS) on ate leakae current has been evaluated. The source/drain overlap lenth of the nano device under consideration is optimized with reard to off current of the 185

12 device. The variation of ate tunnelin current with source/drain overlap lenth for a iven values of ate bias and oxide thickness has been presented. The variation of ate tunnelin current with temperature and substrate bias for a iven values of ate bias and oxide thickness has, also, been presented. Further, the variation of ate leakae current with ate bias for different value of substrate dopin has been reported in the results. The variation of ate tunnelin current with and without halo dopin is also observed. The comparision between the simulated data and the model value for ate tunnelin current is presented in Fi. 7. for value L met = 25 nm, L ov =10 nm, T ox =1.0 nm. The substrate dopin has been taken to be 1x10 17 cm 3 while that of polysilicon ate is 1x10 22 cm 3 at the top and 1x10 20 cm 3 at bottom of the polysilicon ate i.e. interface of oxide and silicon. The model value while considerin the nano scale effect shows ood areement with the simulated value over the entire positive ate bias rane, certifyin the hih accuracy of the propsed analytical modellin. It is also shown that model value without nano scale effect(ns) does not shows ood areement with simulated value, emphasizin the need of inclusion of nano scale effect. Fiure 7. Comparison of model with simulated data for ate oxide thickness of T ox = 1.0 nm, metallurical ate lenth of L met =25nm and S/D overlap lenth of L ov =10 nm in nano scale reime Similarly, the model is also verified in Fi. 8. with experimental data published in [12] for value L =0.17 µm, L ov =10 nm,t ox =1.85 nm and W =10 µm. The substrate dopin and polysilicon ate dopin has been taken to be 4.1x10 17 cm 3 and 5x10 20 cm 3 respectively. The model value also shows ood areement with the experimental data over the entire ate bias rane, certifyin the hih accuracy of the propsed analytical modellin. 186

13 Fiure 8. Comparison of the model with experimental data for N sub =4.1x10 17 (cm 3 ) and N Poly =5x10 19 cm 3 X T ox =1.0 nm Fiure 9: Gate tunnelin current and Off current vs ate bias for T ox =1.0 nm, N sub = 1x10 17 m 3, L met =25nm and L ov =10 nm in nano scale reime Fiure 9. shows the variation of the ate tunnelin current and off current of the NMOS device with S/D overlap lenth for optimization of S/D overlap lenth at a iven ate bias of 0.6 V and ate oxide thickness of 1.0 nm. It is observed that off current for a device under consideration is slihtly less at S/D overlap lenth of 5 nm. Therefore, S/D overlap lenth of 5.0 nm is considered for the further simulation and model data calculation. 187

14 Fiure 10: Gate tunnelin current vs ate bias for different ate oxide thickness in nano scale reime at L met =25nm and L ov =5.0 nm The I V characteristics for various ate oxide thicknesses are shown in Fi. 10. It can be observed that ate tunnelin current increases exponentially with increase in the ate bias and decreases with increase in ate oxide thickness. This is because electric field responsible for ate tunnelin increases with increases in ate bias and decrease with ate oxide thickness. It can also be seen that for a ate bias of zero volt, the ate tunnelin current shows a drastic reduction. This is because of the fact that the transverse electric filed ets reduced substantially at such an applied ate bias. It is further observed that at hih ate biases, there is a tendency of saturation of ate tunnelin current. Fiure 11: Gate tunnelin current vs S/D overlap lenth for different ate oxide thickness in nano scale reime at V =0.6 V, L met =25nm and L ov =5.0 nm 188

15 In Fiure 11, the scalability of the ate overlap lenth has been presented in context of ate leakae current. The ate leakae shows increasin trend with ate to S/D overlap lenth. Since ate tunnelin current throuh S/D overlap reion is comparable with channel to ate reion current at nano domain, therefore, ate leakae current increases as the area of S/D overlap reion increases because it tends to increase the chare carrier concentration which is responsible for tunnelin. It is desirable to minimize the overlap lenth particularly in those applications where leakae requirements are very restrictive. V = 0.6 V L met = 25 nm L ov = 5.0 nm Fiure 12: Gate tunnelin current vs ate bias for different substrate dopin in nano scale reime at V =0.6 V, T ox = 1.0 nm, L met =25nm and L ov =5.0 nm Another important issue is the effect of the substrate dopin levels on the direct tunnelin currents with respect to the applied ate voltae instead of the oxide voltae drop, which is difficult to determine for ultra thin ate oxide MOS device. Hiher substrate as well as polysilicon dopin levels for modern MOS devices has been used widely and their effects on tunnelin current can not be overlooked. We have calculated the direct tunnelin currents for substrate dopin levels of 1x10 17 cm 3, 5x10 17 cm 3 and 1x10 18 cm 3. The results are shown in Fi. 12. The ate tunnelin current increases as the substrate dopin level decreases for same applied ate voltae and oxide thickness. At lower substrate dopin levels, the formation of an inversion layer requires less ate bias, leadin to a lowered threshold voltae and more electrons in the inversion layer available for tunnelin. In another word, for hihly doped substrate, the substrate band bendin need to become larer in order to form electron inversion layer, implyin less number of tunnelin electron at low ate bias. This trend is more pronounced at low bias conditions, where the tunnelin current for hihly doped substrates is several orders of manitude lower than that of lihtly dopin substrates. At hih bias, the difference between the tunnelin currents becomes smaller. Since the tunnelin currents are mainly determined by the number of available tunnelin electrons, which comes closer in number for different substrate dopin levels at hih bias, the difference between the tunnelin currents is therefore decreased at hih bias. 189

16 Fiure13: Gate tunnelin current vs temperature for different oxide thickness in nano scale reime at V =0.6 V, L met =25nm and L ov =5.0 nm Fi. 13 shows the variation of the ate leakae current with temperature in an NMOS transistor for different ate oxide thickness at a iven ate bias. The ate leakae current is almost insensitive to temperature variation since the electric field across the oxide does not stronly depend upon the temperature. Fiure 14: Gate tunnelin current vs substrate bias for different oxide thickness in nano scale reime at V =0.6 V, L met =25nm and L ov =5.0 nm The application of reverse substrate bias is widely used for reducin subthreshhold leakae in deep sub micron. It is observed in Fi.14 that ate leakae is almost insensitive to substratebias variation and shows same trend for both the profiles. Application of substrate bias only affects the ate to body tunnelin component of ate leakae. However, this component is 190

17 very much less compared to the ate to channel or overlap component of ate leakae. Hence, the net effect of the substrate bias on the ate leakae is neliible. Fiure 15: Gate tunnelin current vs ate bias in nano scale reime for T ox = 1.0nm, V =0.6 V, L met =25nm and L ov =5.0 nm Halo dopin for modern MOS devices has been used widely around the S/D to reduces short channel effects, such as the punch throuh current, DIBL, and threshold voltae roll off and their effect on tunnelin current can not be overlooked. Fi. 15 shows the variation of the ate leakae current with ate bias for a iven oxide thickness of T ox = 1.0 nm with and without halo dopin. The ate leakae current is almost insensitive to halo dopin because carrier concentration in channel reion does not stronly depend upon the halo dopin. 6. Conclusion The simple analytical scheme has been shown to predict the ate tunnelin current in nano scale domain. It is established that the nelience of nano scale effect (NS) while modelin the ate leakae current may lead to serious error especially in application which are sensitive to power requirement. It is shown that the source/drain overlap lenth of the nano device under consideration has been optimized with reard to off current of the device. The scalability of the Source/ Drain overlap reion has to be taken into account particularly in those applications where off state power dissipation is of reat importance. The results indicate that ate leakae current is almost insensitive to temperature variation, substrate bias and halo dopin. 7. References 1. C. H. Choi, K. Y. Nam, Z. Yu, and R. W. Dutton, Impact of ate direct tunnelin current on circuit performance: A simulation study, I Trans. lectron Devices, vol. 48, pp , Dec

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