The challenges of configurable hybrid Memristor-CMOS Integrated circuits fabrication: Physics and Materials Science

Transcription

1 The challenges of configurable hybrid Memristor-CMOS Integrated circuits fabrication: Physics and Materials Science Gilberto Medeiros-Ribeiro HP Labs

2 Outline Context Memristor basics Memristor fabrication and incorporation in reconfigurable logic CMOS Final thoughts 2

3 Data Storage 170%/year Compound Growth rate ( ): 16x Moore s law density increase; 56x increase in storage exabytes of online data 1 Hard disks are cheap, but latency is the bottleneck Flash as a hard disk replacement is on course DRAM roadmap ends in 2015 Need for universal memory! Preferable Non-volatile 1 Physics of data, Marissa Myers, Google 3

4 Why DRAM and Flash are approaching scaling limits? DRAM Capacitors can t get small Transistors leak through the gate Short channel effects S-D leakage FLASH Tunnel oxide can t get thinner Faster degradation 4

5 Non-volatile storage options F=technology node Memory Element Cell size CMOS Integration Switch Mechanism Bipolar /Unipolar Power Scaling Ultimate Scaling Limit Setreset Times Maturity Metal Oxide * 0.5F 2 Excellent E-field Bipolar Good Good Conducting channel size (5nm) Good Lab-tofab PCM *4F 2 Demonstrated Temperature Unipolar Poor Fair Stable nanocrystal size (~10nm) Good Prototyp e Flash *4F 2 Excellent E-field N/A Good Fair Capacitor size Fair Product FeRAM *4F 2 Demonstrated E-field Bipolar Good Poor Domain size (20nm) Good Product MRAM *4F 2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty product 5

6 Non-volatile storage options F=technology node Memory Element Cell size CMOS Integration Switch Mechanism Bipolar /Unipolar Power Scaling Ultimate Scaling Limit Setreset Times Maturity Metal Oxide * 0.5F 2 Excellent E-field Bipolar Good Good Conducting channel size (5nm) Good Lab-tofab PCM *4F 2 Demonstrated Temperature Unipolar Poor Fair Stable nanocrystal size (~10nm) Good Prototyp e Flash *4F 2 Excellent E-field N/A Good Fair Capacitor size Fair Product FeRAM *4F 2 Demonstrated E-field Bipolar Good Poor Domain size (20nm) Good Product MRAM *4F 2 Poor (Fe) B-field Bipolar Poor Poor Domain size (10nm) Good Specialty product 6

7 Memristor x PCRAM: pro s and con s Parameter Memristor PCRAM Operation Bipolar Unipolar 1T/1R Yes Yes X-bar Yes Yes, if incorporates series diode CMOS compatible Yes, for both FEOL and BEOL Maturity Incipient Decades Not FEOL compatible bit size scalability Good (down to 5nm) Uncertain (ok down to 50nm) Retention Good Worsens with decreasing size 7 Copyright 2010 Hewlett-Packard Development Company, L.P.

8 The memristor as the fourth element RESISTOR v = R i CAPACITOR dq = C dv INDUCTOR dφ = L di MEMRISTOR dφ = M dq rigorous definition v ( t) = R[ w, i( t)] i( t) dw ( t) = dt f [ w, i( t)] L. O. Chua, IEEE Trans. Circuit Theory 18, 507 (1971) Quasi-static conduction eq.- R depends on state variable w Dynamical equation: Evolution of state in time

9 What makes the memristor fundamental? Current vs. Sinusoidal Voltage Resistor Time Capacitor Current Voltage Current dv = R di dq = C dv Inductor Memristor Current dφ = L di dφ = M dq Voltage Voltage

10 Simple Phenomenological Description V w Undoped: Doped: Doped D A Undoped R OFF Ionic drift: dw( t) dt = µ V R D ON i( t) Electronic current: w( t) v( t) = RON + ROFF 1 D i w 3 w 2 w 1 t w( t) i( t) D v = M(q(t)) i(t) 0 i = sin[wt] w 3 >>w 2 >>w 1 R ON R ON w/d R OFF (1-w/D) µ ( ) = 1 V M q ROFF R q 2 ON ( t ) D Strukov, Stewart, Snider & Williams, Nature (2008)

11 4 properties of memristive systems in 3 sweeps: a dynamical device 134 Memristive Properties Continuous states Zero-crossing Frequency dependent Bias dependent 2

12 How can one make such a device? Different materials choices, like TiOx, NiOx, CuOx, etc. Metal electrodes 12

13 TiOx: a switching material 3.0/3.2 ev semiconductor dielectric ε ~ 80, birefringent pigment, photocatalyst, O 2 sensors TiO 2 : 1x Ti x O 2- Relatively easy to reduce Vacancy diffusion ~1eV 13

14 MIM devices Metal/oxide/metal junction Metallic nanowire (bottom electrode) Metallic nanowire (top electrode) Switching materials (e.g. TiO 2 ) Typical device fabrication: sputtered deposited films of oxides; e-beam deposition of Pt TEM cross-section Pt top electrode TiO 2 TiO 2-x Pt bottom electrode Ti adhesion layer SiO x Si J. Yang et al., Adv. Mat, (2010)

15 How can one make a memory from this? 15

16 Cross bar concept 16

17 Cross bar concept V - + threshold 0 or 1 Sense amps 17

18 Cross bar concept V/2 -V/2 - + threshold 0 or 1 Sense amps 18

19 Cross bar concept V/2 -V/2 - + threshold 0 or 1 Sense amps 19

20 Cross bar concept V/2 -V/2 = Sense amps threshold 0 or 1 20

21 A memristor X-bar implementation Ability to scale to aggressive technology nodes 50 nm wire width 21

22 Nonlinear devices required! Since the resistance of each device can be a very non linear function of the voltage, this non-linearity and asymmetry can be used in adjacent devices to isolate bits. 10 Current (A) OFF -6 #1-999 cycle # 1000 cycle ON Current (A) Voltage (V) Voltage (V)

23 Putting devices onto a CMOS platform Develop simple models for realistic circuit design Known and well tested CMOS circuitry Match very different technologies Flexible voltage adjustments 23

24 Simple Spice Model for Circuit Verification State of the art model at time of design, a more detailed model exists now. Bench Data provided by HPL Junction IV Characteristics Ion Ioff , E-06 Current (A) , E Voltage (V) Simplified Model Ik = α sinh( β *Vk) State Alpha Beta Avg of RMS error OFF 2.29E E-08 ON 1.73E E-08 Actual device model used for CMOS verification Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp

25 Hard Coded Die Configuration half-adder A in S out start B Q FF D Tim e C in out LSB 0 1 time MSBB In order to mitigate design risk, and speed up test development, CMOS pre-configured 1 1 Q 1 1

26 SNIC Architecture

27 CMOS Integration Challenges Challenges: Unstable process for nanowires Design needed to enable process development Driver circuitry for a dynamical load Different operating voltages Implication: Design had to provide a flexible interface for fab and lab quality imprint tooling Larger than necessary alignment tree Risks Unknown Fab-Lab integration challenges

28 Quartz NIL Molds Bottom Electrode Top Electrode Holey Pad Structure Master mold patterned by EBL. Daughter molds duplicated on QZ using NIL. Nanowires:100 nm HP. Feature height: 60 nm. Pad size: 10 µm by 15 µm. 28

29 CMOS Substrate 3 metal layer CMOS circuits, [0, 3.3V] operation. Chip finished with TEOS and CMP. Fabricated with 0.5 µm technology at HP Corvallis fab in Oregon 29

30 Integrated Hybrid Circuits (c) 100 nm 12 nm Pt 36 nm TiO2 9 nm Pt 2 nm Ti 30

31 Wiring of Logic Gates Using Memristors 31

32 Logic Functions Successfully Implemented NOT gate A C AND gate A B C 1 OR gate A B C 1 32 Reading voltage: 1.7 V. CMOS: 3.3V

33 Logic Functions Successfully Implemented NAND gate A B C 1 NOR gate A B C 1 D Flip-flop D Clk Q Q 33

34 Reconfigurability Demonstrated ON OFF INPUT INPUT OUTPUT Reading voltage: 0.5 V OUTPUT Qiangfei Xia et al, Nano Lett., 2009, 9 (10), pp

35 Main points Scalability: 4F 2 feasible, stacking also feasible CMOS compatible process Low power (not discussed) Non-volatility Faster and more resilient than FLASH, with better scaling perspectives 35

36 Acknowledgements: Julien Borghetti John Paul Strachan Dmitri Strukov Feng Miao Wei Yi Matthew Pickett Douglas Ohlberg Qiangfei Xia Hans Cho Xuema Li Tan Ha Cuong Le Fred Perner Tsung-Wen Lee Mike Cumbie Phil Kuekes Warren Robinett Alexandre Bratkovski Dick Carter Rick Amerson Pascal Vontobel Erik Ordentlich Gadiel Seroussi Wei Wu Max Zhang Hisham Abdahla Shakeel Quresh Greg Snider Janice Nickel Stan Williams Information and quantum Systems Lab: Photonics, CeNSE & Nanoelectronics groups Lab Director: Stan Williams

37 The Questions People Ask Switching voltages/currents (volts/na-100µa) Write/Erase/Read speed and energy (<10ns, pj) ON/OFF ratio (>1000:1) Retention time (years even millennia) Scaling limits (5nm? - >4 terabits/sq cm) Endurance and failure mechanisms (heating) Nature of ON and OFF states (metal/insulator) Devices are evolving rapidly with understanding