EE141-Fall 2009 Digital Integrated Circuits. Inverter Chain. Careful about Optimization Problems. Announcements

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Everett Dorsey
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1 EE-Fall 09 Digital tegrated ircuits verter ha ecture 6 verter Delay Otimization For some given : How many stages are needed to mimize delay? How to size the verters? Anyone want to guess the solution? Announcements ab # Mon., Tues., ab # Fri. Homework # due Thursday Homework # due next Thursday areful about Otimization Problems Get fastest delay if build one very big verter So big that delay is set only by self-loadg ikely not the roblem you re terested Someone has to drive this verter lass Material ast lecture Overview of Semiconductor Memory Today s lecture verter Delay Otimization Readg (.,.) Engeerg Otimization Problems General eed to have a set of constrats onstrats key to: Makg the result useful Makg the roblem have a clean solution For sizg roblem: eed to constra size of first verter 6 6

2 Delay Otimization Problem # You are given: A fixed number of verters The size of the first verter The size of the load that needs to be driven verter with oad P g t Delay Your goal: Mimize the delay of the verter cha eed model for verter delay vs. size g Delay kr ( t / + / ) kr sq,n g [ d / g + /( g )] Delay (ternal) + Delay (oad) oad verter Delay Mimum length devices, 0.09µm Assume that for P aroximately equal resistances, R R P arox. equal rise and fall delays, t H t H Analyze as an R network: R R R R R Delay: P sq, sq, n P t H (ln ) R t H (ln ) R Delay Formula ( + ) Delay ~ R t ( / ) ( γ ) t kr + t + f t v t γ (γ for verter) f / electrical fanout R R sq ( /) ; g t v ln() R sq g oadg on the revious stage: g t v is deendent of sizg of the gate!!! verter Delay P g R Rsq, n Aly to verter ha t d t g t t + t + + t g Relace ln() with k (a constant): Delay kr t + kr Delay kr sq,n (/)( d ) + kr sq,n (/) 9 9 t tv γ +, +, t t t, +, v γ +,, + i,

3 Otimal Taerg for Given Delay equation has - unknowns,,, To mimize the delay, fd - artial derivatives:,, + t... + tv + tv +...,, dt t t 0 d, + v v,,, Examle f f f / has to be evenly distributed across stages: 6 6 Otimal Taerg for Given (cont Result: every stage has equal fanout:,, +,,,,, + (cont d) other words, size of each stage is geometric mean of two neighbors: Equal fanout every stage will have same delay Delay Otimization Problem # You are given: The size of the first verter The size of the load that needs to be driven Your goal: Mimize delay by fdg otimal number and sizes of gates So, need to fd that mimizes: ( γ ) t t + v 7 7 Otimum Delay and umber of Stages hen each stage has same fanout f : f F / Effective fanout of each stage: Mimum ath delay: f F v, ( γ ) t t + F Solvg the Otimization Rewrite terms of fanout/stage f: f ln ( ) ln f (( ) / γ ) ln ( ) f + γ t tv + tv ln f t ln f γ f tv ln ( ) 0 f ln f f ex + ( γ f ) For γ 0, f e, ln ( / )

4 Otimum Effective Fanout f Otimum f for given rocess defed by γ f ex( + γ f ) Buffer Design 6 f t f ot. e f ot.6 for γ γ Practice: Plot of Total Delay hat About Energy (and Area)? [Hodges,.] Ignorg diffusion caacitance: tot + f + + f ( + f + + f ) + f + f ( + f + + f - ) Overhead!!! f(f - -) / (f-) urves very flat for f > Simlest/most common choice: f Examle (γ0): F; i 0fF 6 Fixed: F Overhead:.66F!!! ormalized Delay As a Function of F Examle Overhead umbers Examle: F; 0fF Textbook: age t t ( γ + F), F v (γ ) Overhead aacitance (F) umber of Stages Delay (t v )

5 ext ecture Gate Delay ogical Effort

EE141-Fall Digital Integrated Circuits. Announcements. Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday. Homework #4 due next Thursday

EE141-Fall Digital Integrated Circuits. Announcements. Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday. Homework #4 due next Thursday EE4-Fall 2000 Digital Integrated ircuits Lecture 6 Inverter Delay Optimization Announcements Lab #2 Mon., Lab #3 Fri. Homework #3 due Thursday Homework #4 due next Thursday 2 2 lass Material Last lecture