Design Constraint for Fine Grain Supply Voltage Control LSI
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1 ASP-DAC 211 Designer s Forum Session 8D-3: State-of-The-Art SoCs and Design Methodologies Design Constraint for Fine Grain Suly Voltage Control LSI January 28, 211 Atsuki Inoue Platform Technologies Laboratories Fujitsu Laboratories Ltd. Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
2 Agenda Background Fine grain suly voltage control Energy gain concet Power gating case Various energy losses Results with simle assumtion Modification for actual devices Comarison with simulation results Minimum slee duration time DVFS* case (results only) Summary *DVFS: Dynamic Voltage and Frequency Scaling 1 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
3 General exectation for fine grain suly control User Circuit Control Sensor Power suly unit Suly voltage control LSI Fine Coarse Concet of suly voltage control: Grain size in time domain Collaboration between ower suly unit and user circuit otimizes energy consumtion Power gating and DVFS are tyical controls. Two tyes of grain size Grain size in time domain Grain size in sace domain We will discuss the time domain control in this aer. General exectation Fine grain control will imrove ower efficiency. Grain size in sace domain Fine Coarse Current 2 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
4 Fine grain suly control in time domain (ower gating case) Gating Tr. VDD More frequent controls are exected to reduce leakage ower. OFF Power gating control signal OFF C GND Power domain Virtual ower line Power gating control signal Coarse grain Time OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Power gating control signal Time Fine grain 3 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
5 Energy gain concet to derive design constraint E a Dissiated energy when suly voltage control technique is alied. Energy for circuit oeration itself Energy overhead for changing suly voltage E na Dissiated energy when suly voltage control technique is not alied. Energy for circuit oeration itself Energy gain : n E E na = > a necessary condition Design constraint 4 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
6 Power gating case 5 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
7 Energy losses at ower gating (a) (b) (c) (d) Switching energy of gating transistor Switching energy of isolation gates Storing/restoring energy for internal information Charging/discharging energy of virtual ower line Main ower suly Gating Tr. Virtual ower line (d) C Ground Power domain1 (a) (b) Enable Isolation gate FF (c) Power domain2 Only (d) is deendent of slee duration time (a)-(c) is indeendent of slee duration time. 6 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
8 Start with simle assumtions Start with the following simle assumtions. 1. Leakage current is indeendent on drain voltage. 2. Consider charging energy of virtual ower line only. (Other energy losses (a)-(c) are ignored.) Then we modify the theory excluding these assumtions Power gating control signal V dd Off Slee duration τ On Virtual ower suly voltage gnd τ 1 τ flat τ 2 Time 7 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
9 Energy losses for charging virtual ower line Energy with ower gating : Energy without ower gating : E = E + E + E a E = I V τ = I V ( τ + τ + τ ) na off dd off dd 1 2 flat Main suly Main suly Leakage current Virtual ower line Leakage current Virtual ower line Circuit C E 3 Circuit E 2 E 1 C (a) Discharging hase (b) Charging hase 8 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
10 Minimum slee duration time Case I Virtual ower line voltage Case II V dd gnd τ 1 τ 2 E na = E a Virtual ower line voltage Case III V dd gnd τ 1 τ flat τ2 E na > E a Virtual ower line voltage V dd gnd τ 1 τ 2 Minimum slee duration time: min Time τ = E I na < E a (if other energy losses exist) C V off V dd 9 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
11 Leakage current deendence on drain voltage Actual transistors have DIBL* effects and leakage current does deend on drain voltage. V nv gs λv nv ds V v i i i I ( V ) = Ae e (1 e ), v = Normalized leakage current off ds Drain voltage V ds ds Without DIBL effect With DIBL effect T=3K n=1.39 λ=.9 i kt q DIBL effect term We assume I ( V ) V β off ds ds β = 1 DIBL: Drain Induced Barrier Lowering 1 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved. 2
12 E ov : Other energy loss Other energy loss E ov is indeendent of slee duration time. (a) & (c) are roortional to decouling caacitor C Total load caacitance of ower domain C L is roortional to C due to ower line noise constraint. Caacitance of gating Tr. C x is roortional to C L due to IR dro voltage limitation. Caacitance of storage elements is roortional to total load caacitance C L. (b) is small enough to be ignored for usual cases. C fo ( Circuit) x C f ( GatingTransistor) C C L T v noise α We can assume other energy loss E ov is roortional to C. C x (a) Enable (b) E 2 ov = z* CVdd z = 2% tyical (d) C Power domain C L FF (c) z : Energy overhead factor 11 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
13 Energy gain diagram for ower gating Including other energy loss and non-constant leakage current effect Energy with ower gating : Ea = E1+ E2 + E3 + Eov Energy without ower gating : E = I V τ = I V ( τ + τ + τ ) Energy gain n β = β =1 β =2.56 ~.7 Stronger DIBL Energy gain Energy loss Slee duration time τ / τmin na off dd off dd 1 2 flat z =2% The modified theory redicts: Longer slee time gives higher energy gain. Fleak When τ, 12 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved. n Stronger DIBL effect gives higher gain and shorter minimum slee duration time. τ min = F leak min When β is larger, F leak is smaller. τ =.56 ~.7 (1 < β < 2) (Correction factor)
14 Comarison with simulation results Target circuit : 1.1K gates Energy gain n β = β =1 β =2 technology A technology B Slee duration time τ / τmin z =2% Technology A - I on /I off = 1.2x1 3 τmin = 3.24μs - β~1(weak DIBL) Technology B - I on /I off =1.x1 3 - τmin =.26μs -1<β<2(strong DIBL) τ min = F leak τ min 13 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
15 Which design arameters determines τ min? Minimum duration C Vdd τ min = I ( V ) off dd - Discharging time from V dd to gnd. - It does not deend on ower domain size. Virtual ower line voltage V dd gnd τ min t τ min C I on * * τg C L I gate off Tr. τg : Average gate delay C : Virtual ower line ca. C L : Average load ca. Design deendent Technology deendent 14 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
16 τ min Evaluation of value C C L gate 5 Restriction of suly voltage fluctuation Ex. Activity factor α=25%, ΔV/V dd = 5% α,c L ΔV/V dd C I I on off Tr x1 3x1 1x1 3x1 Assume rocess/temerature coefficient to be 1 *Low standby ower technology τ g 8s 4s τ min 5μs 6μs *Low standby ower technology Relatively long time constant comared with clock cycle time * From ITRS roadma Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
17 Minimum slee cycle number τ min 1 C Ion * * T Ng C L Ioff Tr. gate Ng : cycle Gate number er one ieline stage When Ng = 18 FO4 (Power erformance otimized design*) 4 τ min (3 ~ 8) 1 Tcycle *V. Zyuban et. al., Integrated Analysis of Power and Performance for Pielined Microrocessors, IEEE Trans. On Comuter, , Vol.53, No.6, Aug Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
18 DVFS case (results only) 17 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
19 Minimum DVFS cycles LSI Clock Suly voltage V dd V low Circuits Power management interface V dd gnd Cont. (a) DVFS scheme N cycles Power suly C V in Clock stos by clock gating (b) Non-DVFS sequence N cycles Minimum DVFS cycles exist. α, C L N N > = α : CL C min : : C αc L Activity factor Total load caacitance Total ower line caacitance Clock Suly voltage V dd gnd V low Analysis duration τ (c) DVFS sequence Simle assumtion: Leakage current is ignored and efficiency of ower suly unit is ideal. 18 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
20 Power configuration N min > N = C αc L Regulator LSI V dd V low α C L Power suly LSI V dd V low V dd Power suly α C L Circuit C Circuit (a) External ower suly - Larger C, Larger N min - Higher efficiency of ower suly C (b) On-chi regulator and external ower suly -Smaller C, Smaller N min - Lower efficiency of ower suly 19 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
21 Energy gain diagram for DVFS Energy gain n Gain 1. Vlow x = =.7.8 Vdd.6 k =.3 ηd =.9.4 ηl =.8.2 β = Loss DVFS cycle number N External ower suly C / C = 5 External ower suly +regulator L C / C = 5 L Cycles are required to obtain energy gain larger than unity. 2 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
22 Summary Minimum slee duration Minimum cycle number Correction factor Maximum energy gain Imortant design arameters n Power gating τ min F leak =, when I I = C V I off dd.56 ~.7 on off τ, τ g F leak F N suly min,when DVFS = x+ k 1 n x + k x 2 ( 1 ) N C αc L =.56 ~.86 = 1~ 1. Power suly configuration 2. Efficiency C η dl, 21 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
23 22 Coyright 211 Fujitsu Laboratories Ltd. All Rights Reserved.
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