ECE 497 JS Lecture - 18 Impact of Scaling

Transcription

1 ECE 497 JS Lecture - 18 Impact of Scaling Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1

2 Announcements Thursday April 8 th Speaker: Prof. Umberto Ravaioli - NTRA document updated - Problems using jsa4? 2

3 On-Chip IR Drop Large Voltage Drop Example: VIR=0.78V local supply down by 1.56V:unacceptable Voltage drop across global buses is dependent only on the fraction of metal layer devoted to each bus Remedy Use area bonded chip so that power need not be distributed from chip edge Use more or thicker metal layers Use on-chip bypass capacitors 3

4 Symbiotic Bypass Capacitors On-Chip Bypass Capacitors MOS transistor with source and drain tied together About half the capacitors are symbiotic A M1 C B1 M3 C C1 M5 C D1 M2 C B0 M4 C C0 M6 C D0 50K Gate Module Example Load capacitance C ld =100fF 4,000 gates switching simultaneously 46,000 gates with output loads across power supplies 2.3 nf Adequate to average supply current over a cycle 4

5 On-Chip Bypass Capacitors Area Bonding Flip chip More power distribution to next level of packaging Reduce inductance Helps metal migration problem A capacitor satisfies the relation: C Reduces current load to average value B ki t i av ck > V Thin oxide MOS capacitor: MOS transistor with source and drain tied together C ox = εrεowl t ox 5

6 Integration & Signal Speed Before Today I(t) I(t) current current time time 6

7 Correlation between frequency and physical dimensions In Free Space At 10 KHz : λ= 30 km At 10 GHz : λ = 3 cm Transmission line behavior is prevalent when the structural dimensions of the circuits are comparable to the wavelength. 7

8 Semiconductor Technology Trends Chip size (mm 2 ) Number of transistors (million) Interconnect width (nm) Total interconnect length (km)

9 The Interconnect Bottleneck Delay (ps) SPEED/PERFORMANCE ISSUE Gate Delay Sum of Delays, Al & SiO2 Sum of Delays, Cu & Low K Interconnect Delay, Al & SiO2 Interconnect Delay, Cu & Low K Gate Gate wi Al & SiO2 Al 3.0 µω -cm Cu 1.7 µω -cm SiO2 κ = 4.0 Low κ κ = 2.0 Al & Cu.8µ Thick Al & Cu Line 43µ Long Generation (nm) 9

10 The Interconnect Bottleneck Technology Generation 1.0 um MOSFET Intrinsic Switching Delay ~ 10 ps Response Time ~ 1 ps 0.01 um ~ 1 ps ~ 100 ps 10

11 Transmission Line Model Let d be the largest dimension of a circuit circuit z If d << λ, a lumped model for the circuit can be used λ 11

12 Transmission Line Model circuit z If d λ, or d > λ then use transmission line model λ 12

13 Scaling of Parallel-Plate Waveguide The cutoff frequency is the frequency below which the mode associated with the index m will not propagate in the waveguide. Different modes will have different cutoff frequencies. f c = m 2a µε a ONSET OF HIGHER ORDER MODES IN GHz a dim fc TE1 fc TE2 fc TE3 fc TE4 1 m cm mm mm 150, , , ,000 Scaling of waveguide dimension will shift cutoff frequencies higher 13

14 Parallel-Plate Waveguide y x z PEC PEC µ, ε a Mode m will propagate in the waveguide if the operating frequency f satisfies the condition f > m 2a µε The cutoff frequency f c is defined to be at the onset of propagation f c = m 2a µε 14

15 Lumped Circuit or Transmission Line? Determine frequency or bandwidth of signal RF/Microwave: f= operating frequency Digital: f=0.35/t r Determine the propagation velocity and wavelength Material medium v=c/(ε r ) 1/2 Obtain wavelength λ=v/f Compare wavelenth with feature size If λ>> d, use lumped circuit: L tot = L* length, C tot = C* length If λ 10d or λ<10d, use transmission-line model 15

16 Frequency Dependence of Lumped Circuit Models Level Dimension Frequency Edge rate PCB line 10 in > 55 MHz < 7ns Package 1 in > 400 MHz < 0.9 ns VLSI int* 100 um > 8 GHz < 50 ps * Using RC criterion for distributed effect 16

17 Metallic Conductors σ Area Length Re sist an ce : R R Length = σ Area Package level: W=3 mils R= Ω/mm Submicron level: W=0.25 microns R=422 Ω/mm 17

18 Sheet Resistance of Interconnections R sq. int = ρ int H int H int = W int 3 W int Aluminum WSi 2 Polysilicon (ρ = 3µΩ-cm ) ( ρ=130µω-cm) ( ρ=1000µω-cm) 3.00 µm µm µm µm µm µm

19 Ideal Scaling of MOS Transistors Dimensions (W, L, t gox, X j ) 1/S Substrate doping (N SUB ) S Voltages (V DD, V TN, V TP ) 1/S Current per device (IDS) 1/S Gate capacitance (C g =ε ox WL/t gox ) 1/S Transistor on-resistance 1 Intrinsic gate delay(τ=r tr C g ) 1/S Power-dissipation per gate (P=IV) 1/S 2 Power-delay product per gate (P τ) 1/S 3 Area per device (A=WL) 1/S 2 Power-dissipation density (P/A) 1 S: Scaling factor for device dimensions. 19

20 Scaling of IR Voltage Drops at Power Lines Ideal Improved Parameter scaling Scaling Total chip current S 2 S 2 c S 2 S 2 c Conductor thickness 1/S S Sheet resistance (R int ) S 1/S Number of power planes 1 S Number of power connections 1 SS 2 C Effective resistance S 1/S 3 S 2 C IR voltage drop S 3 S 2 C 1/S Signal-to-noise ratio 1/S 4 S 2 C 1 S: Scaling factor for device dimensions. S C : Scaling factor for chip size 20

21 Scaling of Local Interconnections Parameter Ideal Quasi-Ideal Constant-R Generalized Thickness (Hint) 1/S 1/ S 1/2 1/ S 1/2 1/S H Width (Wint) 1/S 1/S 1/ S 1/2 1/S w Separation (Wsp) 1/S 1/S 1/ S 1/2 1/S sp Insulator thickness 1/S 1/ S 1/2 1/S 1/2 1/S ox Length (lloc) 1/S 1/S 1/S 1/S Resistance (Rint) S S 1/2 1 S w S H /S Capacitance to subst 1/S 1/ S 3/2 1/S S ox /SS w Capacitance between lines 1/S 1/ S 1/2 1/S S ox /SS H RC delay (T) 1 1/ S 1/2 1/S S w S H /S 2 Voltage drop (IR) 1 1/ S 1/2 1/S S w S H /S 2 Current density (J) S S 1/2 1 S w S H /S S: Scaling factor for device dimensions. 21

22 Scaling of Global Interconnections Ideal Constant Constant Generalized Parameter Scaling Dimension Delay Scaling Thickness (H int ) 1/S 1 S C 1/S H Width (W int ) 1/S 1 S C 1/S w Separation (W sp ) 1/S 1 1/S 1/2 1/S sp Insulator thickness (t ox ) 1/S 1 S C 1/S ox Length (l int ) S C S C S C S C Resistance (R int ) S 2 S C S C 1/S C S w S H S C Capacitance (C int ) S C S C S C ~S C RC delay (T) S 2 S 2 C S 2 C 1 S w S H S 2 C S: Scaling factor for device dimensions. S C : Scaling factor for chip size 22

23 Optimal Chip Size Delay Factor On-chip delay is usually kept much smaller than chip-to-chip delay Choose chip delay to be 10% of chip-to-chip delay Optimal If the chips are made larger, the system will become slower If the chips are made smaller, the complexity of the package will increase A chip = RC C A /2+ C o o 0.16 ln RchipC chip C o pack package L Achip : Area of chip Apackage : Area of package 23

24 Scaling of Interconnection Capacitance Wiring Capacitance vs Device Capacitance Wiring capacitance becomes more important Transistor input capacitance decreases with reduced size Capacitance of chip-to-chip wire is an order of magnitude larger than on-chip capacitance + + M1 M3 V in V int V out M2 C int M4 24

25 Scaling of Interconnection Capacitance T50% = Rtr ( Cint + Cgate) R tr 1 W C gox ( V DD V T ) L µ 1 C gate WL n n + WL p p = εox 1/ t gox S C W l = ε S inxt int int ox C tox 25

26 Scaling of Local and Global Interconnections Cross sectional dimensions (W int, H int, W sp, t ox ) 1/S Resistance per unit length S 2 Capacitane per unit length 1 RC constant per init length S 2 Local interconnection length (l loc ) 1/S Local interconnection RC delay 1 Die size (D c ) Global interconnection length (l int ) Global interconnection RC delay S 2 S 2 C Transmission line time of flight (l int /v c ) S C S C S C S: Scaling factor for device dimensions. S C : Scaling factor for chip size 26

27 Effect of Scaling on Signal-to-Noise Ratio S/N ratio is reduced by: 4 3 SS C This is an alarming ratio Severity is reduced by Off-chip wires have larger inductance Their current demand does not increase as fast Their large size allow easy decoupling In general off-chip transients are slower TAB and flip-chip technology can improve 27