Towards Eyes for Sensor Network Systems
|
|
- Catherine Hunt
- 5 years ago
- Views:
Transcription
1 Towards Eyes for Sensor Network Systems Andreas G. Andreou Electrical and Computer Engineering and Whitaker Biomedical Engineering Institute Johns Hopkins University
2 outline Ears for sensor network systems: a brief detour Introduction Light, photons, noise, bandwidth Current signal processing and translinear networks Systems Polarization contrast chip Spatial-temporal processing Ego-motion compensation chip in a balloon observatory Network architecture for distributed feature extraction. Conclusions 2
3 smart microphone project 4 chamber acoustic horn Cross-Correlation ASIC Gradient Flow ASIC Auto-Correlation Wake-Up ASIC Power Strobe Circuit 4 MEMs Microphones 3
4 and some related papers P. Julian, A.G. Andreou, P. Mandolesi, D. Goldberg, A low-power CMOS integrated circuit for bearing estimation, Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, (ISCAS 2003), Bangkok, Thailand, Vol. 5, pp , May P. Julian, A.G. Andreou, L. Riddle, S. Shamma, G. Cauwenberghs, A comparative study of sound localization algorithms for energy aware sensor network nodes, IEEE Transactions on Circuits and Systems: Part II: Analog and Digital Signal Processing, to appear, D. Goldberg, A.G. Andreou, et.al., A wake-up detector for an acoustic surveillance sensor network: algorithm and VLSI implementation, submitted to IPSN-04. M. Stanacevic and G. Cauwenberghs, ``Micro-power mixed-signal acoustic localizer,'' in Proc. European Solid State Circuits Conf. (ESSCIRC 2003), Estoril, Portugal, September
5 what did we learn? COTS can take you up to a point. DSP and FPGA also take you up to a point, custom analog or digital design is necessary. Event based, one bit digital processing. Interfaces are critical! necessity for system level design- Algorithm exploration is necessary with real data and the actual application environment. Wireless data communication is expensive; do the computation locally if you can! Analog subthreshold CMOS works well if designed properly! 5
6 the energy cost of bits in wires and wireless- CCxxxx: Chipcon Datasheets UWB: 03267r6P802-15_TG3a Multi-band-OFDM-CFP Presentation 6
7 the not-so-state-of-the-art not-eye CrossBow MTS310CASensorBoard 13 nj per bit of light data NOT informationhttp:// Clairex CdSe photoconductor ~ 2 mw power (light ON) ~ 47 uw power (light OFF) ~ 10 khz bandwidth 5 Volts power supply (signal) 10 bits ADC, 15 KS/s 7
8 eyes for sensor network systems Eyes: sensory structures capable of spatial vision, i.e. imaging the environment, no matter how crude the image is Is there something interesting in the environment? in a specific class of objects Where is it? What is it? Land and Nilsson, Animal Eyes often it is about a few bits in the right place at the right time 8
9 the way natural eyes see Continuous sensing Polarization sensitivity Contrast sensitivity Local gain control Spatial filtering Temporal filtering Sampling on demand 9
10 light, photons, photon shot-noise, bandwidth 10
11 analog, digital and all that CVDT Continuous-Value Discrete-Time Continuous-Value Continuous-Time CVCT CCD Switched Capacitor Linear and non-linear analog Binary digital Multivalue digital Asynchronous digital Neuron spikes Anisochronous Pulse Time Modulation DVDT Discrete-Value Discrete-Time Discrete-Value Continuous-Time DVCT 11
12 subthreshold CMOS Current is exponential function of the terminal voltages Vs, Vb, Vg, Vd Large dynamic range High gain (transconductance) Low saturation voltage Vdsat ~100mV Lossless channel and source/drain symmetry (diffusive networks) Zero conductance control node (gate); possibility of floating gate for long term charge storage Mobility considerations Frequency limitations f T = g 2πC µ V πl m t max 2 1µ m 100MHz 0.25µ m 1.6GHz 12
13 subthreshold MOS and bipolar characteristics κ nv GB V SB V DB ID IDS = SIn0 exp exp exp Vt Vt Vt κ pvgb V SB V DB ID ISD = SIp0 exp exp exp Vt Vt Vt I C = I S exp V BE V t = I S exp V B V E V t 13
14 symmetric MOS model DIFFUSION 2 2 W 1 QS kt 1 QD kt I IQ I S Q = µ + Q D S + QD L 2 Cox Cd ep q 2 Cox Cdep q + + I F V, V F V, V ( ) ( ) SD GB SB GB DB DRIFT ( ) ( ) ( ) I G V H V H V SD GB SB DB 14
15 non-linear CMOS resistors and translinear grids Linear conductances V r V P = G 1 I P V r V Q = G 1 I Q I PQ = G 1 I Q I P G 2 ( ) V P V Q = G 2 I PQ NMOS only diffusor/conveyor S h κ nvc κ nv r I = exp I I S v V T ( ) P Q Q P A.G. Andreou and K.A. Boahen, Translinear circuits in subthreshold CMOS, Journal of Analog Integrated Circuits and Signal Processing, Vol. 9, pp , March
16 1D spatial averaging network I j = I j + S h S v exp κ n v C κ n v r ( ) 2 I j I i I k ( ) Inputs: d 2 I dx 2 2I j I i I k I i, I j, I k, I (x) Outputs: Normalizing inter-node distances to unity we write the above on the continuum where I i, I j, I k, I(x) At node V j : I j = I ij I jk + I j Find the smooth function I(x) that best fits the data I(x) with the minimum energy in its first derivative. λ 2 d I 2 I ( x) = I( x) + λ dx The reqularization parameter cost associated with energy in the derivative relative to the squared error of the fit to the data 16
17 sensor level processing: what and where X Computational Circuits Row Select PIXEL Amplifiers Y Computational Circuits Pixel: transduction amplification gain control quantization non-uniformity correction spatial filtering temporal filtering Periphery: ego-motion moments global contrast data-communication Column Select 17
18 seeing in ways that we can t! Mantis Shrimp L.B. Wolff and A.G. Andreou, Polarization camera sensors, Image and Vision Computing, Vol. 13, No. 6, pp , August
19 doing things in front of the pixel: micropolarizers A.G. Andreou and Z.K. Kalayjian, Polarization imaging: principles and integrated polarimeters, IEEE Sensors Z. Kalayjian and A.G. Andreou, Integrated Journal, Vol. 2, No. 6, pp , December imaging linear polarimeter," ISA Transactions, Vol. 38, pp ,
20 current-mode translinear processing PC = T R T R + T R T R T R T R 20
21 sensor level processing: what and where X Computational Circuits Row Select PIXEL Amplifiers Y Computational Circuits Pixel: transduction amplification gain control quantization non-uniformity correction spatial filtering temporal filtering Periphery: ego-motion moments global contrast data-communication Column Select 21
22 spatial/temporal filter Moving t Scanning Temporal Filtering Spatial Filtering Detection Buffering / Amplification 33 x 30 pixels 0.5 micron linear capacitor triple metal CMOS 50 micron cell pitch (2 x 2 mm die) 22
23 sensor level processing: what and where X Computational Circuits Row Select PIXEL Amplifiers Y Computational Circuits Pixel: transduction amplification gain control quantization non-uniformity correction spatial filtering temporal filtering Periphery: ego-motion moments global contrast data-communication Column Select 23
24 doing things in the sides A.G. Andreou, R.C. Meitzler, K. Strohbehn and K.A. Boahen, Analog VLSI neuromorphic image acquisition and pre-processing systems, Neural Networks, Vol. 8, No. 7-8, pp ,
25 Flare Genesis Observatory Balloon based observatory Truly autonomous low bit rate link - A three stage hierarchical system of sun orientation and tracking Two Eyes for finding the sun and motion stabilization + Kodak Megaplus CCD camera Solar power; command and control power budget ~1W 25
26 networks of nodes.constraints. Image sensor constraints (1280x1024 pixels, 24 bit/pixel, frames/s) Rates Data rate (Mbits/s) Distance (m) Energy per bit (pj) Latency (ms) Scanned 24, x (bits/frame) 0.1 (frame rate) Anisochronous event based variable (pixel) RF link constraints Rates Data rate (Mbits/s) Distance (m) Energy per bit (nj) Latency (ms) UWB (Multiband OFDM) COTS (Chipcon 24xx) s 26
27 analog, digital and all that CVDT Continuous-Value Discrete-Time Continuous-Value Continuous-Time CVCT CCD Switched Capacitor Linear and non-linear analog Binary digital Multivalue digital Asynchronous digital Neuron spikes Anisochronous Pulse Time Modulation DVDT Discrete-Value Discrete-Time Discrete-Value Continuous-Time DVCT 27
28 event based systems X Computational Circuits Row Select PIXEL Amplifiers Y Computational Circuits Pixel: transduction amplification gain control quantization non-uniformity correction spatial filtering temporal filtering Periphery: ego-motion moments global contrast data-communication Column Select 28
29 digital event based imager 29
30 high slew rate gain at low energy costs 30
31 the network is the architecture Encoder Decoder Local Processor Communication Processor ALL COMPUTATION DONE ON THE ADDRESSES OF THE EVENTS 31
32 distributed network processing Information is encoded in a stream of events, the address of each pixel node Address Event Representation Asynchronous on demand Programmable communication processors transform and route the events Local Processors perform spatial/temporal integration and normalization Point-to-point and broadcast links provide high speed interconnects 32
33 simulation 33
34 feature extraction through projective fields Think of computation as part of the MAC layer D.H. Goldberg, G.C. Cauwenberghs and A.G. Andreou, Probabilistic synaptic weighting in a reconfigurable network of VLSI integrate-and-fire neurons, Neural Networks, Vol. 14, No. 6-7, pp , July
35 results Input Rectifed Laplacian (Matlab) PrAER chip PrAER (Matlab) 35
36 and something about biology: blow-fly photoreceptor P.A. Abshire and A.G. Andreou, Capacity and energy cost of information in biological and silicon photoreceptors," Proceedings of the IEEE, Vol. 89, No. 7, pp , July
37 some final thoughts One size perhaps does not fit all! With multiple interacting points of view, is worth revisiting polarization vision. Asynchronous on demand systems may be preferable to random access or scanned for giving information to the question: is there anything of interest out there? CMOS imagers can be cheap and can be designed to specific applications; 0.5 micron CMOS may be a sweet spot for garden variety eyes. Increased physical complexity; more than just visible; large area sensor devices conformal to non planar surfaces. What good are eyes without optics or when they can t move?. Good questions! eye designers have plenty things to do. 37
38 acknowledgments: DARPA N C-0315 Acoustic Microsensors NSF-ECS : Microscale adaptive optical wavefront correction NSF-EIA : A comparative study of information processing in biological and bio-inspired systems: performance criteria, resources tradeoffs and fundamental limits. NVSED Smart focal planes Philippe Pouliquen Rich Meitzler Zaven Kalayjian Pamela Abshire Kwabena Boahen Marc Cohen Bernabe Linares Barranco Teresa Serrano Kim Strohbehn Larry Riddle Gert Cauwenberghs David Goldberg Pedro Julian Pablo Mandolesi Eugenio Culurciello 38
39 subthreshold CMOS challenges: noise 39
40 energy costs per pixel P: power ( Watts) ξ : pixel activity factor N : number of pixels N : number of pixels in the computational kernel I ker nel bg : mean photocurrent ( A) I : computational branch current ( typically na) comp V = V : phototransduction branch voltage ( typically (0.3) = 0.3 Volts) pd scale V = V + V : computational branch voltage ( typically ( ) = 0.5 Volts) comp scale sat Bandwidth scales linearly with computational branch current Power will scale linearly with computational branch voltage 40
41 Transduction and Dynamic Range Compression (I): Temporal Delbruck and Mead Average signal in time and store the state -range- on a quasi floating gate (Vfb) 2. Employ negative feedback to position the DC operating point. 3. Amplifier-computational branch-: single stage biased in substhreshold (100nA) P = ( ξ I V + I V ) N bg pd comp comp ( ) = W per pixel 41
42 Non-Uniformity Correction Using FGMOS An MOS mirror with FGMOS transistor (M2) injected using impact ionization (tunneling will work as well). NO power cost during operation. Technique can be applied to both current mode and voltage mode pixels Energy cost only with initial calibration Calibration takes ~2000 iterations for all pixels on the chip and each pixel takes about 1sec Cohen & Cauwenberghs 2001 E = P T = N ( I V + I V ) T adapt in pd out comp = ( ) 1 = 10 7 Joules per pixel 42
43 Transduction and Dynamic Range Compression (I): Spatial -network based- 1. Average using a shunting network 2. Employ negative feedback and log-antilog amplifier to do the ratio computation 3. Note! kernel size does not matter as we normalize everything to the computational current and this gets steered from one pixel to the other. 4. Compression function not tanh but something that can be synthesized in CM circuits! Vnw Ih Vdd VIu Vdd Vnw R H Vnw Iin Iout Vhh V s = 0.6nA, 1.8nA n =1.2 I S = 1.5nA,3nA Vcc Vnw Boahen and Andreou 92 Vpx Vln I I I I P= ( ξ I V + I V ) N out comp in bg bg pd comp comp V V s = I n I n + I s n 43
44 Center-ON-OFF surround with local competition and rectification V ni C 0 60 C 60 V li C +120 I +120 I +60 C +60 Cauwenberghs and Waskiewicz 1999 C C 120 C 0 I 0 I I C I C +0 N eighbour same-orientation inhibition C C I 120 I 60 I + 60 I Local different-orientation inhibition C 0 V r I I 60 C 60 I I I +0 I 120 C An alternative to resistive grids we can explicitely compute the Laplacian using simple scaled mirrors and summing the currents. 2. Added local wiring complexity Normalized-intensity gradient computation Rectification C = I I + I I α C + C β C + C + C + C P = ( ξ 4 IcompVcomp ) N 8 7 (4 10 1) = 10 W per pixel 44
Neuromorphic architectures: challenges and opportunites in the years to come
Neuromorphic architectures: challenges and opportunites in the years to come Andreas G. Andreou andreou@jhu.edu Electrical and Computer Engineering Center for Language and Speech Processing Johns Hopkins
More informationMOS Transistors Models
MOS Transistors Models Andreas G. Andreou Pedro Julian Electrical and Computer Engineering Johns Hopkins University http://andreoulab.net The MOS transistor Levels of Abstraction- Model Equations If V
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationLearning on Silicon: Overview
Learning on Silicon: Overview Gert Cauwenberghs Johns Hopkins University gert@jhu.edu 520.776 Learning on Silicon http://bach.ece.jhu.edu/gert/courses/776 Learning on Silicon: Overview Adaptive Microsystems
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationEE105 - Fall 2006 Microelectronic Devices and Circuits
EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM
More informationLecture 11: MOS Transistor
Lecture 11: MOS Transistor Prof. Niknejad Lecture Outline Review: MOS Capacitors Regions MOS Capacitors (3.8 3.9) CV Curve Threshold Voltage MOS Transistors (4.1 4.3): Overview Cross-section and layout
More informationPractice 3: Semiconductors
Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given
More informationScaling of MOS Circuits. 4. International Technology Roadmap for Semiconductors (ITRS) 6. Scaling factors for device parameters
1 Scaling of MOS Circuits CONTENTS 1. What is scaling?. Why scaling? 3. Figure(s) of Merit (FoM) for scaling 4. International Technology Roadmap for Semiconductors (ITRS) 5. Scaling models 6. Scaling factors
More informationJ. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C. A. Mead California Institute of Technology Pasadena, CA 91125
WINNER-TAKE-ALL NETWORKS OF O(N) COMPLEXITY J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C. A. Mead California Institute of Technology Pasadena, CA 91125 ABSTRACT We have designed, fabricated, and tested
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationMixed Analog-Digital VLSI Circuits & Systems Laboratory
CORNELL U N I V E R S I T Y School of Electrical and Computer Engineering Mixed Analog-Digital VLSI Circuits & Systems Laboratory Our research presently revolves around two major themes: Devising new circuit
More informationEE105 - Fall 2005 Microelectronic Devices and Circuits
EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationChoice of V t and Gate Doping Type
Choice of V t and Gate Doping Type To make circuit design easier, it is routine to set V t at a small positive value, e.g., 0.4 V, so that, at V g = 0, the transistor does not have an inversion layer and
More informationIntegrated Circuit Implementation of a Compact Discrete-Time Chaos Generator
Analog Integrated Circuits and Signal Processing, 46, 275 280, 2006 c 2006 Springer Science + Business Media, Inc. Manufactured in The Netherlands. Integrated Circuit Implementation of a Compact Discrete-Time
More informationElectronic Circuits Summary
Electronic Circuits Summary Andreas Biri, D-ITET 6.06.4 Constants (@300K) ε 0 = 8.854 0 F m m 0 = 9. 0 3 kg k =.38 0 3 J K = 8.67 0 5 ev/k kt q = 0.059 V, q kt = 38.6, kt = 5.9 mev V Small Signal Equivalent
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. Power Consumption in Digital Circuits. Pietro Mercati
CSE140L: Components and Design Techniques for Digital Systems Lab Power Consumption in Digital Circuits Pietro Mercati 1 About the final Friday 09/02 at 11.30am in WLH2204 ~2hrs exam including (but not
More informationLecture 5: CMOS Transistor Theory
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics
More informationThe Devices: MOS Transistors
The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More informationLow-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement
Low-Noise Sigma-Delta Capacitance-to-Digital Converter for Sub-pF Capacitive Sensors with Integrated Dielectric Loss Measurement Markus Bingesser austriamicrosystems AG Rietstrasse 4, 864 Rapperswil, Switzerland
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationCMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors
CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier
More informationLecture 11: MOSFET Modeling
Digital Integrated Circuits (83-313) Lecture 11: MOSFET ing Semester B, 2016-17 Lecturer: Dr. Adam Teman TAs: Itamar Levi, Robert Giterman 18 June 2017 Disclaimer: This course was prepared, in its entirety,
More informationSWITCHED CAPACITOR AMPLIFIERS
SWITCHED CAPACITOR AMPLIFIERS AO 0V 4. AO 0V 4.2 i Q AO 0V 4.3 Q AO 0V 4.4 Q i AO 0V 4.5 AO 0V 4.6 i Q AO 0V 4.7 Q AO 0V 4.8 i Q AO 0V 4.9 Simple amplifier First approach: A 0 = infinite. C : V C = V s
More informationE18 DR. Giorgio Mussi 14/12/2018
POLITECNICO DI MILANO MSC COURSE - MEMS AND MICROSENSORS - 2018/2019 E18 DR Giorgio Mussi 14/12/2018 In this class we will define and discuss an important parameter to characterize the performance of an
More informationSwitching circuits: basics and switching speed
ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V
More informationLecture 3: CMOS Transistor Theory
Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors
More informationDEPFET sensors development for the Pixel Detector of BELLE II
DEPFET sensors development for the Pixel Detector of BELLE II 13 th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD13) 7 10 October 2013, Siena, Italy Paola Avella for the DEPFET collaboration
More informationAnalysis of Transconductances in Deep Submicron CMOS with EKV 3.0
MOS Models & Parameter Extraction Workgroup Arbeitskreis MOS Modelle & Parameterextraktion XFAB, Erfurt, Germany, October 2, 2002 Analysis of Transconductances in Deep Submicron CMOS with EKV 3.0 Matthias
More informationHow we wanted to revolutionize X-ray radiography, and how we then "accidentally" discovered single-photon CMOS imaging
How we wanted to revolutionize X-ray radiography, and how we then "accidentally" discovered single-photon CMOS imaging Stanford University EE Computer Systems Colloquium February 23 rd, 2011 EE380 Peter
More informationVLSI Design The MOS Transistor
VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationECE 523/421 - Analog Electronics University of New Mexico Solutions Homework 3
ECE 523/42 - Analog Electronics University of New Mexico Solutions Homework 3 Problem 7.90 Show that when ro is taken into account, the voltage gain of the source follower becomes G v v o v sig R L r o
More informationSwitched-Capacitor Circuits David Johns and Ken Martin University of Toronto
Switched-Capacitor Circuits David Johns and Ken Martin University of Toronto (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) University of Toronto 1 of 60 Basic Building Blocks Opamps Ideal opamps usually
More informationIntroduction to Digital Signal Processing
Introduction to Digital Signal Processing What is DSP? DSP, or Digital Signal Processing, as the term suggests, is the processing of signals by digital means. A signal in this context can mean a number
More informationVery Wide Range Tunable CMOS/Bipolar Current Mirrors with Voltage Clamped Input
Very Wide Range Tunable CMOS/Bipolar Current Mirrors with Voltage Clamped Input Teresa Serrano-Gotarredona, Bernabé Linares-Barranco, and Andreas G. Andreou National Microelectronics Center (CNM), Ed.
More informationMicroelectronics Main CMOS design rules & basic circuits
GBM8320 Dispositifs médicaux intelligents Microelectronics Main CMOS design rules & basic circuits Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim mohamad.sawan@polymtl.ca M5418 6 & 7 September
More informationLecture 4: CMOS Transistor Theory
Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q
More informationIntegrated Circuits & Systems
Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated
More informationLecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995
Lecture 34: Portable Systems Technology Background Professor Randy H. Katz Computer Science 252 Fall 1995 RHK.F95 1 Technology Trends: Microprocessor Capacity 100000000 10000000 Pentium Transistors 1000000
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationLecture 5: DC & Transient Response
Lecture 5: DC & Transient Response Outline q Pass Transistors q DC Response q Logic Levels and Noise Margins q Transient Response q RC Delay Models q Delay Estimation 2 Activity 1) If the width of a transistor
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationPiecewise Nonlinear Approach to the Implementation of Nonlinear Current Transfer Functions
1 Piecewise Nonlinear Approach to the Implementation of Nonlinear Current Transfer Functions Chunyan Wang Abstract A piecewise nonlinear approach to the nonlinear circuit design has been proposed in this
More informationFundamentals of the Metal Oxide Semiconductor Field-Effect Transistor
Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the
More informationQ. 1 Q. 25 carry one mark each.
GATE 5 SET- ELECTRONICS AND COMMUNICATION ENGINEERING - EC Q. Q. 5 carry one mark each. Q. The bilateral Laplace transform of a function is if a t b f() t = otherwise (A) a b s (B) s e ( a b) s (C) e as
More informationGrasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits
E = B; H = J + D D = ρ ; B = 0 D = ρ ; B = 0 Yehia Massoud ECE Department Rice University Grasping The Deep Sub-Micron Challenge in POWERFUL Integrated Circuits ECE Affiliates 10/8/2003 Background: Integrated
More informationOutline. Neural dynamics with log-domain integrator circuits. Where it began Biophysics of membrane channels
Outline Neural dynamics with log-domain integrator circuits Giacomo Indiveri Neuromorphic Cognitive Systems group Institute of Neuroinformatics niversity of Zurich and ETH Zurich Dynamics of Multi-function
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationEECS240 Spring Today s Lecture. Lecture 2: CMOS Technology and Passive Devices. Lingkai Kong EECS. EE240 CMOS Technology
EECS240 Spring 2013 Lecture 2: CMOS Technology and Passive Devices Lingkai Kong EECS Today s Lecture EE240 CMOS Technology Passive devices Motivation Resistors Capacitors (Inductors) Next time: MOS transistor
More informationLecture 25. Dealing with Interconnect and Timing. Digital Integrated Circuits Interconnect
Lecture 25 Dealing with Interconnect and Timing Administrivia Projects will be graded by next week Project phase 3 will be announced next Tu.» Will be homework-like» Report will be combined poster Today
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationLecture 4: DC & Transient Response
Introduction to CMOS VLSI Design Lecture 4: DC & Transient Response David Harris Harvey Mudd College Spring 004 Outline DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Slide
More informationNPSAT1 Solar Cell Measurement System
NPSAT1 Solar Cell Measurement System Presented by Captain John Salmon, USMC Space Systems Academic Group 777 Dyer Rd., Bldg. 233 Code (SP/Sd), Rm. 125 Monterey, CA 93943 (831) 656-7521 Topics NPSAT1 Overview
More informationExtremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors
Extremely small differential non-linearity in a DMOS capacitor based cyclic ADC for CMOS image sensors Zhiheng Wei 1a), Keita Yasutomi ) and Shoji Kawahito b) 1 Graduate School of Science and Technology,
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationMark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions
Lecture Slides Intro Number Systems Logic Functions EE 0 in Context EE 0 EE 20L Logic Design Fundamentals Logic Design, CAD Tools, Lab tools, Project EE 357 EE 457 Computer Architecture Using the logic
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 15: March 15, 2018 Euler Paths, Energy Basics and Optimization Midterm! Midterm " Mean: 89.7 " Standard Dev: 8.12 2 Lecture Outline! Euler
More informationLast Name _Di Tredici_ Given Name _Venere_ ID Number
Last Name _Di Tredici_ Given Name _Venere_ ID Number 0180713 Question n. 1 Discuss noise in MEMS accelerometers, indicating the different physical sources and which design parameters you can act on (with
More informationAnnouncements. EE141- Fall 2002 Lecture 7. MOS Capacitances Inverter Delay Power
- Fall 2002 Lecture 7 MOS Capacitances Inverter Delay Power Announcements Wednesday 12-3pm lab cancelled Lab 4 this week Homework 2 due today at 5pm Homework 3 posted tonight Today s lecture MOS capacitances
More informationE40M Review - Part 1
E40M Review Part 1 Topics in Part 1 (Today): KCL, KVL, Power Devices: V and I sources, R Nodal Analysis. Superposition Devices: Diodes, C, L Time Domain Diode, C, L Circuits Topics in Part 2 (Wed): MOSFETs,
More informationCase Studies of Logical Computation on Stochastic Bit Streams
Case Studies of Logical Computation on Stochastic Bit Streams Peng Li 1, Weikang Qian 2, David J. Lilja 1, Kia Bazargan 1, and Marc D. Riedel 1 1 Electrical and Computer Engineering, University of Minnesota,
More informationOPTI510R: Photonics. Khanh Kieu College of Optical Sciences, University of Arizona Meinel building R.626
OPTI510R: Photonics Khanh Kieu College of Optical Sciences, University of Arizona kkieu@optics.arizona.edu Meinel building R.626 Announcements Homework #6 is assigned, due May 1 st Final exam May 8, 10:30-12:30pm
More informationAddressing Challenges in Neuromorphic Computing with Memristive Synapses
Addressing Challenges in Neuromorphic Computing with Memristive Synapses Vishal Saxena 1, Xinyu Wu 1 and Maria Mitkova 2 1 Analog Mixed-Signal and Photonic IC (AMPIC) Lab 2 Nanoionic Materials and Devices
More informationNEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES
NEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES KAUSHIK ROY ABHRONIL SENGUPTA, KARTHIK YOGENDRA, DELIANG FAN, SYED SARWAR, PRIYA PANDA, GOPAL SRINIVASAN, JASON
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationLecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson
Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal
More informationMidterm. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Lecture Outline. Pass Transistor Logic. Restore Output.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 16: March 21, 2017 Transmission Gates, Euler Paths, Energy Basics Review Midterm! Midterm " Mean: 79.5 " Standard Dev: 14.5 2 Lecture Outline!
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationEE247 Lecture 16. Serial Charge Redistribution DAC
EE47 Lecture 16 D/A Converters D/A examples Serial charge redistribution DAC Practical aspects of current-switch DACs Segmented current-switch DACs DAC self calibration techniques Current copiers Dynamic
More informationAuxiliaire d enseignement Nicolas Ayotte
2012-02-15 GEL 4203 / GEL 7041 OPTOÉLECTRONIQUE Auxiliaire d enseignement Nicolas Ayotte GEL 4203 / GEL 7041 Optoélectronique VI PN JUNCTION The density of charge sign Fixed charge density remaining 2
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationDesign Engineering MEng EXAMINATIONS 2016
IMPERIAL COLLEGE LONDON Design Engineering MEng EXAMINATIONS 2016 For Internal Students of the Imperial College of Science, Technology and Medicine This paper is also taken for the relevant examination
More informationDelay and Energy Consumption Analysis of Conventional SRAM
World Academy of Science, Engineering and Technology 13 8 Delay and Energy Consumption Analysis of Conventional SAM Arash Azizi-Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, and Ali Barati Abstract
More informationSynaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics
Synaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics Byung-Gook Park Inter-university Semiconductor Research Center & Department of Electrical and Computer Engineering Seoul National
More informationAdministrative Stuff
EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationChapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan
Chapter 2 CMOS Transistor Theory Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan Outline Introduction MOS Device Design Equation Pass Transistor Jin-Fu Li, EE,
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More information5. CMOS Gate Characteristics CS755
5. CMOS Gate Characteristics Last module: CMOS Transistor theory This module: DC Response Logic Levels and Noise Margins Transient Response Delay Estimation Transistor ehavior 1) If the width of a transistor
More informationMeasuring the Leakage Current Module Characteristic of the HICANN Neuron Circuit
Measuring the Leakage Current Module Characteristic of the HICANN Neuron Circuit David Stöckel July 31, 2014 Abstract The HICANN wafer scale integrated circuits of Schemmel et al. [4] emulate the differential
More informationMicroelectronic Devices and Circuits Lecture 13 - Linear Equivalent Circuits - Outline Announcements Exam Two -
6.012 Microelectronic Devices and Circuits Lecture 13 Linear Equivalent Circuits Outline Announcements Exam Two Coming next week, Nov. 5, 7:309:30 p.m. Review Subthreshold operation of MOSFETs Review Large
More informationAn Analog-digital CMOS circuit for motion detection based on direction-selective neural networks
An Analog-digital CMOS circuit for motion detection based on direction-selective neural networks Masato Koutani, Tetsuya Asai, and Yoshihito Amemiya Department of Electrical Engineering, Hokkaido University
More informationCryogenic Characterization of 28 nm Bulk CMOS Technology for Quantum Computing
Cryogenic Characterization of 8 nm Bulk CMOS Technology for Quantum Computing Arnout Beckers, Farzan Jazaeri, Andrea Ruffino, Claudio Bruschini, Andrea Baschirotto, and Christian Enz Integrated Circuits
More informationLecture 23. Dealing with Interconnect. Impact of Interconnect Parasitics
Lecture 23 Dealing with Interconnect Impact of Interconnect Parasitics Reduce Reliability Affect Performance Classes of Parasitics Capacitive Resistive Inductive 1 INTERCONNECT Dealing with Capacitance
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor
More informationE40M. Binary Numbers. M. Horowitz, J. Plummer, R. Howe 1
E40M Binary Numbers M. Horowitz, J. Plummer, R. Howe 1 Reading Chapter 5 in the reader A&L 5.6 M. Horowitz, J. Plummer, R. Howe 2 Useless Box Lab Project #2 Adding a computer to the Useless Box alows us
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationIntroduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline
Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and
More informationLogic. Intro to Neuroscence: Neuromorphic Engineering 12/9/2013. (c) S. Liu and T. Delbruck, Inst. of Neuroinformatics, UZH-ETH Zurich 1
Introductory Course in Neuroscience Neuromorphic Shih-Chii Liu Inst. of Neuroinformatics http://www.ini.uzh.ch/~shih/wiki/doku.php?id=introneuro What is neuromorphic engineering? It consists of embodying
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationModeling All-MOS Log-Domain Σ A/D Converters
DCIS 04 Modeling All-MOS Log Σ ADCs Intro Circuits Modeling Example Conclusions 1/22 Modeling All-MOS Log-Domain Σ A/D Converters X.Redondo 1, J.Pallarès 2 and F.Serra-Graells 1 1 Institut de Microelectrònica
More informationAdvances in Radio Science
Advances in Radio Science, 3, 331 336, 2005 SRef-ID: 1684-9973/ars/2005-3-331 Copernicus GmbH 2005 Advances in Radio Science Noise Considerations of Integrators for Current Readout Circuits B. Bechen,
More informationECE315 / ECE515 Lecture-2 Date:
Lecture-2 Date: 04.08.2016 NMOS I/V Characteristics Discussion on I/V Characteristics MOSFET Second Order Effect NMOS I-V Characteristics ECE315 / ECE515 Gradual Channel Approximation: Cut-off Linear/Triode
More informationS No. Questions Bloom s Taxonomy Level UNIT-I
GROUP-A (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNIT-I 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationLecture 16: Circuit Pitfalls
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution
More information