What Does VLV Testing Detect?
|
|
- Grant Thompson
- 5 years ago
- Views:
Transcription
1 Center for RC eliable omputing What Defect Does L Testing Detect? Stanford University Nov. 1, 1999 Outline Introduction Physics of Tunneling Proposal of Tunneling Defect Theoretical Calculation Experiment Evidence Future Work Summary 1 Introduction L effectiveness table [Chang 96] Failure Mode IDDQ L Transmission gate opens NO YES Threshold voltage shifts NO YES Diminished-drive gates NO YES Gate oxide shorts YES YES Metal shorts YES YES Defective interconnect buffers YES YES High resistance interconnects NO NO Tunneling open NO NO Introduction 9 L-only CUTs in Murphy 5 CUT can not be explained by the table Goal of this talk 3 4 Physics of Tunneling Put Them ll Together 5 6 Page 1 Nov.1, 1999
2 Proposal of Tunneling Defect L-only CUT behavior Previous study Possible explanations Proposal of a tunneling defect formation of a tunneling defect qualitative description of the circuit behavior at nominal voltage at very low voltage L-only CUT Behavior Long time IDDQ leakage phenomena IDDQ in u time (second) 8 Maly Previous Study Possible Explanations location C R Logic 1fF 1T 1pF 1G I/O 1pF 1G 9 1 Formation of a Tunneling Defect Qualitative Description I DDQ (t) very long leakage Metal X SiO SiO Poly very thin in out 11 1 Page Nov.1, 1999
3 @ Nominal ery Low oltage fast ckt response log I very slow I DDQ leakage log I very slow response very slow I DDQ leakage Theoretical Calculation electrical model analytical equations simulation results nominal voltage L IDDQ leakage J tunnel Electrical model d, = defect oxide thickness, area E ox = ox /d ox C d metal C gate poly nalytical equations Tunneling effect (FN+Dir) [Schuegraf 9] tunnel Eox J ( t) = e correction _ fector = (1 ( / Eox ) b b ox ) e B( b ox ) b / E ox Simulation: 5,C gate = 4fF, d=1 =1 m m p_tunnel p_couple J poly( t) = C Coupling Effect tunnel gate ( t) dt voltage 3 = ox d Cd poly = metal Cd + C Cd gate time (ns) 18 Page 3 Nov.1, 1999
4 I DDQ Leakage Simulation: 1.7 nalytical equation voltage m p_tunnel p_couple time (ns) 19 T leakage = C J gate L_tunnel ssumptions (@ nominal voltage) = (th -t) =.5 -.7=1.8 C gate = 4fF T leakage = 1ms ~ 1S = 1 m Calculation result J L_tunnel = 7 ~ 7. /cm Experimental Evidence Boolean Test - Expected Behavior Boolean Test Evidence expected behavior experimental results IDDQ Test Evidence expected behavior experimental results Failure nalysis Evidence If not tunneling [Chang 96] Delay Ratio = T_bad / T_good either fail or less than 1 x slower Defect Max Delay Weak driven gate 41.7 Tran. gate open Fail t shift.98 Diminished drive gate Boolean Test - Expected Behavior Boolean Test - Expected Behavior If Tunneling extremely long L eventually work minimum functional voltage same as good Expected shmoo plot N Good not tunneling tunneling L min 3 ns s ms delay 4 Page 4 Nov.1, 1999
5 Boolean Test - Experiment Results Table of delay different voltage I DDQ Test - Expected Behavior Table of expected IDDQ behavior cut id Good 3nS 6nS 1ns 47nS sq 38nS 114nS N 6nS sq 3nS 86nS N Fail 35.8.m1 36nS N Fail Fail sq 36nS N Fail Fail 1.3.m1 34nS 3ns 5 S 3mS sq 37nS 148nS 4nS 1 S m1 35nS ns 3 S ms sq 37nS 9nS 6 S 3 S m1 35nS 7nS 9 S 4 S defect high IDDQ () IDDQ leakge GOS Y N - - t shift N N - - WD gate Y N - - Tr. gate open Y N - - RC Y Y S No D/S junction leakage Y Y ms ~ S decrease decrease Tunneling Y Y ms ~ S No 5 6 IDDQ in u I DDQ Test - Experiment Results I DDQ different voltage (from sq) Time (second) I DDQ Test - Experiment Results Table of experimental I DDQ behavior cut id max decrease leakage IDDQ decrease sq N sq N m1 18 N sq 38 N m1 88 Y 14~56mS N sq 5 Y 56~7mS N m1 14 Y 8~69mS N sq 35 Y 4~57mS N m1 1 Y 4~55mS N 8 Failure nalysis Sematech data [Nigh 98] dd=5 dd=3.3 dd=1.8 m d t ns m d t ns m d t ns Page 5 Nov.1, 1999
6 Q: Why sequence L? ll tunneling defect CUTs are seq. tunneling effect has polarity rise time different than fall time Q3: Is it process error or defect? Defect 5 CUTs from 3 lots, different wafer Q4: What is the best test condition? L transition pattern maybe low temperature 31 Q5: Will it cause reliability problem? Yes low quality oxide, break down easily No Sematch data [Nigh 98] IDDQ did not change much after burn-in after break down, becomes high impedance 3 Q6: Will it cause more trouble in the future technology? No Cg smaller, coupling effect dominates dd decreases, FN tunneling decrease Yes metal intensive direct tunneling is field depdent 33 Summary 5/9 L CUT can be explained by FN tunneling CUT ID high IDDQ slow IDDQ possible defect sq N N N t shift? sq N N N t shift? 35.8.m1 Y N N shorts? sq Y N N shorts? 1.3.m1 Y Y Y Tunneling sq Y Y Y Tunneling m1 Y Y Y Tunneling sq Y Y Y Tunneling m1 Y Y Y Tunneling 34 Reference ppendix 35 Page 6 Nov.1, 1999
7 Direct Tunneling Oxide thinner than 4~5nm Fowler-Nordheim Tunneling Strongly depends on electric field Trap ssisted Tunneling Depends on oxide quality I DDQ Test - Experiment Result Definition of I DDQ I(t) = I leak exp (-t/ ) + I final I leak I fianl 39 time 4 Page 7 Nov.1, 1999
Fault Modeling. Fault Modeling Outline
Fault Modeling Outline Single Stuck-t Fault Model Other Fault Models Redundancy and Untestable Faults Fault Equivalence and Fault Dominance Method of oolean Difference Copyright 1998 Elizabeth M. Rudnick
More informationVLSI GATE LEVEL DESIGN UNIT - III P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT
VLSI UNIT - III GATE LEVEL DESIGN P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) contents GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate gate circuits, Time Delays, Driving large
More informationL ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling
L13 04202017 ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling Scaling laws: Generalized scaling (GS) p. 610 Design steps p.613 Nanotransistor issues (page 626) Degradation
More informationUNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. Professor Oldham Fall 1999
UNIVERSITY OF CLIFORNI College of Engineering Department of Electrical Engineering and Computer Sciences Professor Oldham Fall 1999 EECS 40 FINL EXM 13 December 1999 Name: Last, First Student ID: T: Kusuma
More informationSingle Stuck-At Fault Model Other Fault Models Redundancy and Untestable Faults Fault Equivalence and Fault Dominance Method of Boolean Difference
Single Stuck-At Fault Model Other Fault Models Redundancy and Untestable Faults Fault Equivalence and Fault Dominance Method of Boolean Difference Copyright 1998 Elizabeth M. Rudnick 1 Modeling the effects
More informationand V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )
ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 13, 2017 Variation; I/O Circuits, Inductive Noise Lecture Outline! Design Quality " Variation! Packaging! Variation and Testing!
More informationFLCC Seminar. Spacer Lithography for Reduced Variability in MOSFET Performance
1 Seminar Spacer Lithography for Reduced Variability in MOSFET Performance Prof. Tsu-Jae King Liu Electrical Engineering & Computer Sciences Dept. University of California at Berkeley Graduate Student:
More informationV t vs. N A at Various T ox
V t vs. N A at Various T ox Threshold Voltage, V t 0.9 0.8 0.7 0.6 0.5 0.4 T ox = 5.5 nm T ox = 5 nm T ox = 6 nm m = 4.35 ev, Q ox = 0; V sb = 0 V 0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Body Doping, N
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar
More informationLecture 16: Circuit Pitfalls
Introduction to CMOS VLSI Design Lecture 16: Circuit Pitfalls David Harris Harvey Mudd College Spring 2004 Outline Pitfalls Detective puzzle Given circuit and symptom, diagnose cause and recommend solution
More informationELEN 610 Data Converters
Spring 04 S. Hoyos - EEN-60 ELEN 60 Data onverters Sebastian Hoyos Texas A&M University Analog and Mixed Signal Group Spring 04 S. Hoyos - EEN-60 Electronic Noise Signal to Noise ratio SNR Signal Power
More informationDigital Integrated Circuits A Design Perspective
Semiconductor Memories Adapted from Chapter 12 of Digital Integrated Circuits A Design Perspective Jan M. Rabaey et al. Copyright 2003 Prentice Hall/Pearson Outline Memory Classification Memory Architectures
More informationCircuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive
More informationObjective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components
Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the
More informationFloating Gate Devices: Operation and Compact Modeling
Floating Gate Devices: Operation and Compact Modeling Paolo Pavan (1), Luca Larcher (1) and Andrea MarmirolI (2) (1) Università di Modena e Reggio Emilia, Via Fogliani, 1 42100 Reggio Emilia (Italy) -
More informationFlash Memory Cell Compact Modeling Using PSP Model
Flash Memory Cell Compact Modeling Using PSP Model Anthony Maure IM2NP Institute UMR CNRS 6137 (Marseille-France) STMicroelectronics (Rousset-France) Outline Motivation Background PSP-Based Flash cell
More informationCircuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number
EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >
More information23.0 Introduction Review
ECE 650R: Reliability Physics of Nanoelectronic Devices Lecture 22: TDDB Statistics Date: Nov. 0, 2006 Class Notes: Lutfe Siddiqui Review: Saakshi Gangwal 23.0 Introduction Time dependent dielectric breakdown
More informationAdvanced Testing. EE5375 ADD II Prof. MacDonald
Advanced Testing EE5375 ADD II Prof. MacDonald Functional Testing l Original testing method l Run chip from reset l Tester emulates the outside world l Chip runs functionally with internally generated
More informationEE650R: Reliability Physics of Nanoelectronic Devices Lecture 18: A Broad Introduction to Dielectric Breakdown Date:
EE650R: Reliability Physics of Nanoelectronic Devices Lecture 18: A Broad Introduction to Dielectric Breakdown Date: Nov 1, 2006 ClassNotes: Jing Li Review: Sayeef Salahuddin 18.1 Review As discussed before,
More informationAUTOMOTIVE GRADE. A I DM Pulsed Drain Current P A = 25 C Maximum Power Dissipation 2.0 P A = 70 C Maximum Power Dissipation 1.
AUTOMOTIVE GRADE Features Advanced Planar Technology Ultra Low On-Resistance Logic Level Gate Drive Dual N and P Channel MOSFET Surface Mount Available in Tape & Reel 5 C Operating Temperature Lead-Free,
More informationLecture 16: Circuit Pitfalls
Lecture 16: Circuit Pitfalls Outline Variation Noise Budgets Reliability Circuit Pitfalls 2 Variation Process Threshold Channel length Interconnect dimensions Environment Voltage Temperature Aging / Wearout
More informationS No. Questions Bloom s Taxonomy Level UNIT-I
GROUP-A (SHORT ANSWER QUESTIONS) S No. Questions Bloom s UNIT-I 1 Define oxidation & Classify different types of oxidation Remember 1 2 Explain about Ion implantation Understand 1 3 Describe lithography
More informationLecture 2: CMOS technology. Energy-aware computing
Energy-Aware Computing Lecture 2: CMOS technology Basic components Transistors Two types: NMOS, PMOS Wires (interconnect) Transistors as switches Gate Drain Source NMOS: When G is @ logic 1 (actually over
More informationFault Modeling. 李昆忠 Kuen-Jong Lee. Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan. VLSI Testing Class
Fault Modeling 李昆忠 Kuen-Jong Lee Dept. of Electrical Engineering National Cheng-Kung University Tainan, Taiwan Class Fault Modeling Some Definitions Why Modeling Faults Various Fault Models Fault Detection
More informationModel-Based I DDQ Pass/Fail Limit Setting
Model-Based I DDQ Pass/Fail Limit Setting T. Aruna Unni Xilinx Corp. 21 Logic Drive, San Jose CA 955 Ph: (48) 879-5366, Fax: (48) 377-3259 Email: aruna@xilinx.com Abstract This paper describes several
More informationCMPEN 411 VLSI Digital Circuits Spring 2012
CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 09: Resistance & Inverter Dynamic View [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]
More informationScaling of MOS Circuits. 4. International Technology Roadmap for Semiconductors (ITRS) 6. Scaling factors for device parameters
1 Scaling of MOS Circuits CONTENTS 1. What is scaling?. Why scaling? 3. Figure(s) of Merit (FoM) for scaling 4. International Technology Roadmap for Semiconductors (ITRS) 5. Scaling models 6. Scaling factors
More informationMASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MSSCHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences nalysis and Design of Digital Integrated Circuits (6.374) - Fall 2003 Quiz #1 Prof. nantha Chandrakasan Student
More informationIRF5851. HEXFET Power MOSFET. Ultra Low On-Resistance Dual N and P Channel MOSFET Surface Mount Available in Tape & Reel Low Gate Charge.
PD-93998B HEXFET Power MOSFET l l l l l Ultra Low On-Resistance Dual N and P Channel MOSFET Surface Mount Available in Tape & Reel Low Gate Charge G S2 G2 2 3 6 5 4 D S D2 N-Ch P-Ch DSS 20-20 R DS(on)
More informationEE 330 Lecture 16. MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow
EE 330 Lecture 16 MOS Device Modeling p-channel n-channel comparisons Model consistency and relationships CMOS Process Flow Review from Last Time Operation Regions by Applications Id I D 300 250 200 150
More informationVLSI Design and Simulation
VLSI Design and Simulation Performance Characterization Topics Performance Characterization Resistance Estimation Capacitance Estimation Inductance Estimation Performance Characterization Inverter Voltage
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 4 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI Contents Delay estimation Simple RC model Penfield-Rubenstein Model Logical effort Delay
More informationEE 330 Lecture 17. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law
More informationSIPMOS Small-Signal-Transistor
Type SIPMOS Small-Signal-Transistor Feature N-Channel Enhancement mode Logic level BSS131 Product Summary V DS 24 V R DS(on),max 14 Ω I D.1 A dv /dt rated Pb-free lead-plating; RoHS compliant PG-SOT-23
More information! Crosstalk. ! Repeaters in Wiring. ! Transmission Lines. " Where transmission lines arise? " Lossless Transmission Line.
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 24: April 19, 2018 Crosstalk and Wiring, Transmission Lines Lecture Outline! Crosstalk! Repeaters in Wiring! Transmission Lines " Where transmission
More informationSIPMOS Small-Signal-Transistor
Type BSS225 SIPMOS Small-Signal-Transistor Feature n-channel enhancement mode Logic level Product Summary 1) V DS 6 V R DS(on),max 45 Ω I D.9 A dv /dt rated Qualified according to AEC Q11 Halogen free
More information2. (2pts) What is the major reason that contacts from metal to poly are not allowed on top of the gate of a transistor?
EE 330 Exam 1 Spring 2018 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.
More informationCARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DIGITAL INTEGRATED CIRCUITS FALL 2002
CARNEGIE MELLON UNIVERSITY DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING 18-322 DIGITAL INTEGRATED CIRCUITS FALL 2002 Final Examination, Monday Dec. 16, 2002 NAME: SECTION: Time: 180 minutes Closed
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationEE 330 Lecture 16. MOSFET Modeling CMOS Process Flow
EE 330 Lecture 16 MOSFET Modeling CMOS Process Flow Model Extensions 300 Id 250 200 150 100 50 300 0 0 1 2 3 4 5 Vds Existing Model 250 200 Id 150 100 50 Slope is not 0 0 0 1 2 3 4 Actual Device Vds Model
More informationExact Analysis of a Common-Source MOSFET Amplifier
Exact Analysis of a Common-Source MOSFET Amplifier Consider the common-source MOSFET amplifier driven from signal source v s with Thévenin equivalent resistance R S and a load consisting of a parallel
More informationUniversity of Toronto. Final Exam
University of Toronto Final Exam Date - Apr 18, 011 Duration:.5 hrs ECE334 Digital Electronics Lecturer - D. Johns ANSWER QUESTIONS ON THESE SHEETS USING BACKS IF NECESSARY 1. Equation sheet is on last
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationEE141Microelettronica. CMOS Logic
Microelettronica CMOS Logic CMOS logic Power consumption in CMOS logic gates Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit
More informationEEC 116 Lecture #5: CMOS Logic. Rajeevan Amirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation
EEC 116 Lecture #5: CMOS Logic Rajeevan mirtharajah Bevan Baas University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW
More informationDKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction
DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction Saraju P. Mohanty Dept of Computer Science and Engineering University of North Texas smohanty@cs.unt.edu http://www.cs.unt.edu/~smohanty/
More informationENEE 359a Digital VLSI Design
SLIDE 1 ENEE 359a Digital VLSI Design & Logical Effort Prof. blj@ece.umd.edu Credit where credit is due: Slides contain original artwork ( Jacob 2004) as well as material taken liberally from Irwin & Vijay
More informationLecture 7 Circuit Delay, Area and Power
Lecture 7 Circuit Delay, Area and Power lecture notes from S. Mitra Intro VLSI System course (EE271) Introduction to VLSI Systems 1 Circuits and Delay Introduction to VLSI Systems 2 Power, Delay and Area:
More informationFault Tolerant Computing CS 530 Fault Modeling
CS 53 Fault Modeling Yashwant K. Malaiya Colorado State University Fault Modeling Why fault modeling? Stuck-at / fault model The single fault assumption Bridging and delay faults MOS transistors and CMOS
More informationN- & P-Channel Enhancement Mode Field Effect Transistor
PRODUCT SUMMARY V (BR)DSS R DS(ON) I D annel 30 27.5m 7A annel -30 34m -6A G : GATE D : DRAIN S : SOURCE ABSOLUTE MAXIMUM RATINGS (T C = 25 C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS SYMBOL annel
More informationType Package Pb-free Tape and Reel Information SN7002N PG-SOT-23 Yes H6327: 3000 pcs/reel SN7002N
SN72N SIPMOS Small-Signal-Transistor Feature N-Channel Enhancement mode Logic Level dv/dt rated Qualified according to EC Q Halogen-free according to IEC6249-2-2 Gate pin Product Summary V DS 6 V R DS(on)
More informationTOSHIBA Field Effect Transistor Silicon N Channel MOS Type (π MOSIII) 2SK2610
TOSHIBA Field Effect Transistor Silicon N Channel MOS Type (π MOSIII) Chopper Regulator, DC DC Converter and Motor Drive Applications Unit: mm Low drain source ON resistance : RDS (ON) = 2.3 Ω (typ.) High
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 23: April 17, 2018 I/O Circuits, Inductive Noise, CLK Generation Lecture Outline! Packaging! Variation and Testing! I/O Circuits! Inductive
More informationDigital Integrated Circuits Designing Combinational Logic Circuits. Fuyuzhuo
Digital Integrated Circuits Designing Combinational Logic Circuits Fuyuzhuo Introduction Digital IC Dynamic Logic Introduction Digital IC EE141 2 Dynamic logic outline Dynamic logic principle Dynamic logic
More informationSEMICONDUCTOR MEMORIES
SEMICONDUCTOR MEMORIES Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM
More informationBSS123. Rev K/W. R thja
Thermal Characteristics Parameter Symbol Values Unit min. typ. max. Characteristics Thermal resistance, junction - ambient at minimum footprint R thj - - 35 K/W Electrical Characteristics, at T j = 25
More informationPreliminary data. Type Package Ordering Code Tape and Reel Information BSS 192 P SOT89 Q67042-S4168 -
SIPMOS Small-Signal-Transistor Feature P-Channel Enhancement mode Logic Level dv/dt rated Gate pin Product Summary V DS -25 V R DS(on) 2 Ω I D -.9 Drain pin 2 Source pin 3 3 SOT89 2 2 VPS562 Type Package
More informationDigital Integrated Circuits A Design Perspective. Semiconductor. Memories. Memories
Digital Integrated Circuits A Design Perspective Semiconductor Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies Semiconductor Memory Classification
More informationThe Wire EE141. Microelettronica
The Wire 1 Interconnect Impact on Chip 2 Example: a Bus Network transmitters receivers schematics physical 3 Wire Models All-inclusive model Capacitance-only 4 Impact of Interconnect Parasitics Interconnect
More informationOptiMOS 2 + OptiMOS -P 2 Small Signal Transistor
BSZ5DCKD H OptiMOS + OptiMOS -P Small Signal Transistor Features Product Summary Complementary P + channel P Enhancement mode Super Logic level (.5V rated) Common drain Avalanche rated V DS - V R DS(on),max
More information2. (2pts) What is the major difference between an epitaxial layer and a polysilicon layer?
EE 330 Exam 1 Spring 2017 Name Instructions: Students may bring 1 page of notes (front and back) to this exam and a calculator but the use of any device that has wireless communication capability is prohibited.
More informationLecture 5 Fault Modeling
Lecture 5 Fault Modeling Why model faults? Some real defects in VLSI and PCB Common fault models Stuck-at faults Single stuck-at faults Fault equivalence Fault dominance and checkpoint theorem Classes
More informationEEC 118 Lecture #6: CMOS Logic. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 118 Lecture #6: CMOS Logic Rajeevan mirtharajah University of California, Davis Jeff Parkhurst Intel Corporation nnouncements Quiz 1 today! Lab 2 reports due this week Lab 3 this week HW 3 due this
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationCONSTANT CURRENT STRESS OF ULTRATHIN GATE DIELECTRICS
CONSTANT CURRENT STRESS OF ULTRATHIN GATE DIELECTRICS Y. Sun School of Electrical & Electronic Engineering Nayang Technological University Nanyang Avenue, Singapore 639798 e-mail: 14794258@ntu.edu.sg Keywords:
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2016 Final Friday, May 6 5 Problems with point weightings shown.
More informationEE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors
EE 330 Lecture 16 Devices in Semiconductor Processes MOS Transistors Review from Last Time Model Summary I D I V DS V S I B V BS = 0 0 VS VT W VDS ID = μcox VS VT VDS VS V VDS VS VT L T < W μc ( V V )
More informationCMOS Transistors, Gates, and Wires
CMOS Transistors, Gates, and Wires Should the hardware abstraction layers make today s lecture irrelevant? pplication R P C W / R W C W / 6.375 Complex Digital Systems Christopher atten February 5, 006
More informationLeakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta I DDQ Testing
JOURNAL OF ELECTRONIC TESTING: Theory and Applications 19, 341 352, 2003 c 2003 Kluwer Academic Publishers. Manufactured in The Netherlands. Leakage Current in Sub-Quarter Micron MOSFET: A Perspective
More informationSemiconductor Memories
!"#"$%&'()$*#+%$*,' -"+./"$0 1'!*0"#)'2*+03*.$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002 !"#$%&'()*&'*+&, Memory Classification Memory Architectures
More informationPD A N-CHANNEL MOSFET 1 D2 P-CHANNEL MOSFET. Top View SO-8. 1
l l l l l Generation Technology Ultra Low On-Resistance Dual N and P Channel MOSFET Surface Mount Fully valanche Rated Description Fifth Generation HEXFETs from International Rectifier utilize advanced
More informationLecture 25. Semiconductor Memories. Issues in Memory
Lecture 25 Semiconductor Memories Issues in Memory Memory Classification Memory Architectures TheMemoryCore Periphery 1 Semiconductor Memory Classification RWM NVRWM ROM Random Access Non-Random Access
More informationPackage Ordering Code BTS 282 Z 49 V 6.5 m P-TO Q67060-S6004-A2 P-TO Q67060-S6005-A2 P-TO Q67060-S6007.
Speed TEMPFET NChannel Enhancement mode Logic Level Input nalog driving possible Fast switching up to MHz 7 VPT5754 7 VPT567 Potentialfree temperature sensor with thyristor characteristics Overtemperature
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VIII Semiconductor Memory (chapter 12 in textbook) 1 Chapter Overview Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies
More informationParallel Processing and Circuit Design with Nano-Electro-Mechanical Relays
Parallel Processing and Circuit Design with Nano-Electro-Mechanical Relays Elad Alon 1, Tsu-Jae King Liu 1, Vladimir Stojanovic 2, Dejan Markovic 3 1 University of California, Berkeley 2 Massachusetts
More informationCS/EE N-type Transistor
CS/EE 6710 MOS Transistor Models Electrical Effects Propagation Delay N-type Transistor D + G Vds i electrons +Vgs S - 1 Another Cutaway View Thanks to National Central University for Some images Vgs Forms
More informationDynamic operation 20
Dynamic operation 20 A simple model for the propagation delay Symmetric inverter (rise and fall delays are identical) otal capacitance is linear t p Minimum length devices R W C L t = 0.69R C = p W L 0.69
More informationSample-and-Holds David Johns and Ken Martin University of Toronto
Sample-and-Holds David Johns and Ken Martin (johns@eecg.toronto.edu) (martin@eecg.toronto.edu) slide 1 of 18 Sample-and-Hold Circuits Also called track-and-hold circuits Often needed in A/D converters
More informationP-Channel Enhancement Mode Mosfet
WPM34 WPM34 P-Channel Enhancement Mode Mosfet Features Higher Efficiency Extending Battery Life Miniature SOT3-3 Surface Mount Package Super high density cell design for extremely low RDS (ON) http://www.willsemi.com
More informationMemory Trend. Memory Architectures The Memory Core Periphery
Semiconductor Memories: an Introduction ti Talk Overview Memory Trend Memory Classification Memory Architectures The Memory Core Periphery Reliability Semiconductor Memory Trends (up to the 90 s) Memory
More informationName: Answers. Mean: 83, Standard Deviation: 12 Q1 Q2 Q3 Q4 Q5 Q6 Total. ESE370 Fall 2015
University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2015 Final Tuesday, December 15 Problem weightings
More informationDual N-/Dual P-Channel 30-V (D-S) MOSFETs
Dual N-/Dual P-Channel 3-V (D-S) MOSFETs V (BR)DSS Min (V) r DS(on) Max ( ) V GS(th) (V) I D (A) N-Channel 3 @ V GS = 2 V.8 to 2.5.85 P-Channel 3 2 @ V GS = 2 V 2 to 4.5.6 Low On-Resistance:.8/.6 Low Threshold:.5/
More informationTiming-Aware Decoupling Capacitance Allocation in Power Distribution Networks
Timing-Aware Decoupling Capacitance Allocation in Power Distribution Networks Sanjay Pant, David Blaauw Electrical Engineering and Computer Science University of Michigan 1/22 Power supply integrity issues
More informationChapter 2 Process Variability. Overview. 2.1 Sources and Types of Variations
Chapter 2 Process Variability Overview Parameter variability has always been an issue in integrated circuits. However, comparing with the size of devices, it is relatively increasing with technology evolution,
More informationMaximum Ratings, at T j = 25 C, unless otherwise specified Parameter Symbol Value Unit Continuous drain current I D. I D puls 0.68.
SIPMOS Small-Signal-Transistor Feature N-Channel Enhancement mode Logic Level dv/dt rated Gate pin1 Product Summary V DS 1 V R DS(on) 6 Ω I D.17 Drain pin 3 Source pin 2 PG-SOT23 3 1 2 VPS5161 Type Package
More informationMM74C906 Hex Open Drain N-Channel Buffers
Hex Open Drain N-Channel Buffers General Description The MM74C906 buffer employs monolithic CMOS technology in achieving open drain outputs. The MM74C906 consists of six inverters driving six N-channel
More informationMake sure the exam paper has 9 pages (including cover page) + 3 pages of data for reference
UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences Spring 2006 EE143 Midterm Exam #1 Family Name First name SID Signature Make sure the exam paper
More informationReview Energy Bands Carrier Density & Mobility Carrier Transport Generation and Recombination
Review Energy Bands Carrier Density & Mobility Carrier Transport Generation and Recombination The Metal-Semiconductor Junction: Review Energy band diagram of the metal and the semiconductor before (a)
More informationP-Channel Enhancement Mode Mosfet
WPM34 WPM34 P-Channel Enhancement Mode Mosfet Http://www.sh-willsemi.com Features Higher Efficiency Extending Battery Life Miniature SOT3-3 Surface Mount Package Super high density cell design for extremely
More informationSemiconductor Memories
Semiconductor References: Adapted from: Digital Integrated Circuits: A Design Perspective, J. Rabaey UCB Principles of CMOS VLSI Design: A Systems Perspective, 2nd Ed., N. H. E. Weste and K. Eshraghian
More informationTopics to be Covered. capacitance inductance transmission lines
Topics to be Covered Circuit Elements Switching Characteristics Power Dissipation Conductor Sizes Charge Sharing Design Margins Yield resistance capacitance inductance transmission lines Resistance of
More informationCMOS Inverter (static view)
Review: Design Abstraction Levels SYSTEM CMOS Inverter (static view) + MODULE GATE [Adapted from Chapter 5. 5.3 CIRCUIT of G DEVICE Rabaey s Digital Integrated Circuits,, J. Rabaey et al.] S D Review:
More informationEEC 118 Lecture #5: CMOS Inverter AC Characteristics. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation
EEC 8 Lecture #5: CMOS Inverter AC Characteristics Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Acknowledgments Slides due to Rajit Manohar from ECE 547 Advanced
More informationAdvanced Flash and Nano-Floating Gate Memories
Advanced Flash and Nano-Floating Gate Memories Mater. Res. Soc. Symp. Proc. Vol. 1337 2011 Materials Research Society DOI: 10.1557/opl.2011.1028 Scaling Challenges for NAND and Replacement Memory Technology
More informationSPP03N60S5 SPB03N60S5
Cool MOS Power Transistor New revolutionary high voltage technology Ultra low gate charge Periodic avalanche proved Extreme dv/dt rated Optimized capacitances Improved noise immunity Former development
More informationMODULE 5 Chapter 7. Clocked Storage Elements
MODULE 5 Chapter 7 Clocked Storage Elements 3/9/2015 1 Outline Background Clocked Storage Elements Timing, terminology, classification Static CSEs Latches Registers Dynamic CSEs Latches Registers 3/9/2015
More information