Timing Analysis in Presence of Supply Voltage and Temperature Variations

Transcription

1 Timing Analysis in Presence of Supply Voltage and Temperature Variations Benoît Lasbouygues, Robin Wilson STMicroelectronics, Crolles France Nadine Azemard, Philippe Maurine LIRMM, Montpellier France

2 Motivation Delay is strongly dependent on supply voltage +10% Vdd, induce > +20% delay WC/BC drop ±10% of V, is it accurate? Temperature sensitivity depends on domains Function of process and supply voltage value 15 Timing (125 C-m40 C) Timing (125 C) 0 (%) -15 0,8 0,9 1 1,1 1,2 V (V) -30 Temperature Inversion Possibility to reduce margins T. independent 2

3 Our goal Reduced margins using real V, T values for each cell Avoid over-design or re-design steps How? Using Vdrop and T. Gradient maps Non-linear timing derating for each instance 3

4 How? Manage Vdd and θ at cell level? Popular K-factor method Voltage Temperature Delay Do + D V V D + θ θ From a standard corner analysis we estimate timing for any Voltage and Temperature value Best case Worst case Temperature Voltage Process Silicon 4

5 Problem How to define accurately scaling factors? Delay Do + D V V D + θ θ?? Linear function not enough accurate Polynomial template not enough accurate on large range of V and T. Scaling must follow physical behavior 5

6 Sensitivity analysis outhl V τ ( ps / V ) Derating factor must characterized: V (V ) ) Slow and domains Design dependence τ IN ( ps Input slope "0.092, 0.247, 0.553, 1.172", \ "0.093, 0.247, 0.556, 1.172", \ "0.103, 0.258, 0.557, 1.166", \ "0.134, 0.275, 0.556, 1.173", \ "0.194, 0.344, 0.597, 1.176" ); Output Capacitance Transition Time LUT 6

7 Analytical Timing Model Slope Modeling the transistor as a current generator τ out CL V I MAX Depending on the input range value input domain: saturation current τ out DW C K W ( V V ) α Slow input domain: current function of slope τ Slow out L V α DW CL τ IN V α K W T 1 α 1 1+ α 7

8 Analytical Timing Model Delay Propagation Delay is strongly dependent on: Input slew Output Load Gate size I/O coupling capacitance (Miller effect) t τ IN α 1 α V + V T CM C + C M L τ 2 out 8

9 Analytical Timing Model Temperature Supply voltage value appears explicitly Temperature acts on Threshold Voltage and Mobility V T V Tnom δ τ out ( θ θ ) nom θ K θ nom τ in α 1 V t α X K W T K K DW C nom θ θ nom X K ( V V + δ ( θ θ )) α δ V L T ( θ θ ) nom nom 2CM + 1+ CM + C L τ 2 out 9

10 Derating Coefficient - V From analytical model, We derate formulas with respect to V We extract design dependency For slope in fast input domain, ( 1 α) τ out DW CL V V V K W ( V V ) T 1+ α T Becomes τ V Slope 2 Slope 2 a, b are V independent parameters to be calibrated OUT a V b + V C L 10

11 Derating Coefficient Temperature Temperature Template t θ a Delay + b Delay τ IN + c Delay C L τ INinv a INV + b INV C L 900 Delay (ps) C -40 C C L 120fF 300 C L 64fF 0 C L 4fF Input Slope ( ps)

12 Derating Coefficient Constraint Setup and Hold: Race between Clock and Data paths. CPN Clock C1 C2 CPI Setup (D1+D2+D3) C1 CPI Data D1 D2 D3 CPN CPN Ignore Load sensitivity, keep only slope variation CPI Setup θ a Setup + b Setup τ Data + c Setup τ Clock 12

13 Validation Standard cell Template are fitted with 3 corners (1 ref., 1 for Vdd, 1 for T) Corner computed for an entire library with derating factor Comparison: scaling values versus electrical simulations Simulation vs Derating (%) % Ref. -5 0% -10-5% 1.1 V (V) Temperature ( C) 13

14 Application - Chip level Derating on Slope Slope file (~ SDF) 1 timing update with new slope Compute delay With new slope New SDF is available (delay can be scaled using internal developed tool) Final annotation is done Derating on Delay Final SDF 14

15 Application Chip level Chip Vdrop map Timing Analysis with Vdrop data From a worst case corner, we update delay with Vdrop maps. We compute each Slope and Delay derating (cell by cell) IP Vdrop map Comparison :TA with (Vdd 10%) Versus :TA with Vdrop Data 15

16 Path Delay (ns) Results 2,50 Comparison Spice/WC/Derating Margin gain :9 to 12% ~200ps 2,25 9% 12% 2,00 1,75 2% accuracy Worst case timing Derating analysis Spice analysis Path # 16

17 Summary We propose a method to handle Temperature/V variations based on cell by cell scaling factor These deratings are non-linear and function of design conditions Taking account Vdrop in TA, highlights a significant gain in margin versus standard worst case method. Voltage Derating could be also used to validate Dynamic Voltage, Multi-Voltage feature Method has demonstrated for precise Temperature effects such as Temperature inversion and can be used to characterize hot spots. 17

18 Thank you!! 18