Will Reliability Limit Moore s Law?

Transcription

1 Will Reliability Limit Moore s Law? Tony Oates, TSMC 1

2 Outline Trends Interconnect Transistors Soft Errors in Memory and Logic Conclusions 2

3 Market Growth Electronic Equipment Revenue ($B) 2,500 2,000 1,500 1, st Wave: Desktop PC 2 nd Wave: Mobile Phone 3 rd Wave: Mobile Computing

4 System Integration and Scaling in 3D Human Brain ~20W, 3D ~100B Neural Cells (~1T Transistors) vs. Thousands of Cores 28nm HKMG vs.?w, 2D ~7B Logic transistors 20B vias, 20Km metal 3D CMOS (FinFET,..) TSV/3D-Stacking 3D + 3D Si-Based Green System Scaling 4 200x to match brain 2nm node or +7 generations (>15years) Next 10 years: reasonably clear to ~5nm Many new innovations are possible beyond 10 years Si-based 3D green CMOS + Si wafer-based 3D Chip Stacking Faster, smaller/thinner, lighter, lower power, and higher system value = Si-Based System Scaling

5 Moore s Law: Innovation Based IC Scaling Edelstein

6 Reliability Improvement Has Enabled IC Progress Bohr, But will reliability limit the pace of future progress?

7 Shrinking Reliability Margins Defects SER EM, TDDB, BTI, HCI etc.. Failure Rate 7

8 Interconnect Requirements Interconnects dominate system delay Jmax(MA/cm C ITRS Technology Node (nm) RC reduction Jmax Increase 8

9 Porous Low-k Dielectrics K=2.0 (P~40%) K=2.5 (P~25%) K=2.9 (Porosity~15%) Cap TDDB Lifetime T=125C E-Field (MV/cm) Pores reduce breakdown path length SiOC Cu Rapid reduction of reliability with increasing porosity 9

10 Porous Low-k Reliability Scaling k reduction is limited by reliability K= Median Time to Fail (t 63% ) E= 4 MV/cm, T=125C Model Porosity (%) Percolation Theory Lee IRPS Independent of voltage acceleration model 10

11 Solutions for Low-k Scaling Median Time to Fail (t 63% ) K=3.9 E= 4 MV/cm,T=125C Model β γ 0 ) e 0 L t = t ( a Model of control porcess increase t o by ~10X increase BD path length by ~30% SiO 2 Air Gap data Porous SiOC Air Gap data E Porosity (%) 11 Air Gap / non-porous materials

12 Low-k TDDB Variability Interaction 99% 63% LER, Via Overlay 10% 1% 0.1% Failure Time LER and via overlay sources of variability are aggravated by scaling 12

13 Failure Time LER Variability: Minimal Impact at Use Voltage Accelerated Test f(v/s)= E-model f(v/s)= Sqrt(E) model f(v/s)= 1/E model t = t 0 N(s) -1/β f(v/s) 99% 63% LER s = 10% s 0 Failure Time LER σ = 3%s 0, β=3, N=10000, E = 6 MV/cm Normalized dielectric thickness t = t 0 N(s) -1/β e -γv/s s fai l = s min Circuit Use 10% 1% 0.1% E=7 β=0.49 E=5 E=3 β=0.68 β=1.06 Time E=0.6 (MV/cm) β= s fail = s nom LER σ = 3%s 0, β=3, N=10000, E=0.5 MV/cm Normalized dielectric thickness

14 Scaling of Cu Electromigration 10 8 t f i = V A ν s i c i d 2 Kw Trench mode T50 (a.u.) 6 4 Slit mode 2 0 Technology node (nm) 14 Critical geometry, fast transport limit reliability

15 A Paradigm Change Jmax(MA/cm C Short length benefit, L<5µm ITRS 2010 new Technology Node (nm) J em Blech Effect ( jl) c Cu = Ω σ * ez ρ J s EM design rules are now driven by short lengths 15

16 Short Length Electromigration Scaling t 0.1% (L) / t 0.1% (L=250µm) 10nm 16nm 20nm 28nm L=5 µm L=10 µm L=250 µm t b /w 16 Short-length reliability reduces fastest! (barrier thickness reduction)

17 17 Short and Long Length Failure Times are NOT Independent ) ( ci i s i v v d s c f j j A w d KL A V t i i i i i i = ν So solutions are independent of length

18 Electromigration Process Solutions for Continued J max Increase Cu/cap interface Cap bulk Grain Boundary Metal Caps interface Cu Alloys g.b. Liner Reduction of grain boundary transport is key 18

19 Viability of Cu Process Solutions V d T/ j (Kcm 3 /A sec) 1E-11 1E-12 1E-13 1E-14 1E-15 1E-16 1E-17 1E-18 Temperature ( o C) N10 target N7 target Cu CuCo 110 N10 Pure Cu N10 CuAl doping N10 CuMn doping N10 Co-cap+Co barrier CuAl CuMn 1E-19 N5 targetcu Drift Velocity 1E /T (K -1 ) Goal 10 nm 7 nm 5 nm Cu alloys: limited options for 10 nm and below 19

20 Process Variability Impact on Electromigration Failure Times Volume=V c Area=A s L v d v j t f i = A V s i c i ν d A KL s i d w vi vi i ( ji jci ) V c, A s, j ci are statistically distributed random variables 20

21 Impact of Process Variability: Failure when j < j c L=50 µm, j=0.5 j c Multi-link N=50 R (ohm) Time(a.u.) R (ohm) j=0.7j c R~15Ω L=10 µm Time(a.u.) Short length immortality cannot be applied to circuits 21

22 Impact of Process Variation: New Extrapolation Procedures Lognormal fit j c = Lognormal fitting does not work

23 Transistor Structure and Materials Trends Mobility (performance) 100X 3D transistors and new materials on Si substrate 10X 1X Moore s Law 20nm /14nm nm nm nm 2019 Nanowire FET III-V on Si CMOS (TSMC, VLSI 04) 23 HKMG Planar N16 FinFET

24 Scaling of HK/MG Transistor Degradation Mechanisms SiO 2 /HfO 2 Linder, DAC,

25 Technology Scaling Impact on NBTI Interface State Generation NBTI Lifetime due to Vit (a.u.) EOT 1 > EOT 2 > EOT 3 > EOT 4 > EOT 5 > EOT 6 > EOT 7 > EOT 8 > EOT 9 ΔVt NBTI R-D Model EOT 1 EOT 4 EOT ( ) ( ) 2 1 2γ Eox 7 6 = A EOT E 3 C exp t EOT 2 EOT 5 3EOT 8 EOT 3 EOT 6 EOT Electric Field (MV/cm) ITRS Franco, IEDM, 2010 No additional impact of HK/MG and FinFET transitions 25

26 SiGe Channel: NBTI Scaling Solution (Si)Ge CB Si VB SiO 2 HfO 2 Max. V G -V th for 10Y [V] T=125ºC RMG SiGe MIPS Ultra-Thin EOT T inv ( EOT+4Å) [Å] Franco et al, TED,

27 New Channel Materials Ge PMOS NBTI (SiO 2 / HfO 2 ) InAs NMOS PBTI Maximum V G -V th [V] (Si)Ge Si T inv [Å] T=125C Si baseline SiGe 55%, Tinv1 SiGe 55%,Tinv2 SiGe 45%, Tinv3 SiGe finfet r-ge (planar) s-ge (planar & finfet) ITRS Target Deora, TDMR 2013 Franco, TED, TDMR PBTI becomes the dominant degradation mechanism? But gate stack quality is critical

28 New Gate Stack Materials: SiO 2 IL Replacement by High-k IL Gate Dielectric TDDB SiO 2 /HfO 2 Al 2 O 3 /HfO 2 ITRS Sahoo and Oates, TDMR

29 Circuit Impact of BTI: SRAM Vcc,min Shift (+) 0 (-) 0 HK/MG Lin IRPS 2007 Vt RM = Read margin WM = Write margin PMOS (RM) NMOS (RM) NMOS (WM) PMOS (WM) (+) Vcc,min Drift Medium Values (mv) (+) 0 (-) RM Dominated RM+WM Mixed WM Dominated Alpha Ratio α ratio = I I on, PU on, PG Cell design is critical to minimize RM increase 29

30 Circuit Impact of NBTI: Digital Logic Probability % T0 (HTOL-Data) T1000 (HTOL-Data) T0 (HTOL-sim) T1000 (HTOL-sim) T10yrs (0.9V 100C-sim) Vdd=1.4V, 125 o C, 1000 hours Data (symbols) T1000 ~ Nil aging Simulation (lines) T1000 ~ Nil aging T10yrs ~ 1.65% Norm. Freq (a.u.) ARM11, 40nm Vaidyanathan IRPS 2011 Process variation can obscure aging 30

31 BTI is a Time-Dependent Variability Source σ( Vth) = K EOT µ ( Vth) A GOX σ( Vt) (mv) Scaling 31 1/(A GOX ) 0.5 (um -1 )

32 BTI Aging and Process Variation: New Definitions of Reliability Probability density w/o NBTI w/ NBTI point defined by 3σ or 99.9% probability of occurence fall-out Circuit/Device parameter Reliability can be defined in terms of fall-out from a process variability window 32

33 Variability and Degradation of Circuits Variability and NBTI Scaling Ring Osc. Fall-out NBTI Id, Freq V dd, 125C Transistor, DC Transistor, AC Ring Oscillator Process Variation Process variation Induced 3σ Id (a.u.) NBTI Induced delay (%) 1 Tech. node (a.u.) Tech. node (a.u.) Reliability fall-out improves with scaling 33

34 10000 SER per Mega-Devices 1000 SER Scaling Trends Alpha and Fast Neutrons SRAM FF MCU Probability SRAM Multi-bit 65nm wi DNW 45nm widnw 40nm widnw 45nm wodnw 28m wo DNW nm 90nm 65nm 40nm 28nm Technology MCU Cluster Size (um) DNW=Deep N Well Component trends are favorable - but system trends are not 34

35 Challenges: SER of Combinational Logic Fast Neutrons FF TSMC 40 nm R-OSC Comparator Above ~1 GHz, logic errors can dominate system SER 35

36 Virtual SER Qualification Assess logic circuit reliability Neutron SER per MFFs IROC TFIT: 40 nm Flip-Flops N40G Exp. TFIT Simulation Probability IROC TFIT: SRAM Multi-bits (b) p 100.0% Exp. 10.0% Sim. 1.0% 0.1% 100 FF A FF B FF C FF D FF E 0.0% Cell# Accurate ASIC cell and circuit EDA tools available 36

37 100 Challenge: Thermal Neutrons B 10 incorporation in BEOL of advanced nodes ( ) SRAM Symbols: exp. data Lines: model SER per Cell (A.U.) 10 Alpha Thermal neutron 1 65nm 40nm 28nm 20nm Fang, TDMR 2013 Negligible < 28 nm 37

38 Challenges: Muon SER A New Issue Muons are the most abundant high energy cosmic ray particle Sierawski IRPS Ibe, IOLTS 2012

39 Some Good News: FinFET SER Horizontal Strike G D S D STI Ion track Bulk substrate Bulk substrate G Vertical Strike S STI Drain Voltage(V) LET=10 LET=20 LET=40 LET=60 Unit: MeVcm 2 /mg Time(ps) Space environment only Drain Voltage (V) LET=5 0.6 LET=10 LET= LET= Time(s) 39 FinFET shows reduced charge collection in the terrestrial environment

40 FinFET SER Charge Collection Simulations T-SRAM SER Trend 100 FIT/Mbit 10 1 Alpha Neutron G 28HP 20SOC 16FF Fast neutrons dominate 40

41 SER with III-V Channels SRAM Simulations FF Liu, TDMR Increased SER (V dd > 0.5V)

42 Conclusions Reliability progress/containment has enabled Moore s law to continue to work its magic But clearly, technology scaling is accompanied by a shrinking of reliability margins The reliability challenges to be overcome cover the entire spectrum of known issues Holistic approaches will ensure that reliability does not limit the pace of technology progression 42