FDFS2P753AZ. Integrated P-Channel PowerTrench MOSFET and Schottky Diode -30V, -3A, 115mΩ

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FFSP753Z Integrated P-hannel PowerTrench MOSFET and Schottky iode -30V, -3, 5mΩ Features Max r S(on) = 5mΩ at V GS = -0V, I = -3.0 Max r S(on) = 0mΩ at V GS = -.5V, I = -.5 V F < 0.5V @ V F < 0.

1 FFSP753Z Integrated P-hannel PowerTrench MOSFET and Schottky iode -30V, -3, 5mΩ Features Max r S(on) = 5mΩ at V GS = -0V, I = -3.0 Max r S(on) = 0mΩ at V GS = -.5V, I = -.5 V F < V F < 00m Schottky and MOSFET incorporated into single power surface mount SO- package Electrically independent Schottky and MOSFET pinout for design flexibility RoHS ompliant Pin SO- MOSFET Maximum Ratings T = 5 unless otherwise noted Thermal haracteristics S G General escription pril 00 The FFSP753Z offers a single package solution for / conversion. It combines an excellent Fairchild s PowerTrench MOSFET with a Schottky diode in an SO- package. The MOSFET features a low on-state resistance and an optimized gate charge to achieve fast switching. The independently connected Schottky diode has a low forward voltage drop to minimize power loss. This device is an Ideal - solution for up to 3 peak load current. pplications - onversion Symbol Parameter Ratings Units V S rain to Source Voltage -30 V V GS Gate to Source Voltage ±5 V I rain urrent -ontinuous (Note a) -3 -Pulsed -6 Power issipation T P = 5 3. Power issipation T = 5 (Note a).6 W E S Single Pulse valanche Energy (Note ) 6 mj V RRM Schottky Repetitive Peak Reverse Voltage 30 V I O Schottky verage Forward urrent T J, T STG Operating and Storage Junction Temperature Range -55 to G S tm R θj Thermal Resistance, Junction to ase (Note ) 0 R θj Thermal Resistance, Junction to mbient (Note a) 7 Package Marking and Ordering Information /W evice Marking evice Package Reel Size Tape Width Quantity FFSP753Z FFSP753Z SO- 330mm mm 500units

2 Electrical haracteristics T J = 5 unless otherwise noted Symbol Parameter Test onditions Min Typ Max Units Off haracteristics BV SS rain to Source Breakdown Voltage I = -50µ, V GS = 0V -30 V BV SS Breakdown Voltage Temperature I T J oefficient = -50µ, referenced to 5 - mv/ V S = -V, - I SS Zero Gate Voltage rain urrent µ V GS = 0V T J = 5-00 I GSS Gate to Source Leakage urrent V GS = ±5V, V S = 0V ±0 µ On haracteristics V GS(th) Gate to Source Threshold Voltage V GS = V S, I = -50µ V V GS(th) Gate to Source Threshold Voltage T J Temperature oefficient I = -50µ, referenced to 5 5 mv/ V GS = -0V, I = r S(on) Static rain to Source On Resistance V GS = -.5V, I = mω V GS = -0V, I = -3.0, T J = g FS Forward Transconductance V = -5V, I = S ynamic haracteristics iss Input apacitance pf V S = -5V, V GS = 0V, oss Output apacitance 60 0 pf f = MHz rss Reverse Transfer apacitance pf R g Gate Resistance f = MHz Ω Switching haracteristics t d(on) Turn-On elay Time 6 ns V = -5V, I = -3.0, t r Rise Time 0 ns V GS = -0V, R GEN = 6Ω t d(off) Turn-Off elay Time 9 3 ns t f Fall Time 5 7 ns Q g Total Gate harge V GS = 0V to -0V n V = -5V, Q g Total Gate harge V GS = 0V to -.5V. 5.7 n I = -3.0 Q gs Gate to Source harge.3 n Q gd Gate to rain Miller harge.0 n rain-source iode haracteristics V S Source to rain iode Forward Voltage V GS = 0V, I S = -.0 (Note 3) V t rr Reverse Recovery Time 0 30 ns I F = -3.0, di/dt = 00/µs Q rr Reverse Recovery harge n Schottky iode haracteristics V R Reverse Breakdown Voltage I R = m 30 V T J = µ I R Reverse Leakage V R = 0V T J = 5 m T J = I F = 00m T J = 5 0 V F Forward Voltage mv T J = I F = T J = 5 90

NOTES:.R θj is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.

3 NOTES:.R θj is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θj is guaranteed by design while R θ is determined by the user s board design.. Starting T J = 5, L = 3 mh, I S = -, V = -7V, V GS = -0V. 3. Pulse Test: Pulse Width < 300µs, uty cycle <.0%. a. 7 /W when mounted on a 0.5 in pad of oz copper. b. 35 /W when mounted on a minimum pad of oz copper. 3

4 Typical haracteristics T J = 5 unless otherwise noted -I, RIN URRENT () NORMLIZE RIN TO SOURE ON-RESISTNE -I, RIN URRENT () 6 PULSE URTION = 0µs UTY YLE = 0.5%MX Figure. V GS = -0V V GS = -5V V GS = -.5V V GS = - V V GS = -3.5V -V S, RIN TO SOURE VOLTGE (V) NORMLIZE RIN TO SOURE ON-RESISTNE On-Region haracteristics Figure. Normalized On-Resistance vs rain urrent and Gate Voltage T J, JUNTION TEMPERTURE ( o ) Figure 3. Normalized On- Resistance vs Junction Temperature 6 I = -3 V GS = -0V PULSE URTION = 0µs UTY YLE = 0.5%MX V = -5V T J = 50 o T J = -55 o V GS, GTE TO SOURE VOLTGE (V) rs(on), RIN TO SOURE ON-RESISTNE (mω) -IS, REVERSE RIN URRENT () Figure. V GS = -3.5V PULSE URTION = 0µs UTY YLE = 0.5%MX V GS = -V V GS = -.5XV V GS = -0V -I, RIN URRENT() V GS = -5V PULSE URTION = 0µs UTY YLE = 0.5%MX T J = 50 o I = V GS, GTE TO SOURE VOLTGE (V) V GS = 0V T J = 50 o On-Resistance vs Gate to Source Voltage T J = -55 o V S, BOY IOE FORWR VOLTGE (V) Figure 5. Transfer haracteristics Figure 6. Source to rain iode Forward Voltage vs Source urrent

5 Typical haracteristics T J = 5 unless otherwise noted -VGS, GTE TO SOURE VOLTGE(V) -IS, VLNHE URRENT() -I, RIN URRENT () 0 6 I = Figure V = -0V V = -5V Q g, GTE HRGE(n) V = -0V V S, RIN TO SOURE VOLTGE (V) Gate harge haracteristics Figure. apacitance vs rain to Source Voltage t V, TIME IN VLNHE(ms) Figure 9. Unclamped Inductive Switching apability R θj = 7 o /W V GS = -0V V GS = -.5V T, MBIENT TEMPERTURE ( o ) -Ig, GTE LEKGE URRENT() PITNE (pf) -I, RIN URRENT () Figure 0. f = MHz V GS = 0V iss oss rss V GS, GTE TO SOURE VOLTGE(V) Gate Leakage urrent vs Gate to Source Volatge THIS RE IS LIMITE BY r S(on) SINGLE PULSE T J = MX RTE R θj = 35 o /W T = 5 o V S, RIN to SOURE VOLTGE (V) ms 0ms 00ms s 0s 30 0 Figure. Maximum ontinuous rain urrent vs mbient Temperature Figure. Forward Bias Safe Operating rea 5

6 Typical haracteristics T J = 5 unless otherwise noted IF, FORWR URRENT() V F, FORWR VOLTGE(V) Figure 3. P (PK), PEK TRNSIENT POWER (W) NORMLIZE THERML IMPENE, Z θj 50 0 Schottky iode Forward Voltage V GS = -0V Figure 5. IR, REVERSE LEKGE URRENT (m) V R, REVERSE VOLTGE (V) Figure. Schottky iode Reverse urrent SINGLE PULSE R θj = 35 o /W T = 5 o UTY YLE-ESENING ORER = SINGLE PULSE R θj = 35 o /W t, PULSE WITH (s) Single Pulse Maximum Power issipation t, RETNGULR PULSE URTION (s) P M t t NOTES: UTY FTOR: = t /t PEK T J = P M x Z θj x R θj + T Figure 6. Transient Thermal Response urve 6

7 tm tm tm TREMRKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidianries, and is not intended to be an exhaustive list of all such trademarks. Ex Build it Now oreplus orepower ROSSVOLT TL urrent Transfer Logic EcoSPRK EfficentMax EZSWITH * Fairchild Fairchild Semiconductor FT Quiet Series FT FST Fastvore FlashWriter * FPS F-PFS FRFET Global Power Resource SM Green FPS Green FPS e-series GTO IntelliMX ISOPLNR MegaBuck MIROOUPLER MicroFET MicroPak Millerrive MotionMax Motion-SPM OPTOLOGI OPTOPLNR * EZSWITH and FlashWriter are trademarks of System General orporation, used under license by Fairchild Semiconductor. ISLIMER FIRHIL SEMIONUTOR RESERVES THE RIGHT TO MKE HNGES WITHOUT FURTHER NOTIE TO NY PROUTS HEREIN TO IMPROVE RELIBILITY, FUNTION, OR ESIGN. FIRHIL OES NOT SSUME NY LIBILITY RISING OUT OF THE PPLITION OR USE OF NY PROUT OR IRUIT ESRIBE HEREIN; NEITHER OES IT ONVEY NY LIENSE UNER ITS PTENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPEIFITIONS O NOT EXPN THE TERMS OF FIRHIL S WORLWIE TERMS N ONITIONS, SPEIFILLY THE WRRNTY THEREIN, WHIH OVERS THESE PROUTS. LIFE SUPPORT POLIY FIRHIL S PROUTS RE NOT UTHORIZE FOR USE S RITIL OMPONENTS IN LIFE SUPPORT EVIES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN PPROVL OF FIRHIL SEMIONUTOR ORPORTION. s used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. PP-SPM Power-SPM PowerTrench Programmable ctive roop QFET QS Quiet Series Rapidonfigure Saving our world mw at a time SmartMax SMRT STRT SPM STELTH SuperFET SuperSOT -3 SuperSOT -6 SuperSOT - SuperMOS The Power Franchise TinyBoost TinyBuck TinyLogic TINYOPTO TinyPower TinyPWM TinyWire µseres UH Ultra FRFET UniFET VX VisualMax. critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PROUT STTUS EFINITIONS efinition of Terms atasheet Identification Product Status efinition dvance Information Preliminary No Identification Needed Obsolete Formative or In esign First Production Full Production Not In Production This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design. This datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only. Rev. I3

Features 3.3 A, 20 V. V F < A (T J = 125 o C). V F < A. V F < A. TA=25 o C unless otherwise noted

Features 3.3 A, 20 V. V F < A (T J = 125 o C). V F < A. V F < A. TA=25 o C unless otherwise noted FFSP Integrated P-hannel MOSFET and Schottky iode October FFSP General escription The FFSP combines the exceptional performance of Fairchild's high cell density MOSFET with a very low forward voltage drop