FDFS6N754. FDFS6N754 Integrated N-Channel PowerTrench MOSFET and Schottky Diode

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Final atasheet ugust FFSN7 Integrated N-hannel PowerTrench MOSFET and Schottky iode V,, mω Features Max r S(on) = mω at V GS = V, = Max r S(on) = 7mΩ at V GS =.V, =. V F <.V @ V F <.

1 Final atasheet ugust FFSN7 Integrated N-hannel PowerTrench MOSFET and Schottky iode V,, mω Features Max r S(on) = mω at V GS = V, = Max r S(on) = 7mΩ at V GS =.V, =. V F V F m Schottky and MOSFET incorporated into single power surface mount SO- package Electrically independent Schottky and MOSFET pinout for design flexibility Low Gate harge (Qg = n) Low Miller harge SO- Pin MOSFET Maximum Ratings T = unless otherwise noted S G General escription The FFSN7 combines the exceptional performance of Fairchild's PowerTrench MOSFET technology with a very low forward voltage drop Schottky barrier rectifier in an SO- package. This device is designed specifically as a single package solution for to converters. It features a fast switching, low gate charge MOSFET with very low on-state resistance. The independently connected Schottky diode allows its use in a variety of / converter topologies. pplications / converters Symbol Parameter Ratings Units V S rain to Source Voltage V V GS Gate to Source Voltage ± V rain urrent -ontinuous (Note a) -Pulsed Power issipation for ual Operation P Power issipation for Single Operation (Note a). V RRM Schottky Repetitive Peak Reverse Voltage V I O Schottky verage Forward urrent (Note a) T J, T STG Operating and Storage Temperature - to S G 7 W tm Thermal haracteristics R θj Thermal Resistance, Junction-to-mbient (Note a) 7 /W R θj Thermal Resistance, Junction-to-ase (Note ) /W Package Marking and Ordering Information evice Marking evice Package Reel Size Tape Width Quantity FFSN7 FFSN7 SO- mm mm units Fairchild Semiconductor orporation

2 Electrical haracteristics T J = unless otherwise noted Symbol Parameter Test onditions Min Typ Max Units Off haracteristics BV SS rain to Source Breakdown Voltage = µ, V GS = V V BV SS T J SS Breakdown Voltage Temperature oefficient Zero Gate Voltage rain urrent On haracteristics (Note ) = µ, referenced to V S = V V GS = V. mv/ T J = I GSS Gate to Source Leakage urrent V GS = ±V, V S = V ± n V GS(th) Gate to Source Threshold Voltage V S = V GS, = µ.7. V V GS(th) T J r S(on) Gate to Source Threshold Voltage Temperature oefficient rain to Source On Resistance = µ, referenced to -. mv/ V GS = V, = V GS =.V, =. 7 mω V GS = V, =, T J = g FS Forward Transconductance V S = V, = S ynamic haracteristics iss Input apacitance 99 pf V S = V, V GS = V, oss Output apacitance 7 pf f =.MHz rss Reverse Transfer apacitance pf R G Gate Resistance f =.MHz. Ω Switching haracteristics (Note ) t d(on) Turn-On elay Time ns t r Rise Time V = V, = ns t d(off) Turn-Off elay Time V GS = V, R GS = Ω ns t f Fall Time ns Q g(tot) Total Gate harge at V V S = V, n Q g() Total Gate harge at V = n Q gs Gate to Source Gate harge. n Q gd Gate to rain Miller harge n rain-source iode haracteristics and Maximum Ratings V S Source to rain iode Forward Voltage V GS = V, I S =. (Note ).. V t rr Reverse Recovery Time I F =, di/dt = /µs ns Q rr Reverse Recovery harge I F =, di/dt = /µs n Schottky iode haracteristics V R Reverse Breakdown Voltage I R = -m - V T J = o 9 µ I R Reverse Leakage V R = -V T J = o m T J = o I F = m T J = o V F Forward Voltage mv T J = o I F = T J = o 9 µ

3 Notes: : R θj is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θj is guaranteed by design while R θ is determined by the user s board design. a) 7 /W when mounted on a.in pad of oz copper Scale : on letter size paper : Pulse Test: Pulse Width < µs, uty ycle <.%. b) /W when mounted on a. in pad of oz copper c) /W when mounted on a minimun pad

4 Typical haracteristics T J = unless otherwise noted, RIN URRENT () NORMLIZE RIN TO SOURE ON-RESISTNE, RIN URRENT () V GS = V V GS = V V GS = V Figure V GS =.V PULSE URTION = µs UTY YLE =.%MX V GS =.V V GS = V V GS =.V V S, RIN TO SOURE VOLTGE (V) On Region haracteristics Figure Figure. = V GS = V T J, JUNTION TEMPERTURE ( o ) NORMLIZE RIN TO SOURE ON-RESISTNE On Resistance vs Temperature Figure. PULSE URTION = µs UTY YLE =.%MX V S = V T J = o T J = - o T J = o V GS, GTE TO SOURE VOLTGE (V) r S(on), RIN TO IS, REVERSE RIN URRENT () SOURE ON-RESISTNE (mω).... V GS =.V V GS =.V PULSE URTION = µs UTY YLE =.%MX V GS = V V GS =.V V GS = V V GS = V, RIN URRENT() On-Resistance vs rain urrent and Gate Voltage = PULSE URTION = µs UTY YLE =.%MX T J = o T J = o... V GS = V V GS, GTE TO SOURE VOLTGE (V) On-Resistance vs Gate to Source Voltage T J = o T J = o T J = - o E V S, BOY IOE FORWR VOLTGE (V) Figure. Transfer haracteristics Figure. Source to rain iode Forward Voltage vs Source urrent

5 Typical haracteristics T J = unless otherwise noted VGS, GTE TO SOURE VOLTGE (V) IS, VLNHE URRENT(), RIN URRENT () V = V V = V V = V Q g, GTE HRGE (n) Figure 7. Gate harge haracteristics 9 7 T J = o.. t V, TIME IN VLNHE(ms) Figure 9. Unclamped Inductive Switching apability. OPERTION IN THIS SINGLE PULSE RE MY BE T J = MX RTE. LIMITE BY r S(on) T = O. V S, RIN-SOURE VOLTGE (V) us us ms ms ms s s Figure. Forward Bias Safe Operating rea PITNE (pf) rss oss iss. V S, RIN TO SOURE VOLTGE (V) f = MHz V GS = V Figure. apacitance vs rain to Source Voltage I, RIN URRENT () R θj = o /W V GS =.V V GS = V 7 T, SE TEMPERTURE ( o ) Figure. Maximum ontinuous rain urrent vs ase Temperature ), PEK TRNSIENT POWER (W) P(PK V GS = V SINGLE PULSE T = o FOR TEMPERTURES BOVE o ERTE PEK URRENT S FOLLOWS: T I = I t, PULSE WITH (s) Figure. Single Pulse Maximum Power issipation

6 Typical haracteristics T J = unless otherwise noted I F, FORWR LEKGE URRENT () NORMLIZE THERML IMPENE, Z θj.. E V F, FORWR VOLTGE (V) Figure.. T J = o T J = o. E- E- E- Schottky iode Forward Voltage Figure. UTY YLE-ESENING ORER = SINGLE PULSE I R, REVERSE LEKGE URRENT (). Figure. Transient Thermal Response urve T J = o T J = o E- V R, REVERSE VOLTGE(V) Schottky iode Reverse urrent t, RETNGULR PULSE URTION (s) P M t t NOTES: UTY FTOR: = t /t PEK T J = P M x Z θj x R θj + T

7 TREMRKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. Ex ctiverray Bottomless Build it Now oolfet ROSSVOLT OME EcoSPRK E MOS EnSigna FT FST FSTr FPS FRFET FT Quiet Series GlobalOptoisolator GTO HiSe I i-lo Impliedisconnect IntelliMX ISOPLNR LittleFET MIROOUPLER MicroFET MicroPak MIROWIRE MSX MSXPro cross the board. round the world. The Power Franchise Programmable ctive roop ISLIMER FIRHIL SEMIONUTOR RESERVES THE RIGHT TO MKE HNGES WITHOUT FURTHER NOTIE TO NY PROUTS HEREIN TO IMPROVE RELIBILITY, FUNTION OR ESIGN. FIRHIL OES NOT SSUME NY LIBILITY RISING OUT OF THE PPLITION OR USE OF NY PROUT OR IRUIT ESRIBE HEREIN; NEITHER OES IT ONVEY NY LIENSE UNER ITS PTENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPEIFITIONS O NOT EXPN THE TERMS OF FIRHIL S WORLWIE TERMS N ONITIONS, SPEIFILLY THE WRRNTY THEREIN, WHIH OVERS THESE PROUTS. LIFE SUPPORT POLIY FIRHIL S PROUTS RE NOT UTHORIZE FOR USE S RITIL OMPONENTS IN LIFE SUPPORT EVIES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN PPROVL OF FIRHIL SEMIONUTOR ORPORTION. s used herein:. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.. critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PROUT STTUS EFINITIONS efinition of Terms atasheet Identification Product Status efinition dvance Information Formative or In esign OX OXPro OPTOLOGI OPTOPLNR PMN POP Power7 PowerEdge PowerSaver PowerTrench QFET QS QT Optoelectronics Quiet Series Rapidonfigure Rapidonnect µseres ScalarPump SILENT SWITHER SMRT STRT SPM Stealth SuperFET SuperSOT - SuperSOT - SuperSOT - SyncFET TM TinyBoost TinyBuck TinyPWM TinyPower TinyLogic TINYOPTO TruTranslation UH UniFET UltraFET VX Wire This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I 7

FDFS2P753Z Integrated P-Channel PowerTrench MOSFET and Schottky Diode

FDFS2P753Z Integrated P-Channel PowerTrench MOSFET and Schottky Diode FFSP753Z Integrated P-hannel PowerTrench MOSFET and Schottky iode -30V, -3, 5mΩ Features Max r S(on) = 5mΩ at V GS = -0V, I = -3.0 Max r S(on) = 0mΩ at V GS = -.5V, I = -.5 V F < 500mV @ V F < 50mV @ Schottky