Dual N & P-Channel Enhancement Mode Field Effect Transistor. Features R DS(ON) = V GS = 4.5 V G2 6 Q1(N) TA=25 o C unless otherwise noted

Size: px

Start display at page:

Download "Dual N & P-Channel Enhancement Mode Field Effect Transistor. Features R DS(ON) = V GS = 4.5 V G2 6 Q1(N) TA=25 o C unless otherwise noted"

Benedict Dennis
5 years ago
Views:

Dual N & P-Channel Enhancement Mode Field Effect Transistor May General Description These dual N & P-Channel Enhancement Mode Field Effect Transistors are produced using Fairchild s proprietary, high

1 Dual N & P-Channel Enhancement Mode Field Effect Transistor May General Description These dual N & P-Channel Enhancement Mode Field Effect Transistors are produced using Fairchild s proprietary, high cell density, DMOS technology. This very high density process has been designed to minimize on-state resistance, provide rugged and reliable performance and fast switching. These device is particularly suited for low voltage, low current, switching, and power supply applications. Features Q.5 A,. R DS(ON) = GS = R DS(ON) = GS =.5 Q.3 A,. R DS(ON) = 5 GS = R DS(ON) = GS =.5 High saturation current High density cell design for low R DS(ON) Proprietary SuperSOT TM package: design using copper lead frame for superior thermal and electrical capabilities S D D Q(P) 3 5 TM SuperSOT - G S G Q(N) Absolute Maximum Ratings TA=5 o C unless otherwise noted Symbol Parameter Q Q Units DSS Drain-Source oltage GSS Gate-Source oltage ± ± I D Drain Current Continuous (Note a).5.3 A P D Pulsed.5 Power Dissipation for Single Operation (Note a).9 (Note b).9 (Note c).7 T J, T STG Operating and Storage Junction Temperature Range 55 to +5 C Thermal Characteristics R θja Thermal Resistance, Junction-to-Ambient (Note a) 3 C/W R θjc Thermal Resistance, Junction-to-Case (Note ) Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity.C 7 8mm 3 W Fairchild Semiconductor Corporation Rev B (W)

2 Electrical Characteristics T A = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics B DSS Drain Source Breakdown oltage GS =, I D = 5 µa Q GS =, I D = 5 µa Q BDSS T J Breakdown oltage Temperature Coefficient I D = 5 µa,ref. to 5 C I D = 5 µa,ref. to 5 C Q Q 7 57 m/ C I DSS Zero Gate oltage Drain Current DS = 8, GS = Q µa DS = 8, GS = Q I GSSF Gate Body Leakage, Forward GS =, DS = All na I GSSR Gate Body Leakage, Reverse GS =, DS = All na On Characteristics (Note ) GS(th) Gate Threshold oltage Q DS = GS, I D = 5 µa..5 Q DS = GS, I D = 5 µa GS(th) Gate Threshold oltage Q I D = 5 µa,referenced. to 5 C 3.8 T J Temperature Coefficient Q I D = 5 µa,ref. to 5 C 3. R DS(on) Static Drain Source Q GS =, I D =.5 A On Resistance GS =.5, I D =.35 A GS =, I D =.5 A,T J=5 C Q GS =, I D =.3 A GS =.5,I D =.5 A GS =,I D=.3A,T J=5 C I D(on) On-State Drain Current Q GS = DS =.5 Q GS = DS = g FS Forward Transconductance Q DS = I D =.5 A 38 Q DS = I D =.3A 7 Dynamic Characteristics C iss Input Capacitance Q For Q: Q DS = 5, GS = C oss Output Capacitance Q f =.MHz Q For Q: 3 C rss Reverse Transfer Capacitance Q DS = 5, GS =.3 Q f =.MHz R G Gate Resistance Q GS = 5 m, f =. MHz. Ω Q. Switching Characteristics (Note ) t d(on) Turn On Delay Time Q For Q:.8 5. Q DS =5, I DS= A 3.. t r Turn On Rise Time Q GS=, R GEN = Ω 8 Q For Q: t d(off) Turn Off Delay Time Q DS = 5, I DS= A Q GS=, R GEN = Ω 8 t f Turn Off Fall Time Q 8 Q Q g Total Gate Charge Q For Q:..5 Q DS =5, I DS=.5 A.. Q gs Gate Source Charge Q GS=, R GEN = Ω. Q For Q:.3 DS = 5, I DS=.35 A Q gd Gate Drain Charge Q. GS=, R GEN = Ω Q m/ C Ω A ms pf pf pf ns ns ns ns nc nc nc Rev B (W)

3 Electrical Characteristics T A = 5 C unless otherwise noted Symbol Parameter Test Conditions Min Typ Max Units Drain Source Diode Characteristics and Maximum Ratings I S Maximum Continuous Drain Source Diode Forward Current Q.5 A Q.3 SD Drain Source Diode Forward Q GS =, I S =.5 A (Note ).8. oltage Q GS =, I S =.3 A (Note ).8. t rr Diode Reverse Recovery Q I F =.5 A, d if/d t = A/µs 8 Time Q I F =.3 A, d if/d t = A/µs Q rr Diode Reverse Recovery Q I F =.5 A, d if/d t = A/µs Charge Q I F =.3 A, d if/d t = A/µs ns nc Notes:. R θja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θjc is guaranteed by design while R θca is determined by the user's board design. a) 3 C/W when mounted on a.5 in pad of oz. copper. b) C/W when mounted on a.5 in pad of oz copper c) 8 C/W when mounted on a minimum pad. Scale : on letter size paper. Pulse Test: Pulse Width < 3µs, Duty Cycle <.% Rev B (W)

4 Typical Characteristics: N-Channel.5 GS = 8.. I D, DRAIN CURRENT (A) R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE GS = DS, DRAIN-SOURCE OLTAGE () I D, DRAIN CURRENT (A) Figure. On-Region Characteristics. Figure. On-Resistance ariation with Drain Current and Gate oltage. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D =.5A GS = R DS(ON), ON-RESISTANCE (OHM) 5 3 T A = 5 o C T A = 5 o C I D =.A T J, JUNCTION TEMPERATURE ( o C) 8 GS, GATE TO SOURCE OLTAGE () Figure 3. On-Resistance ariation withtemperature. Figure. On-Resistance ariation with Gate-to-Source oltage. I D, DRAIN CURRENT (A) DS = 5 T A =-55 o C 5 o C 5 o C I S, REERSE DRAIN CURRENT (A)... GS = T A = 5 o C 5 o C -55 o C GS, GATE TO SOURCE OLTAGE () SD, BODY DIODE FORWARD OLTAGE () Figure 5. Transfer Characteristics. Figure. Body Diode Forward oltage ariation with Source Current and Temperature. Rev B (W)

5 Typical Characteristics: N-Channel (continued) GS, GATE-SOURCE OLTAGE () 8 I D =.5A DS = Q g, GATE CHARGE (nc) CAPACITANCE (pf) 5 f = MHz GS = 3 C ISS C OSS C RSS 3 5 DS, DRAIN TO SOURCE OLTAGE () Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. I D, DRAIN CURRENT (A). R DS(ON) LIMIT GS = R θja = 8 o C/W T A = 5 o C µs µs ms ms ms s DC P(pk), PEAK TRANSIENT POWER (W) 8 R θja = 8 C/W T A = 5 C.. DS, DRAIN-SOURCE OLTAGE ()... t, TIME (sec) Figure 9. Maximum Safe Operating Area. Figure. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIE TRANSIENT THERMAL RESISTANCE.. D = t, TIME (sec) R θja (t) = r(t) * R θja R θja = 8 C/W P(pk) t t T J - T A = P * R θja (t) Duty Cycle, D = t / t Figure. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note c. Transient thermal response will change depending on the circuit board design. Rev B (W)

6 Typical Characteristics: P-Channel GS = I D, DRAIN CURRENT (A) R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE.8... GS = DS, DRAIN TO SOURCE OLTAGE () I D, DRAIN CURRENT (A) Figure. On-Region Characteristics. Figure. On-Resistance ariation with Drain Current and Gate oltage. R DS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE I D = -.3A GS = - R DS(ON), ON-RESISTANCE (OHM) 5 3 T A = 5 o C T A = 5 o C I D = -.7A T J, JUNCTION TEMPERATURE ( o C) 8 - GS, GATE TO SOURCE OLTAGE () Figure 3. On-Resistance ariation withtemperature. Figure. On-Resistance ariation with Gate-to-Source oltage. -I D, DRAIN CURRENT (A) T A = -55 o C 5 o DS = -5 C.8 5 o C GS, GATE TO SOURCE OLTAGE () -I S, REERSE DRAIN CURRENT (A) GS = T A = 5 o C. 5 o C. -55 o C SD, BODY DIODE FORWARD OLTAGE () Figure 5. Transfer Characteristics. Figure. Body Diode Forward oltage ariation with Source Current and Temperature. Rev B (W)

7 Typical Characteristics: P-Channel (continued) - GS, GATE-SOURCE OLTAGE () I D = -.3A DS = CAPACITANCE (pf) 8 C RSS C OSS C ISS f = MHz GS =..8.. Q g, GATE CHARGE (nc) DS, DRAIN TO SOURCE OLTAGE () Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. -I D, DRAIN CURRENT (A).. R DS(ON) LIMIT GS = - R θja = 8 o C/W T A = 5 o C ms s DC ms ms µs - DS, DRAIN-SOURCE OLTAGE () P(pk), PEAK TRANSIENT POWER (W) 8... t, TIME (sec) R θja = 8 C/W T A = 5 C Figure 9. Maximum Safe Operating Area. Figure. Single Pulse Maximum Power Dissipation. r(t), NORMALIZED EFFECTIE TRANSIENT THERMAL RESISTANCE.. D = t, TIME (sec) Figure. Transient Thermal Response Curve. R θja (t) = r(t) * R θja R θja = 8 C/W P(pk) Thermal characterization performed using the conditions described in Note c. Transient thermal response will change depending on the circuit board design. t t T J - T A = P * R θja (t) Duty Cycle, D = t / t Rev B (W)

8 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks ACEx Bottomless CoolFET CROSSOLT DenseTrench DOME EcoSPARK E CMOS TM EnSigna TM FACT FACT Quiet Series STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROE RELIABILITY, FUNCTION OR DESIGN FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROAL OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein: Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user PRODUCT STATUS DEFINITIONS Definition of Terms FAST â FASTr FRFET GlobalOptoisolator GTO HiSeC I C ISOPLANAR LittleFET MicroFET MicroPak MICROWIRE OPTOLOGIC â OPTOPLANAR PACMAN POP Power7 PowerTrench QFET QS A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness Datasheet Identification Product Status Definition â QT Optoelectronics Quiet Series SILENT SWITCHER â SMART START SPM STAR*POWER Stealth SuperSOT -3 SuperSOT - SuperSOT -8 SyncFET TinyLogic TruTranslation UHC UltraFET â CX Advance Information Preliminary No Identification Needed Formative or In Design First Production Full Production This datasheet contains the design specifications for product development Specifications may change in any manner without notice This datasheet contains preliminary data, and supplementary data will be published at a later date Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design This datasheet contains final specifications Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor The datasheet is printed for reference information only Rev H5

9 Mouser Electronics Authorized Distributor Click to iew Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor: _Q

Features. R DS(on) = 25 C unless otherwise noted. Symbol Parameter Q2 Q1 Units

Features. R DS(on) = 25 C unless otherwise noted. Symbol Parameter Q2 Q1 Units Dual Notebook Power Supply N-Channel PowerTrench SyncFet September General Description The is designed to replace two single SO-8 MOSFETs and Schottky diode in synchronous DC:DC power supplies that provide