ESA-ESTEC GSTP4 - Analog Silicon Compiler for Mixed Signal ASICs. PDFE: A Particle Detector Front-End ASIC
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1 ESA-ESTEC GSTP4 - Analog Silicon Compiler for Mixed Signal ASICs PDFE: A Particle Detector Front-End ASIC
2 PDFE: collaborators z PDFE is the result of a collaboration between ESA-Estec S. Habinc, B. Johlander, T. Sanderson KULeuven, ESAT-MICAS G. Gielen, J. Vandenbussche, G. Van der Plas IMEC, Invomec C. Das, K. Marent, S. Redant, J. Wouters z PDFE is designed by IMEC, Invomec Final presentation ESA-ESTEC 7/3/2001 J. Wouters 2
3 z Basic functionality z Concept z PDFE characteristics: functionalities block diagram specs programmability Presentation overview z Some analog cells z Digital part z Simulations z Radiation hardness z Evaluation PCB s & some measurement results z Status & Conclusions Final presentation ESA-ESTEC 7/3/2001 J. Wouters 3
4 Basic functionality z CSA z PSA z Peak detection z DAC and discriminator z ADC Q V V t t t CSA V Se nso r PSA Peak detect & ho ld ADC 8 t 8 DAC Final presentation ESA-ESTEC 7/3/2001 J. Wouters 4
5 Basic functionality: 1 conversion cycle z One full cycle takes 4 s Final presentation ESA-ESTEC 7/3/2001 J. Wouters 5
6 Concept z Miniaturized Microcontroller based Read-out Electronics for Space Application (Energetic Particle Instrumentation) z PDFE together with a 8052-based Microcontroller z Architectural design drivers: Low noise, low power Low mass Low chip count Single supply voltage simple power supply Integrated ADC Integrated standard space craft interface Re-usability and scalability because high NRE cost & long development time Tolerance against single event effects and total ionizing dose Mixed analog and digital signals Testability and reliability (monolithic) Final presentation ESA-ESTEC 7/3/2001 J. Wouters 6
7 Main PDFE functionalities z Main channel: charge amp, pulse shaping, baseline restorer, peak detector S/H z (Anti-)coincidence channel z Internal or external (anti-)coincidence gating z Build-in 8-bit discriminators z Gain adjustment (+/-5%) z Linear 8-bit ADC, two-step flash z Completely event driven z Cascadable 32 bits serial control/status interface (scalability) z 8-bit parallel output interface z All internal registers SEU protected z Low speed low amplitude digital I/O (to limit noise) z Non-active blocks powered down Final presentation ESA-ESTEC 7/3/2001 J. Wouters 7
8 PDFE block diagram Final presentation ESA-ESTEC 7/3/2001 J. Wouters 8
9 Main specifications z Detector capa 100 pf z Detector leakage 1 na z Full Scale input 0.1 pc z Conversion gain 30 mv/fc z Noise (ENC) 800 e - rms (@ 100 pf) z Peaking time 1 s z Counting rate fc pc z Baseline drift 15 mv z Nonlinearity 1 LSB z Number of channels 2 z ADC resolution 8 bit z ADC INL and DNL ½ LSB z Power supply 5 V z Power consumption One channel: 15 mw ADC: 30 mw Total: 70 mw z Ambient temperature -40 to 65 C z Technology 0.7- m CMOS, mixed-signal, Alcatel Microelectronics z Package 64-pins quad flat pack 56 pins used Final presentation ESA-ESTEC 7/3/2001 J. Wouters 9
10 Programmability z Using the serial control/status interface Coincidence channel enable/disable Coincidence or anti-coincidence gating Internal or external coincidence input Discriminator levels (two 8-bit DACs) Conversion gain adjustment (+/-5%) ADC stand-alone Power down z Using digital pins (VSS - VDD strapped) Charge sign Analog or digital (ADC) output Parallel output interface (ADC): internal or external control of the update (non-latching or latching mode; PROM or P bus) Final presentation ESA-ESTEC 7/3/2001 J. Wouters 10
11 An Instrument on a Chip Final presentation ESA-ESTEC 7/3/2001 J. Wouters 11
12 z CSA Charge sensitive amplifier Integrates a charge pulse, into a voltage step Input transistor: minimum noise (1/f & thermal): W/L=10,000 /0.9 I=1.8mA Analog circuits / 1 R Cf In Ou t De lta Vo ut= Qin*Cf Final presentation ESA-ESTEC 7/3/2001 J. Wouters 12
13 Analog circuits / 2 z Shaper (PSA, Pulse Shaping Amplifier) Gm-C bandpass filter Optimises noise performance and counting rate first-order high pass (differentiation) second-order low pass Rpz: pole-zero cancellation voutdc: sets output DC level; used by the BaselineRestorer Final presentation ESA-ESTEC 7/3/2001 J. Wouters 13
14 z Channel Input: charge pulse Output: semi-gaussian pulse Csa, shaper, baseline restorer Analog circuits / 3 Cext: pin for external capacitor, 100nF. 1. to minimize the effect of the BR on pulses 2. to get a dominant (low frequent) pole Also rail-clipping at the gm output filters pulses (and passes DC); non-linear filtering! Final presentation ESA-ESTEC 7/3/2001 J. Wouters 14
15 z DDA Differential difference amplifier Used to levelshift and invert without resistors (hence low power) Analog circuits / 4 Vp p Vp n Vn p Vo ut Vn n Vo ut= Ao l*[(vpp-vpn)-(vnp-vn n)] Final presentation ESA-ESTEC 7/3/2001 J. Wouters 15
16 z Peak Detector Sample&Hold Current I: 30nA, to counter potential upward drift (fundamental for a PD) I is switched off during ADC Analog circuits / 5 Final presentation ESA-ESTEC 7/3/2001 J. Wouters 16
17 z Comparator Analog circuits / 6 Very fast: 10mV differential input Because node b cannot move far Final presentation ESA-ESTEC 7/3/2001 J. Wouters 17
18 z ClassAB opamp Analog circuits / 7 Only capacitive loads. Drives ADC and/or analog output. Output stage quiescent current is well controlled, for low power Standard cells: not OK: (internal) slew rate too low power too high Final presentation ESA-ESTEC 7/3/2001 J. Wouters 18
19 z Architecture: Two-step flash 4 MSB s first; then 4 LSB s ADC / 1 Two resistive ladders, 16 units each coarse ladder low resistive fine ladder high resistive Comparators CMOS : Vos = 10 mv (3-sigma) 1LSB = 11 mv auto - zeroing necessary 250 K conversions/s 30 mw Final presentation ESA-ESTEC 7/3/2001 J. Wouters 19
20 ADC / 2 z Clocked comparator Auto-zeroing (or correlated double sampling) Only possible because no continuous operation Offset < 100 V Final presentation ESA-ESTEC 7/3/2001 J. Wouters 20
21 ADC / 3 z Measurement results LabVIEW / GPIB setup ADC stand-alone DNL = 0.32 LSB INL = 0.34 LSB Final presentation ESA-ESTEC 7/3/2001 J. Wouters 21
22 z Serial interface, 32 bits Control (input) operating modes various controls (e.g. gain) discriminator levels Status (output) voting & parity errors some pin settings Cascadability (scalability) Digital part z Parallel output (ADC). Latching or none-latching. z 4 MHz clock, 1500 equivalent gates, VHDL, decoding&control z To minimize disturbances of the analog event driven (PDFE quite, except some 30 FF s, until peak latched) I/O: TLL, very long rise & fall times Final presentation ESA-ESTEC 7/3/2001 J. Wouters 22
23 Mixed mode simulations / 1 z Table with main functional modes Z:\pdfe\pdfeTablexx.xx.99 Excel PDFE : modes Rev RESET_N (pin) Main DAC, ED / EDOn Main chan / PSACSAOn Bit10 Bit9 Bit8 AOutSel (pin) Test (pin) Coinc chan, DAC, ED / CDOn External coincidence XCoInIsReload ADCMode CoEDDirect EDDirect driftcomp Reload quiet BypassAAF Extinp (=~ PSACSAOnB) ADC / ADCOn Buffer / BUFOn PDSH / PDSHOn Input signals power up / signals to ana digital set Anti-coincidence Description X 0 EN EN Coincidence detection mode; anti-coincidence mode; digital out Default mode X 0 EN EN Coincidence detection mode; coincidence mode; digital out X 0 EN EN Charge amplification mode; anti-coincidence mode; digital out X 0 EN EN Charge amplification mode; coincidence mode; digital out X 0 EN EN Charge amplification mode; anti-coincidence mode; digital out; coinc chan on, isolated X 0 EN EN Charge amplification mode; coincidence mode; digital out; coinc chan on, isolated X X NA NA ADC-only mode X X 1 X X NA NA Quiet mode (everything in power down, except crystal oscillator and part of ADC) X X 0 X X NA NA Coincidence detection mode; analog out Default mode X X 0 X X NA NA Charge amplification mode; analog out X X X X NA NA Buffer-only mode (AAF bypassed); quasi-quite mode (as quite mode, but buffer on) X 0 EN EN Testmode : as 00000, but buffer to pin bufout (to observe PDSH) EN NA NA Testmode PDSH and MDED (via PDSH). MDED output direct to EDOut X 0 X X NA NA Testmode : as 0101X, but MDED output direct to pin EDOut X X 0 X X NA NA Testmode coincidence channel (main channel etc. off), CDED output direct to ICoOut X 0 EN NA 1 Testmode : as 00010, but ADC off, buffer to pin bufout and MDED output direct to EDOut X X NA NA Testmode : direct test of MDED and MDDAC X X NA NA Testmode : as (= ADC-only mode), but AAF bypassed EN EN Testmode : as 00010, but main channel off, external input to PDSH X 1 X X X 1 X X NA NA Testmode 1 digital part X X X X 1 X X NA NA Testmode 1 digital part X X 1 X X NA NA Testmode 2 digital part X X 1 X X NA NA Testmode 3 digital part 0 X X X X X X X 1 X X NA NA Powerdown mode (everything in power down, except crystal oscillator and part of ADC) Final presentation ESA-ESTEC 7/3/2001 J. Wouters 23
24 Mixed mode simulations / 2 z Chip + external components: simulation schematic Final presentation ESA-ESTEC 7/3/2001 J. Wouters 24
25 Mixed mode simulations / 3 z Chip: toplevel design schematic Final presentation ESA-ESTEC 7/3/2001 J. Wouters 25
26 Mixed mode simulations / 4 z Co-simulation: spice - verilog z Essential for PDFE: Many operating modes Complex interaction analog digital event driven asynchronous loops Final presentation ESA-ESTEC 7/3/2001 J. Wouters 26
27 Nonlinearity LSB Simulation result All circuits except ADC Positive charge End-point nonlinearity Negative charge Zero scale Full scale Best Straight Line nonlinearity < 0.5 LSB Errors somewhat proportional with signal Final presentation ESA-ESTEC 7/3/2001 J. Wouters 27
28 z Total Dose: analog and digital part: good up to 12 krad. Parasitic MOS transistor field-oxide leakage: gate-all-round layout for critical NMOS devices (determined by simulation) Gate oxide threshold voltage drift: corner analysis, and assume that no Worst Case wafer (limited volume) z Single Event Upsets: digital part Cell level: foundry library screened for least sensitive cells Rt (register transfer) level: feedback avoided as much as possible (no FSM s) parity bits majority voting for critical registers (EDAC) z Single Event Latch-up Radiation Hardness Thin epi layer on top of a heavily doped and hence low impedance substrate intrinsically robust for latch-up. Latches up under Cf256. Final presentation ESA-ESTEC 7/3/2001 J. Wouters 28
29 Edgeless transistor layout z Significantly increases the total dose immunity z Applied in the peak detector s anti-drift current source Final presentation ESA-ESTEC 7/3/2001 J. Wouters 29
30 Layout z Die size : 31 square mm Final presentation ESA-ESTEC 7/3/2001 J. Wouters 30
31 z 64 pins Quad Flat Package z 56 pins used Package Final presentation ESA-ESTEC 7/3/2001 J. Wouters 31
32 Debug PCB / 1 z VME board Final presentation ESA-ESTEC 7/3/2001 J. Wouters 32
33 Debug PCB / 2 z The two inputs close to the asic Final presentation ESA-ESTEC 7/3/2001 J. Wouters 33
34 Analog pulses z Analog output mode Semi-gaussian output pulse Event detector out z Digital output mode Charge input (V-step on Cseries) Peak detector output Event detector out End of A-to-D conversion Final presentation ESA-ESTEC 7/3/2001 J. Wouters 34
35 Low noise PCB / 1 z Only passive external components z Battery-powered; faraday cage Final presentation ESA-ESTEC 7/3/2001 J. Wouters 35
36 Low noise PCB / 2 z Crystal (digital) not running z Noise(detector capacitance) z With and without crystal running z Measured with zero input signal z 1mVrms corresponds to an ENC of 207electrons PDFE noise measurements Imec/ Estec-Imec low-noise PCB Faraday cage; 4.5V battery z Crystal (digital) running Noise (mvrms) Noise Noise, no xtal Simulation Delta Detector capacitance (pf) Final presentation ESA-ESTEC 7/3/2001 J. Wouters 36
37 Status & conclusions z A low power low noise PDFE is realized z Implements all analog processing up to (& including) the ADC z Mixed analog digital design z High re-usability and scalability z Samples available since 1 year z Device is fully functional z Evaluation board allows all kind of settings and measurements z Low noise board for noise characterization z Estec is building an instrument for STEREO, using PDFE z Technical paper available, from the ESCCON 2000 conference z Datasheet available Final presentation ESA-ESTEC 7/3/2001 J. Wouters 37
38 Application: NASA s STEREO mission z Study of solar eruptions z PDFE to be part of the SEPT experiment (IMPACT instrument) z Launch: 2004 z nasa.gov/stereo.htm Final presentation ESA-ESTEC 7/3/2001 J. Wouters 38
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