I2 C Compatible Digital Potentiometers AD5241/AD5242
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1 a Preliminary Technical ata FEATURES Position Potentiometer Replacement 0K, 00K, M, Ohm Internal Power ON Mid-Scale Preset +. to +.V Single-Supply; ±.V ual-supply Operation I C Compatible Interface APPLICATIONS Multi-Media, Video & Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage to Current Conversion Line Impedance Matching GENERAL ESCRIPTION The A/A provides a single/dual channel, position digitally-controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer, trimmer or variable resistor. Each VR offers a completely programmable value of resistance, between the A terminal and the wiper, or the B terminal and the wiper. The fixed A-to-B terminal resistance of 0, 00 or M ohms has a % channel-to-channel matching tolerance with a nominal temperature coefficient of 0 ppm/ C. Wiper Position programming defaults to midscale at system power ON. Once powered the VR wiper position is programmed by a I C compatible -wire serial data interface. An asynchronous reset (PR) pin forces the VR wiper to the midscale position. Both parts have two programmable logic outputs available to drive digital loads, gates, LE drivers, analog switches, etc. FUNCTIONAL BLOCK IAGRAMS SHN V SA AR ECOE A W B O O RAC REGISTER REGISTER A SERIAL INPUT REGISTER PWR ON RESET SHN V SA GN I C Compatible igital Potentiometers A/A AR ECOE A W B A W B RAC REGISTER RAC REGISTER A0 A A SERIAL INPUT REGISTER REGISTER PWR ON RESET The A/A are available in the surface mount (SO-/- ) packages. For ultra compact solutions selected models are available in the thin TSSOP-/- packages. All parts are guaranteed to operate over the extended industrial temperature range of -0 C to + C. For -wire, SPI compatible interface applications, see the A0/A0/A0/A/A00/A0/A0 products. ORERING GUIE Kilo Package Package Model Ohms Temp escription Option ABR0 0-0/+ C SO- R- ABRU0 0-0/+ C TSSOP- RU- ABR /+ C SO- R- ABRU /+ C TSSOP- RU- ABRM M -0/+ C SO- R- ABRUM M -0/+ C TSSOP- RU- ABR0 0-0/+ C SO- R- ABRU0 0-0/+ C TSSOP- RU- ABR /+ C SO- R- ABRU /+ C TSSOP- RU- ABRM M -0/+ C SO- R- ABRUM M -0/+ C TSSOP- RU- The A/A die size is 9 mil X mil,, sq. mil. Contains xxx transistors. Patent Number 9 applies. O O GN A0 A REV PrB OCT 99 Information furnished by Analog evices is believed to be accurate and reliable. However, no responsibility is assumed by Analog evices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog evices. One Technology Way, P.O. Box 90, Norwood, MA U.S.A. Tel: /9-00 Fax:/-0
2 I C Compatible igital Potentiometers A/A ELECTRICAL CHARACTERISTICS 0K, 00K, M OHM VERSION (V = +V±0% or +V±0%, V A = +V, V B = 0V, -0 C < T A < + C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Units C CHARACTERISTICS RHEOSTAT MOE Specifications apply to all VRs Resistor ifferential NL R-NL R WB, V A =NC RAB=0KΩ - ±0. + LSB Resistor Nonlinearity R-INL R WB, V A =NC RAB=0KΩ - ±0. + LSB Nominal resistor tolerance R TA = C -0 0 % Resistance Temperature Coefficient R AB / T V AB = V, Wiper = No Connect 0 ppm/ C Wiper Resistance R W I W = V /R, V = +V or +V 0 00 Ω C CHARACTERISTICS POTENTIOMETER IVIER MOE Specifications apply to all VRs Resolution N Bits Integral Nonlinearity INL RAB=0KΩ ±0. + LSB Integral Nonlinearity INL RAB=MΩ ±0. + LSB ifferential Nonlinearity NL RAB=0KΩ ±0. + LSB Voltage ivider Temperature Coefficient V W / T Code = 0H ppm/ C Full-Scale Error V WFSE Code = FH LSB Zero-Scale Error V WZSE Code = 00H LSB RESISTOR TERMINALS Voltage Range V A,B,W VSS V V Capacitance A, B C A,B f = MHz, measured to GN, Code = 0H pf Capacitance W C W f = MHz, measured to GN, Code = 0H 0 pf Common Mode Leakage ICM VA = VB = VW na IGITAL INPUTS Input Logic High V IH SA & 0.V V+0. V Input Logic Low V IL SA & V V Input Logic High V IH A0 & A.0 V V Input Logic Low V IL A0 & A 0.0 V Input Current I IL V IN = 0V or +V ± µa Input Capacitance C IL pf IGITAL Output Output Logic Low V OL IOL = ma SA 0. V Three-State Leakage Current I OZ V IN = 0V or +V ± µa Output Capacitance C OZ pf POWER SUPPLIES Power Single-Supply Range V RANGE VSS = 0V V Power ual-supply Range V /SS RANGE ±. ±. V Positive Supply Current I V IH = +V or V IL = 0V 0. µa Negative Supply Current I SS VSS = -.V, V = +.V 0. µa Power issipation 0 P ISS V IH = +V or V IL = 0V, V = +V 0. µw Power Supply Sensitivity PSS %/% YNAMIC CHARACTERISTICS,9, Bandwidth db BW_0K RAB = 0KΩ, Code = 0H 0 khz BW_0K RAB = 0KΩ, Code = 0H khz BW_00K RAB = 00KΩ, Code = 0H 9 khz Total Harmonic istortion TH W V A =Vrms + V dc, V B = V C, f=khz 0.00 % V W Settling Time t S V A = V, V B =0V, ± LSB error band µs Resistor Noise Voltage e N_WB R WB = KΩ, f = KHz nv Hz REV PrB OCT 99 Information contained in this Product Concept ata Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog evices, Santa Clara, CA. TEL 0 -; FAX 0 -; ; walt.heinzer@analog.com
3 I C Compatible igital Potentiometers A/A ELECTRICAL CHARACTERISTICS 0K, 0K, 00K OHM VERSION (V = +V±0% or +V±0%, V A = +V, V B = 0V, -0 C < T A < + C unless otherwise noted.) Parameter Symbol Conditions Min Typ Max Units INTERFACE TIMING CHARACTERISTICS applies to all parts(notes,) Clock Frequency f 0 00 KHz t BUF Bus free time between STOP & START t. µs t H;STA Hold Time (repeated START) t After this period the first clock pulse is generated µs t LOW Low Period of Clock t. µs t HIGH High Period of Clock t.0 0 µs t SU;STA Setup Time For START Condition t. µs t H;AT ata Hold Time t 00 ns t SU;AT ata Setup Time t 0 ns t F Fall Time of both SA & signals t 00 ns t R Rise Time of both SA & signals t9 000 ns t SU;STO Setup time for STOP Condition t0.0 µs NOTES:. Typicals represent average readings at + C, V = +V.. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-NL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See figure 0 test circuit.. INL and NL are measured at VW with the RAC configured as a potentiometer divider similar to a voltage output /A converter. VA = V and VB = 0V. NL specification limits of ±LSB maximum are Guaranteed Monotonic operating conditions. See Figure 9 test circuit.. Resistor terminals A,B,W have no limitations on polarity with respect to each other.. Guaranteed by design and not subject to production test. 9. Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value result in the minimum overall power consumption. 0. P ISS is calculated from (I x V ). CMOS logic level inputs result in minimum power dissipation.. All dynamic characteristics use V = +V.. See timing diagram for location of measured values. ABSOLUTE MAXIMUM RATINGS (T A = + C, unless otherwise noted) V to GN , +V to GN...0V, -V V to... +V V A, V B, V W to GN..., V A X B X, A X W X, B X W X...±0mA igital Input Voltage to GN...0V, V Operating Temperature Range C to + C Package Power issipation...(t J MAX - T A ) / θ JA Thermal Resistance θ JA, SOIC (SO-)... C/W SOIC (SO-)... C/W TSSOP-...0 C/W TSSOP-...0 C/W Maximum Junction Temperature (T J MAX) C Storage Temperature... - C to +0 C Lead Temperature R-, R-, RU-, RU- (Vapor Phase, 0 sec).. + C R-, R-, RU-, RU- (Infrared, sec) C A PIN CONFIGURATION A W B V SHN SA 0 9 O NC O GN A A0 A PIN CONFIGURATION O A W B V SHN SA 0 9 A W B O GN A A0 REV PrB OCT 99 Information contained in this Product Concept ata Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog evices, Santa Clara, CA. TEL 0 -; FAX 0 -; ; walt.heinzer@analog.com
4 I C Compatible igital Potentiometers TABLE : A PIN Function escriptions Pin Name escription A Resistor terminal A W Wiper terminal W B Resistor terminal B V Positive power supply, specified for operation from +. to +.V. SHN Active Low, Asynchronous connection of the wiper W to terminal B, and open circuit of terminal A. RAC register contents unchanged. Serial Clock Input SA Serial ata Input/Output A0 Programmable address bit for multiple package decoding. Bits A0 & A 9 A Programmable address bit for multiple package decoding. Bits A0 & A 0 GN Common Ground Negative power supply, specified for operation from 0 to -.V O Logic Output terminal O NC No Connect O Logic Output terminal O A/A TABLE : A PIN Function escriptions Pin Name escription O Logic Output terminal O A Resistor terminal A W Wiper terminal W B Resistor terminal B V Positive power supply, specified for operation from +. to +.V. SHN Active Low, Asynchronous connection of the wiper W to terminal B, and open circuit of terminal A. RAC register contents unchanged. Serial Clock Input SA Serial ata Input/Output 9 A0 Programmable address bit for multiple package decoding. Bits A0 & A 0 A Programmable address bit for multiple package decoding. Bits A0 & A GN Common Ground Negative power supply, specified for operation from 0 to -.V O Logic Output terminal O B Resistor terminal B W Wiper terminal W A Resistor terminal A t SA t t t 9 t t t t t t P S Sr P Figure. etail Timing iagram t 0 The A/A I C-bus interface is a receive only slave. ata is accepted from the I C bus in the following serial format: S 0 0 A A 0 0 A A/ B R S S O O X X X A Slave Address Byte Instruction Byte ata Byte 0 A P Where: S = Start Condition P = Stop Condition A = Acknowledge X = on t Care A, A0 = Package pin programmable address bits A/B = RAC sub address select RS = Midscale reset S = Shutdown, same as SHN pin operation O, O = Output logic pin latched values,,,,,,,0 = ata Bits REV PrB OCT 99 Information contained in this Product Concept ata Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog evices, Santa Clara, CA. TEL 0 -; FAX 0 -; ; walt.heinzer@analog.com
5 I C Compatible igital Potentiometers A/A OUTLINE IMENSIONS imensions shown in inches and (mm) REV PrB OCT 99 Information contained in this Product Concept ata Sheet describes a product in the early definition stage. There is no guarantee that the information contained here will become a final product in its present form. For latest information contact Walt Heinzer/Analog evices, Santa Clara, CA. TEL 0 -; FAX 0 -; ; walt.heinzer@analog.com
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