EE143 Microfabrication Technology Spring 2011 Prof. J. Bokor. Final Exam

Transcription

1 -- EE143 Microfabrication Technology Spring 2011 Prof. J. Bokor Final Exam Name: Signature: SID: CLOSED BOOK. THREE 8 112" X 11" SHEET OF NOTES, AND SCIENTIFIC POCKET CALCULATOR PERMITTED. MAKE SURE THE EXAM PAPER HAS 15 PAGES. DO ALL WORK ON THE EXAM PAGES. USE THE BACK OF PAGES IF NECESSARY. TIME ALLOTTED: I 80 MINUTES Question 1 (30 pts) 2 (35 pts) 3 (45 pts) 4 (30 pts) 5 (60 pts) Score Total (200 pts)

2 Fundamental constants you might need: Boltzmann's constant, k = 1.38 X J/K Permittivity of free space, Eo = 8.85 X Permeability offree space, )..to = 1.26 X Flm 10-6 Him Speed of light in vacuum, c = x 10 8 mls Electron charge, e = 1.6 x C Free electron mass, m, = 9.1 X kg Electron volt, 1 ev = 1.6 x J Thermal voltage, kt/q = V (at 300K) Relative dielectric constant of silicon, K, = 11.8 Relative dielectric constant of silicon dioxide, K, = 3.9 Effective masses in silicon at 300K. Electrons: m,* = 1.18 m, ; Holes: m, * = 0.81 m, Silicon band gap at 300K, Eg= 1.12 ev Intrinsic carrier concentration in Si (at 300K), n, = ern" Ideal gas constant, R = J mol" K"I ; L atm rnol' K- I 2

3 Solid Solubility Limits Information which may be useful: As ---p, -2 v:,.. g < r r- V C) C C) - r / / / / / / / ",/ B ---Solubility limit Electrically active L I.-_-.I

4 Diffusion Information which may be useful:,"'i' /4()O 1300 I Ternpersrere f 'C) i200 / WI? [000 1! I Subs titutional Diffusers lo j ; I..i i. I Interstitial Diffusers l e is 10.1 I; Temperature, looolt (K I) 4

5 Ion Implantation Information which may be useful: Si a,-.!;l '-" i1i..3 t>i>.:: QI ill ".s i:- 0 rj) 0 '" w t:l.. e 2 1l Si & Energy (kev) 5

6 Thermal Oxidation Information which may be useful: <loo>silicon 1.0 r-.. E :i. <:» u: v: V.l<:....G... v 'V 'x L--_...J..._L.--L..-I-...L...U'W'...L..-_--I._.l...-.I...l-J...I...l...i...i.-_--..J._...L..-..J...I...-J...J...J..J..J Oxidation time (hr) 6

7 Thermal Oxidation Information which may be useful: <1 Jl >Silicon 1.0 v ;.< o 0.1 Oxidation time (hr) 7

8 1) True or False. (30points total, 2 points for each question).:la) ( B) -=r::. C) T D) LE) -r F) f G) f H) \' I) LJ) r K) \" L) M) "'\ N) --=L 0) In a p-channel MOSFET operating in the saturation region, the inversion charge density decreases from the Source toward the Drain. For a p-channel MOSFET pinchoff occurs when V D > V Dsat. VT rolloff describes when MOSFET threshold voltage is reduced as channel length decreases. The work function of silicon depends on the doping concentration. At the flatband condition in an MOS capacitor, the charge density in the semiconductor is equal to the intrinsic charge density. In an n-channel MOSFET at threshold, the semiconductor bands bend downward towards the oxide interface. The threshold voltage for an-channel MOSFET with heavily doped n-type polysilicon gate is equal to the threshold voltage for a p-channel MOSFET with heavily doped p-type polysilicon gate. Electrons diffuse from high concentration to lower concentration regions, while holes diffuse from low concentration to higher concentration regions. According to EE143 design rules, an Al to poly contact can not be directly on top of an active (thin oxide) region. The self-aligned source/drain implant process saves two lithography steps. Electromigration in metals is dominated by grain boundaries because electrons preferentially flow in the grain boundaries. A uniform substrate concentration profile for one dopant can be perturbed by diffusion of another dopant with a high concentration gradient. Anisotropic etching of silicon can be achieved using wet etching. EUV lithography requires the use of a reflection mask. You add acid to water to dilute the acid, but you add hydrogen peroxide to sulfuric acid to mix piranha. 8

9 2) Definitions (35 points total, 5 points for each) Define each of the terms below in one or two sentences and illustrate the definition with a sketch. The following example illustrates the response requested. Example: linear rate constant Answer: The linear rate-constant in oxidation expresses the growth rate as limited by the surface reaction rate. The sketch below shows a typical growth oxide thickness curve for oxide; in the linear portion (short time), the slope is the linear rate constant. o.c,' l<'---'-=-:'--+---'--"-'--4--=-"-'-+'--'--="=-'-'i D, time min) a) Optical proximity correction Aur--d IQf"1 f(. f-vves (U C:.. trr to +4 et S Ie \ lf'ove.'t+o,) e"rf.a.+;h''\. 8 [b [S t-;0 0 Pc... W\..;l..s. l ""'-se. b) Negative photoresist la.? \ +--l 0 P c, A-.fh- le \JeJ 0 wt + rests.j- re I\A5 f.jj l.e.r i.""f' ey;.fos -k> I 113kt. c) Straggle ft.$ k V' o/' { '/' / (-/ / lit I

10 f) Electromigration OV f v'v\el\ t\()je b1 efec:.tfob'\.

11 3) CMOS (45 points total) a) Increasing substrate doping causes increase or decrease ofmos transistor threshold. (5 points) nmos/ C_(e_,e=-_ pmos J C_(_e e Explain your answers. i", -J - -r \cp F ) + [Jl. s i'ns(j:),,1 + 1&6)1k,- " C Ojc Vif : M"1- - (4r/-[J2esil\1B(\ FJ-VB) Ij(* Qj r G \JTtJ" \4\ "'- NB /l<'\cre.4.se 0d-k. 1'V\c::rA.s-c.O'I 4r loth. f\ MDS f IVtD b) A CMOS process is made with N+ poly gates for both n-channel and p-channel devices. If you switch to P+ poly gates, will it cause an increase or decrease in threshold voltage? (5 points) nmos\ C_r $ pmos la c (_e ) Explain your answers. f + f" 1'( <'<. l; r1ef '-of) r k. ('v+,<>- +L", PI + p. r(, V fb lc..(c:-tt.5e) So T 1'V\.("e '@.,.'; +r botl V\. +- f AA..o:5' 11

12 c) In a "Iumprocess, a large NMOS transistor (W/L = 4rn!4 urn) is designed to have a 1V threshold. But the threshold is known to vary with Wand L as they are reduced. Qualitatively complete the sketches below (i.e., get one point on the curve and show the general trend from this point.) (10 points) i i : 1 1 l-----f li i a L. _ a 2 3 l (um) 4 o W(um) d) If the gate oxide thickness is 50 nm, NA 1EI5 em", what is the approximate threshold implant dose, and what dopant would you choose to achieve the desired 1V large device threshold voltage? Assume no fixed oxide charge or interface traps. (25 points) \ire -O-b - IJ /4rl" VI,, Cl,02" IOS"'" 0.31/.', V F i3 =: -0. \J VT:: \If s +)4f),.. (}r--4j """"I-:--4 c.; Cox - O," t 0, + l)(/,o'i \(ID1J..){/.G,l(((/\rP)(.o.::,y/k- &..9 )(.(0 g D\r l \J VI) -0, h. c; fs:::;ilx6o _, _12..j - 10 kf )Uo FIC WI CO-= - 3. cr6e; v;"'(0-7.: C. 9 '1-/0-'8 F/c."V\""l.- 12

13 4 Interconnects (30 points) Calculate the resistance of this structure between the two large pads on either side. All dimensions are given in urn. Assume the p-layer is uniformly doped. Neglect current crowding effect (if you don't know what that is, don't worry about it). Use the following values: Al resistivity ()..tq-cm) 2.8 W resistivity ()..tq-cm) 5.5 W to Si specific contact resistivity (Q_cm 2 ) 3.0E-6 W to Al specific contact resistivity (Q_cm 2 ) IE-8 p-layer doping (ern") lel9 Hole mobility (cm 2 N-s) 100 OV\ ov'-e s', 0\ e. - A L It "'e: L::; 3 + 0,,c3l:T I}J-; t.s T'::: 0,s: R4L.= f0jr-= W pl0j" «=».c W=-I T- I Rw = OOS.JL VJ - 5 \ C,{) III.-+- GleJ Rt =- je/a A::- JMr.t 2.::; 10- CNl 1 R c. = Joo.J2. W - A I 6> I'\..J.-a.. Rc..::- IO<a/to-S :::- ISl. C., re' (. -} (.:p )- { (J l1 17':\ I ::: 51 "f'1 t'1 )SL :t'/';v-tt- V!! xl,gxlo- >'-100):::- O.OOC3J2-cU1 ltj e f ( '\ 1)b'cIL C&\ tc'*"",", 'l-t'( >-- ( "5'1 'I \'Ie L 7}1M \N -:::t I T O. 2..S" f4.,:: I I 19k J"L 13 R -:;?-( RA( + Rw + 'RW"Si + RW'A-f-RI :: IT!78 k J S'

14 5) Process integration (60 points total, 15 points for each diagram) For each of the 4 following process sequences, carefully and neatly sketch a cross-section through the stated feature at the end of the sequence given. Note scales on sketches. Indicate all important dimensions on your diagrams. Neatness counts for 30% of the grade. Note that except for parts c&d, these are all independent, so you can do (b) without doing (a), etc. a) i) Grow 0.25 urn thermal oxide on Si ii) Deposit 0.75 urn CVD oxide iii) Photomask Ium x Ium openings for contacts. Resist 0.6 urn thick. iv) Wet etch 6 min BHF (etch rate O. 1 urn Imin thermal oxide, 0.3 urn Imin for CVD oxide). Assume infinite selectivity to resist. Draw cross section through the.,.il contact on the given chart. Units are 1.6 'I'! ii, 1.4 -t--+--.t-+-- I : lye t's"+t i i I I 1.2' ;.,._-- I 1 Ii' i 0.8 I 0.6 i 0.4! o in urn. A good estimate of the final L _ oxide thickness is adequate. { I O. / J!0.'3 :: /S'"I\A'I VI. +Q e.t"k ell.d 01'---/ Joe. '3,S-I\,\t 0 v e.re!.t-c:.f'\ '"3. 'f 0 /3 -=:- (,»s;«ivi. Itt.\'E-+c.. \ox.;j.. I M..,,,,- o'le.(e-k. O. W\ '].: l-i1.-ivl o+- +k, Ia.\..U IV' t!.+ck i i! i I! I t I b) i) Grow 0.1 urn thermal oxide on Si ii) Deposit 0.1 urn Si3N4 iii) Photomask 2 urn lines and spaces iv) Etch SbN4 (anisotropy plasma etch, selectivity Si3N4 vs. oxide 4: 1) v) 20% overetch; remove resist vi) Wet oxidation (0.75 urn oxide on bare test wafers) Draw cross section through one line and space. at least "'----i-...:.i2_4_-+! 0.4 1f---t---''---+-7'i-+::t < J 0.2 : i o t-i--!---+o

15 c) i) Grow 0.1 urn thermal oxide on Si ii) Deposit 0.5 urn Polysilicon iii) Dope with Phos 900 C iv) Photomask 2 urn wide gate pattern v) Plasma etch Poly in fully anisotropic etch with 20% overetch, Selectivities: poly vs. oxide 2: 1, poly vs. resist 10: I vi) Remove resist Draw cross section through the gate. r---- Ii 1.6! 1.4 I 1.2 i I i II I I II 1 i i i I,--,-, I" I! I! l.+--t t----r '-+---t , I i I 0.8 l I Iii! 0.6 _ I IiI I I! I 0.4 _ i i I I O. 7 l S 6 o I -_t-h--,e---'k--.j--r-e--' O}(iJe d) Continuation of ( c) i) Deposit O.5flm CVD oxide ii) Plasma etch oxide in fully anisotropic etch. Etch rate same for CVD and thermal oxide. Etch to remove O.5flm plus 20% overetch. Selectivities: oxide vs poly 5: J, oxide vs. Si 5: 1 Draw cross section through the gate. 1.6 I I L----l 1.4 i! I 0.2 LO