Design/Technology Co-Optimisation (DTCO) in the Presence of Acute Variability
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1 Design/Technology Co-Optimisation (DTCO) in the Presence of Acute Variability A. Asenov 1,2, E. A. Towie 1!! 1 Gold Standard Simulations Ltd 2 Glasgow University!
2 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge!! Conclusions!
3 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge!! Conclusions!
4 The semiconductor industry is facing atomic scale limitations!!! The simulation! Paradigm now A 22 nm MOSFET! In production 2013 A. Asenov 1998! A 4.2 nm MOSFET! In production????
5 Statistical variability is one of the major challenges associated with scaling! After K. Takeuchi (NEC)! Variability results in higher parametric yield loss!
6 Main sources of statistical variability Random dopants! Metal Gate Granularity! Line edge roughness!
![Statistical variability in 20nm CMOS σv T [mv] 100 80 60 40 RDD NMOS PMOS LER MGG](/docs-images/82/86655090/images/7-2.jpg "RDD+LER Gate Last COMBINED Gate First 20 0 0.05 1.0-0.05-1.0 Drain Bias [V] P.")
7 Statistical variability in 20nm CMOS σv T [mv] RDD NMOS PMOS LER MGG RDD+LER Gate Last COMBINED Gate First Drain Bias [V] P. Zuber, IMEC!
8 Saturation in performance and increasing variability drives the CMOS innovations! M Bohr (Intel)! FinFETs improve performance and can reduce statistical variability!
9 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge!! Conclusions!
10 Intel 22nm FinFETs
11 Intel 22nm FinFETs
12 3D Ensemble MC simulation provide predictability Quantum confinement! is important! Non-equilibrium transport! is also important! DD! MC! Electron energy! Electron velocity!
13 Intel 22nm FinFETs
14 Intel 22nm FinFETs
![Intel 22nm FinFETs I ON [μa] 100 95 90 85 80 75 Fin 1 Fin 2 Fin 3 Rect (W=10nm) Rect (W=8nm) 70 10](/docs-images/82/86655090/images/15-2.jpg "15 20 25 30 35 40 L [nm] Rectangular fins have 15% higher performance for equivalent width and")
15 Intel 22nm FinFETs I ON [μa] Fin 1 Fin 2 Fin 3 Rect (W=10nm) Rect (W=8nm) L [nm] Rectangular fins have 15% higher performance for equivalent width and height.!
16 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs! " Predictive TCAD simulation! " Statistical CM extraction! " Statistical Circuit simulation!! 10nm FinFETs: Si vs. Ge!! Conclusions!
17 The GSS Tool Suite that enables the Design Technology Co-Optimization flow FLOW CONTROL! Input files generator, job submission, execution monitoring! MONOLITH! GARAND! MYSTIC! RANDOM SPICE! Structure! translator from! TCAD process! simulator! 3D! DD/MC/NEGF! Simulator!! Statistical Compact Model Extractor! Statistical Circuit Simulator! DATABASE CONTROL! Data harvesting, annotation, storage! 8!
18 The GSS Tool Suite that enables the Design Technology Co-Optimization flow FLOW CONTROL! Input files generator, job submission, execution monitoring! MONOLITH! GARAND! MYSTIC! RANDOM SPICE! Structure! translator from! TCAD process! simulator! 3D! DD/MC/NEGF! Simulator!! Statistical Compact Model Extractor! Statistical Circuit Simulator! DATABASE CONTROL! Data harvesting, annotation, storage! 8!
19 The statistical device simulator GARAND
20 14nm DG FinFET specification GATE HM DRAIN Dimension! Min (nm)! Max (nm)! H fin W fin SOURCE tox L G BURIED OXIDE Fin Width! 8! 12! Fin Height! 22! 28! Gate Length! 18! 22! SUBSTRATE " Double gate FinFETs targeted at 14nm technology node. " Devices targeted for high performance SRAM application. " Process variation aware design. T=85 C V DD = 0.9V! NMOS! PMOS! I ON (ma/µm )! 0.9! 0.8! I OFF (na/µm )! 10! 10! DIBL(mV/V)! 56! 65! SS(mV/Dec)! 86! 88! 10!
![The role of predictive MC simulations I D [ma/ m] 1 0.1 0.01 0.001 L G = 20nm MC DD (calibrated) DD (default) 2.0 1.5 1.0 0.5 Velocity [x10 7 cm s -1 ] 2.5 2.0 1.5 1.0 0.5 DD MC 0.0001 0.0 0.1 0.2 0.](/docs-images/82/86655090/images/21-0.jpg "3 0.4 0.5 0.6 0.7 0.8 0.9 V G [V] 0.0 0 10 20 30 40 50 60 X Position [nm] \" Only EMC simulations can predict performance. \" Quantum corrections are essential.")
21 The role of predictive MC simulations I D [ma/ m] L G = 20nm MC DD (calibrated) DD (default) Velocity [x10 7 cm s -1 ] DD MC V G [V] X Position [nm] " Only EMC simulations can predict performance. " Quantum corrections are essential. " DD simulations can be calibrated to EMC. Quantum effects are very important 11!
22 Process induced variability Fin width (nm) IODsat (ma) Gate length (nm) " Captured by experiment design. " Dependence on L, H F, W F, T OX. 12!
23 Statistical Variability Simulations RDD! MGG! GER+FER! 15!
24 Nominal Device Statistical Variability! Correlation between subthreshold figure of merits, such as I OFF and DIBL, can be a good indicator to show whether MGG is an active variability source. 17!
25 Correlation between process and statistical variability 18!
26 Statistical aspects of Reliability Fresh! Normal Quantile Trapping Density (cm -2 ) 0 1E11 5E11 1E V T (V) With degradation! 19!
27 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs! " Predictive TCAD simulation! " Statistical CM extraction! " Statistical Circuit simulation!! 10nm FinFETs: Si vs. Ge!! Conclusions!
28 The GSS Tool Suite that enables the Design Technology Co-Optimization flow FLOW CONTROL! Input files generator, job submission, execution monitoring! MONOLITH! GARAND! MYSTIC! RANDOM SPICE! Structure! translator from! TCAD process! simulator! 3D! DD/MC/NEGF! Simulator!! Statistical Compact Model Extractor! Statistical Circuit Simulator! DATABASE CONTROL! Data harvesting, annotation, storage! 8!
29 Statistical Compact Modeling Procedure! Process Variaiton Aware Device TCAD Design Process Variation Aware Statistical Device Simulation Extended Uniform Device Compact Modelling Extended Statistical Device Compact Modelling Unified Statistical Compact Model Libraries 21!
30 The Statistical Compact Model Extractor Mystic Device Measurement Mystic Device Database Statistical Device Measurement Advanced Data Preprocessing Advanced Data Preprocessing Multi-Stage Fitting Strategy P P P Mystic Optimisation Engine P O P O O P Statistical Fitting Strategy Uniform Compact Model Averaged Compact Model Uniform Compact RandomSpice Uniform Compact Model Model Library Model
31 Extended Uniform Model Group 1 Parameter! 22!
32 Statistical Compact Modeling! Strong correlation between statistical compact model parameter and device figure of merit demonstrates that extraction is physics based! 25!
33 Statistical Compact Modeling Group 2 parameter! 27!
34 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs! " Predictive TCAD simulation! " Statistical CM extraction! " Statistical Circuit simulation!! 10nm FinFETs: Si vs. Ge!! Conclusions!
35 The GSS Tool Suite that enables the Design Technology Co-Optimization flow FLOW CONTROL! Input files generator, job submission, execution monitoring! MONOLITH! GARAND! MYSTIC! RANDOM SPICE! Structure! translator from! TCAD process! simulator! 3D! DD/MC/NEGF! Simulator!! Statistical Compact Model Extractor! Statistical Circuit Simulator! DATABASE CONTROL! Data harvesting, annotation, storage! 8!
36 The Statistical Circuit Simulation Engine RandomSpice Statistical Parameter Generation Template Circuit Compact Model Library RandomSpice Engine Statistical Enhancement Engine SPICE + - Database Analysis Power Performance Yield
37 FinFET based SRAM design Cell! Cell! 29!
38 Cell design trade off Metal Gate Work-Function Engineering! 31!
39 Interplay between CD and statistical variation! " Slow corner has the best SNM performance. " CD variation can introduce 10% degradation on standard deviation of SNM. 34!
40 Reliability Aspect of SRAM Performance! " Under N/PBTI stress condition, SNM can be degraded by more than 25% " However, write operation can be improved under stress condition 35!
41 Summary!! Introduction!! FinFET complexity Motivates DTCO!! DTCO flow at 14nm FinFETs!! 10nm FinFETs: Si vs. Ge!! Conclusions!
42 10nm FinFET options: FinFET design GATE DRAIN SOURCE H fin W fin tox L G STI SUBSTRATE
43 First-Principles Informed Simulations Band structure in UTB devices (in collaboration with A. Asluger & P. Sushko, UCL) 1.2 nm! 2.9 nm! 12.1 nm!
44 DG quantum corrections Base on 1D Poisson-Schrodinger solver
45 Performance based on MC simulations
46 Carrier velocities
47 Simulation of statistical variability
48 Simulation of statistical variability
49 Nominal compact models
50 Impact of Extraction and Wire-load Normalized+Delay+ 4" 3.5" 3" 2.5" 2" 1.5" 1" Si" Ge" Ge is 0.38% faster Ge is 2.26% slower Normalized+Delay+ 4.5" 4" 3.5" 3" 2.5" 2" 1.5" 1" Si" Ge" Ge is 2% faster Ge is 3.5% slower 0.5" 0.5" 0" Intrinsic" Transistors" Extracted" netlists" 100"M1" track"wire" load" 500"M1" track"wire" load" 0" Intrinsic" Transistors" Extracted" netlists" 100"M1" track"wire" load" 500"M1" track"wire" load" Inverter+ 23Input+NOR+ Extracted netlists generated using the ARM 10nm Predictive Technology Modeling toolset!!!
51 Delay vs. Supply Voltage Si Ge Normalized Delay Supply Voltage (V)
52 Conclusions! FinFET complexity Motivates Design/Technology Co-! Development.! 22nm Intel FinFET example!!!! We have studied in detail a full DTCO flow for 14nm FinFETs, showing how GSS simulation platform can help designers from process to devices up to circuit level.!! We have show an example of applicability of GSS platform for evaluating different option for future! FinFETs technology generations.!
53 Thanks for your attention! You will find this presentation and additional material on our webpage
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