Discrete-Time Filter (Switched-Capacitor Filter) IC Lab
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1 Discreteime Filter (Switchedapacitor Filter) I Lab
2 Discreteime Filters AntiAliasing Filter & Smoothing Filter f pass f stop A attenuation FIR Filters f max Windowing (Kaiser), Optimization 0 f s f max f s f s f max IIR Filters Frequency ransformation from Filters Forward / Backward Euler ransformation Bilinear ransformation Lossless Discrete Integrator (LDI) ransformation I Lab
3 S ircuit Motivation Active R Filter R imeonstant ariation ~ 30% apacitance Ratio ariation ~ 0.% Building Blocks Well Integrated Operational Amplifier : Foldedascode onfiguration apacitor : PolyPoly, MetalMetal Switches : ransmission Gate MultiPhase NonOverlapping locks I Lab
4 Foldedascode Op Amp SingleStage Op Amp DD Frequency ompensation M 9 M 0 BP by Load apacitance L D voltage gain A ( 0) g R g [ g r ] m m m ds M M v in M6 M 5 BP M 3 M 4 v UnityGain Frequency ω 0dB gm L BN M 0 M 7 M 8 Slew Rate SR I 0 L SS Fully Differential ersion I Lab
5 S ircuit Applications Analog Discreteime Filters Analog Discreteime Signal Processing ircuits oltage Amplifiers, GA Interpolators, Decimations Modulators, Demodulators, Mixers Oscillators, Waveform Generators,.. Data ransceivers : elecom I, ODE, Baseband Processors,. Data onverters DA : hargeredistribution, yclic (Algorithmic) AD : Successive Approximation, yclic (Algorithmic), Pipeline SigmaDelta Modulators Other Areas I Lab
6 Basic Idea of S ircuits Req harge ransfer ( ) Q Q ( ) Q Average urrent during Q ( ) Iavg Equivalent Resistance R eq Iavg f S I Lab
7 R vs S Integrators R v v Passive Resistor Switchedapacitor Branch v R t ( t) v ( τ) dτ H ( s) in a in ( s) ( s) R s Requirements R I Lab
8 S Integrator Operations v v q q v v v f f q v q q ( n) v( n) vin( n) ( n) v ( n) [ 0 v ( n) ] q q ( n) v( n) 0 ( n) v ( n) [ 0 v ( n) ] at the integration time (f ) n, (f ) n, Dq Dq q q( n) q( n) q( n ) 0 { vin( n ) } ( n) q( n) q( n ) [ 0 v( n) ] [ 0 v( n ) ] [ v ( n) v ( n ) ] v ( n ) in I Lab
9 Basic S Integrator v q v q v t n t n/ t n t n/ t n q q [ 0 { vin( n ) }] [ v( n) v( n ) ] [ v ( n) v ( n ) ] v t n t n t n ( z) [ z ] ( z) z in v t n/ t n/ H ( z) in ( z) z ( z) z v I Lab
10 Basic Integrator v q v q v t n t n/ t n t n/ t n q q [ vin( n) 0] [ v( n) v( n ) ] [ v ( n) v ( n ) ] v t n t n t n ( z) [ z ] ( z) in v t n/ t n/ H ( z) in ( z) ( z) z v I Lab
11 I Lab Frequency Response of SI ransfer Function ondition : W << ontinuousime Integrator For Same Frequency Response ( ) ( ) e H z e H j e z j j Ω Ω Ω ( ) ( ) j j H e j Ω Ω Ω Ω L ( ) ( ) Ω Ω Ω j R H s j H j s R / & accurate / & accurate
12 Parasitic apacitance Problem P3 P4 v P P P ( ) P H z z z P : onnected to GND P3 : onnected to irtual GND P4 : onnected to Output of an Amplifier I Lab
13 ParasiticInsensitive S Integrators v v H ( ) ( z) z z H( z) ( z) z in in ( z) ( z) z All Parasitic apacitors onnected to GND / irtual GND oltage Source / Output of Amplifier I Lab
14 Signal Flow Graph Establishment (n) q(n) v (n) in z (z ) Switched Branch Input : in, Output : DQ q ( n) q( n) q( n ) [ 0 vin( n) ] Q( z) z ( z) Op Amp w/ Feedback Input : DQ, Output :, v in ( n) v ( n ) q( n) ( z ( z) Q( z) ) I Lab
15 Signal Flow Graph for S Integrators v ( z ) v F v z (/ F ) z v 3 z 3 ( z) ( z) ( z) ( z) 3 F F z F z I Lab
16 storder S Filter Active R ersion S ersion F R 3 R F v (n) in (s) (s) (n) 3 Signal Flow Graph in (z ) F (z ) 3 ( ) H z in ( z) F F ( z) 3 F z z I Lab
17 HighOrder Filter Implementation ascade of Biquad Blocks X H H i H N/ Y N N bz bz b0 i i az az a0 ( ) Hi( z) H z H H...H i...h N/ RL Prototype X(s) R S L L R L Y(s) I I sl ( s) [ ( s) ( s) ] ( z) I ( s) z s z I Lab
18 LowQ S Biquad Active R ersion S ersion k 4 F k 6 F (s) ω 0 /h 0 F /ω 0 /ω 0 Q/ω 0 F v (s) k F F k 5 F F v /h k F h ( ) H s in ( s) hs hs h ( s) ωo s s ω Q o 0 k 3 F I Lab
19 LowQ S Biquad (cont d) Signal Flow Graph k 4 k 6 k k 5 z z z v k k 3 (z ) ransfer Function ( ) H z in ( z) ( z) ( k k3) z ( kk5 k k3 ) z k3 az az a ( k ) z ( k k k ) z b z b z k 3 a 0 k a a 0 k5 a 0 a a k 6 b 4 k5 b b k k I Lab
20 HighQ S Biquad Active R ersion S ersion k 4 F /ω 0 (s) ω 0 /h 0 F /Q /ω 0 F v (s) k F F k 6 F k 5 F F v h /ω 0 k F h k 3 F ( ) H s in ( s) hs hs h ( s) ωo s s ω Q o 0 I Lab
21 HighQ S Biquad (cont d) Signal Flow Graph k 4 k 6 (z ) k k 5 z z z v k (z ) k 3 (z ) ransfer Function ( ) H z in ( z) ( z) k 3 z z ( kk5 kk5 k3 ) z ( k3 kk5) az az a ( k k k k ) z ( k k ) z bz b k k 3 a k5 a a0 k k5 a 0 a a 5 k6 b0 k 4 k5 b b0 k I Lab
22 S Ladder Filter RL Prototype R S I L 3 R L v I 3 s sl s 3 ( ) ( ) 3 ( I) in R S 3 R L ( I ) Block Diagram /R S in (s) /R S I s sl s 3 3 /R L I Lab
23 S Ladder Filter (cont d) Active R Implementation S Implementation R S in S S in (s) I L 3 3 (s) S L R R S L L 3 L R L I Lab
24 in S L S 3 For discharged to GND For connected to I/O of op amp. in S L S 3 φ φ φ L L I Lab
25 Scaling for Maximum Dynamic Range apacitors onnected to Output of Op Amp k, m,k m,k α k,k / α k For Maximum Output of Op Amp k, max,k a k max,k / max,lin d a d a a a (n) v (n) b c (n) v (n) a b a c max,lin max, max,lin max, Noise Increase by Much Less than O(a k ) I Lab
26 Scaling for Minimum apacitance apacitors onnected to Input of Op Amp k, n,k n,k β k in,k For Minimum apacitance of Op Amp k, min,k β k min / min,k where min is the min. capacitance value set by technology. Smallest apacitor onnected to Input of Op Amp k ~ min otal apacitance Minimized I Lab
27 Nonideal Problems in S FIlters Switch Nonidealities NonZero OnResistance harge Injection Junction Leakage urrent apacitance Nonidealities Mismatch Problem Op Amp Nonidealities Offset oltage Finite D Gain & Bandwidth Limited Slew Rate NonZero Output Impedance Noise I Lab
28 harge Injection φ ov e v Due to Overlap apacitance O Signal Independent O O ( ) Due to hannel harge DQ H Signal Dependent O DD SS H Q H ox WL ( ) WL ( ) GS H ox DD S H I Lab
29 Solution D O HalfSize Dummy Switch Driven By omplement locks ransmission Gate Fully Differential Approach S v S v ov () & ov () ancelled Each Other I Lab
30 Solution D H Delayed locking Scheme φ 4 φ 3 v φ 3 φ 4 Due to S : hannel harge Dependent on in Due to S3 & S4 : hannel harge Dependent on GND an be Removed uring Off S 3 & S 4 Earlier hannel harge of S Isolated from Using ompensation apacitor Insert () Q H Stored on ompensation apacitor I Lab
31 apacitance Mismatch Area Inaccuracy & Oxide hickness ariation Keep apacitance Ratio onstant 0µm 40µm 0µm 0µm 0µm 40µm ( ) ( 400.5) ( 00.5 ) ( 00.5 ).6% error ( 00.5 ) ( 00.5 ) ( 00.5) ( 00.5 ) 4 I Lab
32 apacitance Lay ommomentroid Approach 4 4 Ground Shielding poly nwell analog ground poly n I Lab
33 DS echnique orrelated Double Sampling an Remove Offset oltage, /fnoise, Power Supply Noise, Finite D Gain Error f f offset Stored offset Removed v v offset v v v offset v offset v offset I Lab
34 Finite D Gain of Op Amp v / A 0 v ransfer Function Frequency Response Magnitude Error ( ) H z A 0 jω jω Hideal ( ) ( e ) H e m ( ω) m A A 0 z e jω ( ω) jθ( ω) jsin( ω ) m( ω) jθ( ω) 0 Phase Error θ ( ω) A 0 sin ( ω ) I Lab
35 I Lab Finite Bandwidth of Op Amp Op Amp : OnePole System w/ Unity Gain Freq. of w 0 Frequency Response Magnitude Error Phase Error A (s) [db] A 0 0 p ω 0 ω ( ) p s p s p A p s A s A ω ( ) ( ) ( ) ( ) ( ) ω ω ω ω ω ω F jsin e e H F H e j j ideal j ( ) ( ) ( ) cos e m F o 0 ω ω ω ω ( ) ( ) ( ) sin e F 0 0 ω θ ω ω ω
36 Lay Example ADD ASS GND Op Amp Well apacitor DDD DSS LKs Switch I Lab
37 S Filter Simulation Example LowQ S Lowpass Biquad Filter FF Analysis for Each Frequency of Interest.fft v(node) np 048 format unorm ircuit Schematic φ 0.68p Simulation Results ndorder S Lowpass Biquad Low Q.56p p 0.68p v magnitude (db) p 50 0p Model first ircuit Second frequency (Hz) I Lab
38 Implementation Example 5thOrder Lowpass Filter for ISDN UI/F AFE x Filter 0 0 H(f) [db] : calculation o : simulation x : measurement frequency [Hz] I Lab
39 Recent Advance Example 6thOrder hannel Select Lowpass Filter IEEE LSI Symposium 996. I Lab
40 Recent Advance Example Bandpass Biquad w/ GainEnhancement Replica Op Amp f center 0MHz (Q0) f sample 00MHz IEEE ISS 997. I Lab
41 Recent Advance Example 3 Bandpass Biquad w/ Switched Op Amp f center 440kHz (Q6.7) w/ f s.8mhz Power DD IEEE ISS 997. I Lab
42 Recent Advance Example 4 00MSampes/s SLPF 0.5µm MOS echnology Power DD 3 IEEE ISS 999. I Lab
43 Recent Advance Example 5 SBPF w/ Switched Op Amp 0.5µm MOS echnology f o 75kHz w/ Q 45 Power DD IEEE ISS 000. I Lab
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