Advantages of Using CMOS

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1 Advantages of Using CMOS Compact (shared diffusion regions) Very low static power dissipation High noise margin (nearly ideal inverter voltage transfer characteristic) Very well modeled and characterized Mechanically robust Lends itself very well to high integration levels Analog CMOS process usually includes non-salicided poly layer for linear resistors. SiGe BiCMOS is very useful but is a generation behind currently available standard CMOS 1

2 Transistor f T Calculation V DD i g i d f T is the frequency at which becomes 1. i d g m = i g 2πf Τ C gs v gs V GS C gs ( ) W g m = µc ox L V V GS t C gs = γwlc ox ω T = 2πf T = µ γl 2 ( V GS V t ) f T gives a fundamental speed measure of a technology µm CMOS: f T ~ 23GHz (V DD = 2.5V) 0.18 µm CMOS: f T ~ 57GHz (V DD = 1.8V) 2

3 Static CMOS propagation delay: V in W p L p V out W p L p τ fall µ n W n L n C L ( V DD V t ) τ rise µ p W p L p C L ( V DD V t ) W n L n W n L n Assume: W p = 3W n for optimum noise margin. L p = L n = L min τ rise = τ fall = γl min (W p +W n )C ox µ n C ox W n L min (V DD V t ) = γl 2 min 1+ W p µ n W n 1 = 4 V DD V t ω T Operation is 4X slower than theoretical maximum due to n-channel & p-channel gates connected in parallel. (Actual τ values will be higher due to high diffusion capacitances present in submicron transistors.) 3

4 Verifying with simulation: n-channel ac simulation to determine f T : CMOS inverter transient simulation: I G V in V out I D f T = 57GHz τ = 18ps 6.4 ω T 4

5 Single-Ended Signaling in CMOS V DD I DD V in V in V out V out I SS I SS sub I DD V SS Series R & L cause supply/ground bounce. Resulting modulation of transistor V t s result in pattern-dependent jitter. 5

6 Effect of Supply/Ground Bounce on Jitter V DD data in data out clock in clock out V SS R s = 5Ω L s = 5nH clock out R s = 0 L s = 0 V DD V SS clock out R s = 5Ω L s = 5nH data out 6

7 Summary of CMOS Gate Performance Advantages of static CMOS gates: 1. Simple & straightforward design. 2. Robust operation. 3. Nearly zero static power dissipation. Disdvantages of static CMOS gates: 1. Full speed of transistors not exploited due to n-channel & p- channel gate in parallel at load. 2. Single-ended operation causes current spikes leading to V DD / V SS bounce. 3. Single-ended operation also highly sensitive to V DD /V SS bounce leading to jitter. 7

8 Current-Mode Logic (CML) CML inverter: V DD R V out+ V out- R Based on conventional differential pair Differential operation V in+ C L C L V in- Inherent common-mode rejection I SS Very robust in the presence of commonmode disturbances (e.g., V DD / V SS bounce) 8

9 DC Biasing of CML Inverter V DD R I R SS _ I SSR _ R V in(dc ) =V out(dc ) =V DD 1 2 I SSR V OUT(DC ) V OUT(DC ) To keep current source transistor in saturation: V IN(DC ) + V GS W L V S I SS W L V IN(DC ) V + GS V S >V bias V t V S =V in(dc ) V GS V BIAS V in(dc ) >V bias + ( V GS V t ) 9

10 Logic Swing & Gain of CML Inverter V DD V high =V DD V low =V DD I SS R R V out+ V out- R V swing = I SS R C L C L To achieve full current switching: V in+ W L W L V in- V swing ( V GS V t ) = ID =I SS 2I SS µ n C ox W L V min I SS V swing = R 1 V min 2 µc W ox L I SS V swing V min > 1 for correct operation 10

11 Small-Signal Behavior of CML Inverter Small-signal voltage gain: rise/fall time constant: A v = g m R = R µc ox W L I SS Recall V swing = R 1 V min 2 µc W ox L I > 1 SS τ = RC L C L = γc ox WL (Assuming fanout of 1) V swing V min = A v 2 A v 2 for full switching τ = R(γWLC ox ) Note: rising & falling time constants are the same 11

12 Speed vs. Gain in Logic Circuits fast input transition: step response determined by τ slow input transition: step response determined by A v 12

13 Relationship between A v, τ, and V swing A v = R µc ox W L I SS A 2 W v = µc ox L I SSR 2 = µ γl ( RγWLC 2 ox ) ( I SS R) τ = R(γWLC ox ) V swing = I SS R A v 2 = µ γl 2 τ V swing A v 2 τ = µ γl 2 V swing large-signal gain-bandwidth product Larger logic swing preferred for higher gain-bandwidth product Larger V swing Larger V min smaller W/L larger current density 13

14 Thought Experiment R R R R W L W L W L W L I SS I SS Suppose we decrease current density by increasing W/L: W L 2 V min 1 2 R 1 2, C L 2 τ = RC 2 Slower! 14

15 Note that the load is only one gate capacitance: τ = RC L = R g m ω T = A v ω T 2 ω T CML speed ~ 2.5 times faster than static CMOS n-channel ac simulation to determine f T : CML buffer transient simulation: I G I D τ = 8ps 2.9 ω T f T = 57GHz 15

16 Typical V swing : 0.3 V DD Should be large enough to allow sufficient gain-bandwidth product. Should be small enough to prevent transistors from going into triode. * CML will still work in triode (unlike BJT), but there is no additional speed benefit. V swing = I SS R Once V swing has been chosen, designer can trade off between gain & bandwidth by parameterizing between R & I SS : τ = R(γWLC ox ) Higher speed: I SS R A v = R µc ox W L I SS Higher gain: I SS R 16

17 Other Benefits of CML Gates 1. Constant current bias V DD /V SS bounce greatly reduced I SS KCL sets this current to be nearly constant. I SS 17

18 V DD data in data out clock in clock out V SS clock out R s = 0 L s = 0 R s = 5Ω L s = 5nH V DD V SS clock out R s = 5Ω L s = 5nH data out 18

19 2. Non-inverting buffer available without additional delay: CMOS: t p 2t p inverter buffer CML: V out+ V out+ V out V out+ V in+ V in V in+ V in inverter buffer 19

20 Fanout & Scaling of CML Gates R R 1x = V in+ V out- W L V out+ W L V in- I SS R/n R/n V out- V out+ nx = V in+ n W L n W L V in- All voltages unchanged from unit-sized buffer. Currents & power increase by factor of n. ni SS 20

21 For fanout of n: τ = nc L R A v 2 τ = 2µ nγl 2 V swing τ increases linearly with fanout. 21

22 From interconnect, etc.; assumed not to scale with buffer sizes τ = ( nc L +C p ) ( R / n) = γwlc ox R 1+ C p nc L A v 2 = 2µC ox nw L ( ni SS ) ( R / n) 2 W = 2µC I ox L SS R2 τ = 2µ γl V 2 swing 1+ C p nc L A v 2 1 Should set n 0.1 ( C p /C L ) to minimize degradation due to interconnect capacitance Power (proportional to n) determined primarily by interconnect capacitance! 22

23 Sub-micron MOSFETs obey square-law characteristics only in a limited region! I D I D Mobility reduction (linear) + V GS _ Square-law behavior Weak inversion (exponential) CML buffer design procedure: V GS 1. Determine largest allowable I SS (usually limited by electromigration constraints) 2. Choose unit-sized n-channel transistor (typically W/L=20) 3. Run a series of simulations to determine optimum value of R: R too small: full current switching not achieved R too large: slower than necessary 4. Choose minimum scaling factor after laying out some test buffers of various sizes and determining approximate value of interconnect capacitance C p. 23

24 1. Determine largest allowable I SS standard layout shared drain (1/2 diffusion capacitance) I D I max I max independent of W determined by electromigration limits 24

25 CML Design Procedure Example Choose: I SS = 400µA W L = 4 µm 0.18 µm R = 900 I SS R = 360mV t p = 10ps R too small R = 1200 I SS R = 480mV t p = 12ps *R optimum* R = 1500 I SS R = 600mV t p = 14ps R too large 25

26 Parameterizing Between Gain & Bandwidth I SS = 100 µa R = 4.8 kω A v = 9.3 db BW = 2.6 GHz I SS = 200 µa R = 2.4 kω A v = 7.1 db BW = 5.5 GHz I SS = 400 µa R = 1.2 kω A v = 3.9 db BW = 11.5 GHz 26

27 Parameterized CML Buffer R GBW GSCALE MSCALE W L GSCALE MSCALE I SS GSCALE MSCALE GBW GSCALE: Global scaling parameter (depends on C p ) MSCALE: Local scaling parameter (depends on fanout or bit rate) GBW: Gain-bandwidth parameter 27

28 CML with p-channel Active Load Can be used if linear resistors are not available. p-channel load transistors operates in triode region: Increased capacitance and mismatch result 28

29 Capacitance Comparison (1) Poly resistor: p-channel MOSFET: C 1 2 C poly sub C C depletion + 1 ( 2 C + C channel gate channel sub) gate channel sub 29

30 Capacitance Comparison (2) (Numbers based on TSMC 180nm CMOS process) C poly-sub C channel-sub : 0.13 ff/µm 2 C depletion : 1.20 ff/µm 2 C channel-gate : 7.80 ff/µm 2 Poly resistor: W poly = 0.6 L poly = 2.5 C 1 2 C poly sub = 0.1 ff p-channel MOSFET: W channel = W diff = 2.5 µm L channel = 0.18 µm L diff = 0.3 µm ( ) C C depletion C channel gate + C channel sub = 0.9 ff ff +.03 ff = 2.8 ff 30

31 Capacitance Comparison (3) R = 1.2 kω ρ s = 235 Ω/ W r = 0.6 µm L r = 2.5 µm C res = 0.1 ff W p = 2.5 µm L diff = 0.3 µm C d2 = 2.8 ff M 2 M 2 M 1 M 1 M 1 M 1 C d1 = 3.7 ff C g1 = 5.8 ff 31

32 Pulse Response Comparison PW in = 100ps resistor load R = 1.2 kω t d = 16 ps; PW out = 100 ps p-channel load (W/L) p = 2.5 µm / 0.18 µm t d = 20 ps; PW out = 98 ps 32

33 Eye Diagram Comparison including mismatch effects σ R R resistor load = 1.5% mismatch p-channel load σ ID I D = 4% mismatch 160mV gate-referred mismatch DCD ISI 33

34 Series-Gated CML Topology XOR gate: M A M A M A M A M B M B Common-mode voltage of BP/N critical: Too low current source transistor biased in triode Too high Transistors M B biased in triode 34

35 Series-Gated CML (2) V S BP I 1 I 2 BN V BP V BN I 1 I 2 I SS Transistors should be biased in saturation to realize maximum g m. V BP V BN Especially important when gate voltages exhibit slow slew rates -I SS Slope = g m 35

36 I BP I BN V B(cm) = 1.0 V B(cm) = 1.3 DC current: V B(cm) = 1.6 I BP I BN V B(cm) = 1.3 V B(cm) = 1.0 V BP V BN Transient response: (400mV amplitude sine wave applied to BP/BN) V B(cm) = 1.6 t 36

37 Level-Shifting CML Buffer Used to drive clock inputs of series-gated CML gates V DD + I SS R cm _ R R cm R Output levels: ( V DD I SS R cm ) ( V DD I SS R cm ) I SS R I SS 37

38 CML Select Circuit Be reassigning the inputs, the XOR can be transformed into a Select circuit. Used in a 2:1 multiplexer. R OUTN R OUTP SELA AP AN BP BN AP/N SELA SELB BP/N I SS OUTP/N 38

39 CML Latch By setting BP/N = OUTP/N, we can construct a CML latch: OUTN OUTP DP DN CKP CKN I SS 39

40 CML D Flip-Flop QIN QIP OUTN OUTP DP DN QIP QIN CKP CKN CKN CKP CKP/N DP/N Output OUTP/N is synchronized with CKP/N falling edge. OUTP/N 40

41 CML Latch Design Considerations R R slope=1/r gg I GG V GG 1 2 I SS dc operating points V GG I GG Necessary criterion for bistability: r gg = 2 2R = 1/ R g m 1 g m R < 0 (Equivalent to loop gain = g m R > 1) at middle operating point 41

42 Avoiding Latch Transparency g m R > 1 g m R 1 g m R 1 transparent latch 42

43 QIN QIP OUTN OUTP DP DN QIP QIN CKP CKN CKN CKP GBW parameter can be increased to ensure bistability. R=1000 g m R > 1 R=800 g m R 1 R=600 g m R < 1 43

44 Buffering Clock Signals (1) Clock signals (generated from VCO or clock divider) often drive large capacitive loads. 1x 1x C n C 1x Fanout = n C τ = nrc f 3dB = 1 2π τ For a large fanout, attenuation of clock amplitude will occur. 44

45 Buffering Clock Signals (2) kt p 1x k x k 2 x n x m stages Now τ is increased by k << n less attenuation at each stage Delay = mkt p Power = P 1 (1 + k + k n) Power dissipated by first stage As f clock 1/t p then k 1; number of stages and total power become very large. 45

46 Buffering Clock Signals (3) Since clock signal is made up of a single frequency (+ harmonics), resonance can be used to increase gain with greatly reduced power dissipation. Y = 1 R + jωc + 1 jωl = (1 ω2 LC) + jω(l / R) jωl Resonant frequency: ω r = 1 LC Y = 1 R at resonance If lossless inductors were available, we could achieve high gain at any frequency simply by choosing the correct inductor value. 46

47 On-Chip Passive Elements Resistor: t l w l R = ρ t w Capacitor: d l w l C w ε d (+ fringing) substrate Inductor: t l w L ln t + w l ph/µm l t + w 3 l Inductance calculation much more complicated! 47

48 t l w L ln t + w l ph/µm l t + w 3 l Special case of Greenhouse result Note for l >> W, L is a weak function of w To increase effective inductance per unit length, we make use of mutual inductance via spiral structure: 48

49 Modeling of Spiral Inductor 1 2 Accurate lumped model should include: Series inductance (self + mutual) & resistance Skin effect (frequency dependent series resistance) Interwinding capacitance Capacitance to substrate Substrate capacitance & loss number of turns n = 2 Design of inductor requires: inductor simulation package (e.g., asitic) trial and error conversion to lumped element model Procedure for constructing lumped model: 1. 2-port s-parameters over frequency range of interest (this comes from the inductor simulator) 2. Choose lumped circuit topology. 3. Run simulations to find the optimal lumped circuit element values such that the the circuit s-parameters are sufficiently close to the inductor s s-parameters (can use.net and.optimize in HSPICE) 49

50 Modeling of Spiral Inductor (cont.) Link to asitic web pages: Parameters most relevant to circuit designers: Inductance Series resistance Self-resonant frequency 50

51 Modeling of Spiral Inductor (cont.) C int L R s 2 C ox1 C ox2 R sub1 C sub1 C sub2 R sub2 L: R s : C int : C ox : C sub /R sub : Self/mutual inductance Series resistance Interwinding capacitance Oxide capacitance Substrate capacitance/resistance Values of L and R s in lumped model should correlate with physical parameters. Values of other lumped model elements need not necessarily correlate with physical parameters. 51

52 Parasitic capacitances usually combine with load capacitance L decreases slightly Series R s has more important effect: L C R L C R R s Y = 1 R + jωc + 1 R s + jωl At resonance, Im [Y(jω r )] = 0: 2 1 ω r = LC R s L Y( jω r ) = 1 R + CR s L 2 L = L 1 CR s 2 L Slight increase in effective inductance R = R Y = 1 R + jωc + 1 jω L 2 1 ω r = L C Y ( jω r ) = 1 R L CR s Very important effect! 52

53 CML Tuned Amplifiers (1) Differential-mode ground Sets common-mode output voltage C L resonates out with L Gain at resonant frequency = g m R 53

54 CML Tuned Amplifiers (2) Symmetric inductor structure can be used: Single structure allows more inductance to be realized from mutual coupling less series resistance 54

55 CML Tuned Amplifiers (3) Higher-gain topology: Gain is much higher at resonance, but depends completely on R s. Variation in gain correlates with variation in metal (not resistor) sheet resistance. 55

56 CML Tuned Amplifiers (4) Watch out for ac current amplitude in inductors! I in + I L V swing L C R _ I in = V swing R I L = V swing ω L Let V swing = 500mV, L=0.5nH, f =10GHz: I L = 16mA Spiral inductor should be wide enough to meet ac electromigration specs. 56

57 V in R Inductors in Broadband Circuits C R + V out V in R LC lossless transmission line (Z 0 ) R + V out _ H(s) = s CR 2 H( jω) H( jω) H(s) = 1 2 e st d for R = Z 0 T d = LC H( jω) 2 CR ω H( jω) ω ω ω 90 slope = -T d 57

58 Series Peaking (1) With direct connection of 2 buffers, output & input capacitances are in parallel: C d C g By connecting an inductor between the capacitors, the bandwidth and delay increase: L ser C d C g Series peaking 58

59 Series Peaking (2) R V x- L Using R ser set L C ser C d R 2 d V x+ L ser V in+ V in- C d C g Series peaking provides speed at the expense of extra delay. C d = C g = 16 ff R = 400 Ω Frequency response: Transient response: V x V in L ser = 0 BW = 6.3 GHz L ser = 3.5 nh BW = 8.3 GHz V x (L ser = 3.5 nh) V x (L ser = 0) V x V in L ser = 3.5 nh V in L ser = 0 59

60 Shunt-Peaking (1) By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer time, to charge the load capacitance. 60

61 Properties of Shunt-Peaking Frequency response: C L Z( jω) = R 1+ jω L R ( 1 ω 2 LC L ) + jωc L R 1+ s L Z(s) = R R 1+ sc L R + s 2 LC L Im s Resonant frequency: ω r 2 = 1 LC L 1 C L R2 L X L 0: zero at s = R/L additional pole at s (1/CR + R/L) O X L = 0: pole at s = 1/RC Re s No resonance for L C L R 2 < 1 61

62 Shunt-Peaking -- AC Response C L = 38 ff R = 400 Ω L C L R 2 = 0.3 L = 1.8 nh BW = 9.4 GHz Use of shunt-peaking increases small-signal bandwidth L = 0 BW = 6.3 GHz L C L R 2 = 0.6 L = 3.7 nh BW = 14.3 GHz 62

63 Shunt Peaking Transient Response (1) Step Response: Pulse Response (Δt in = 50 ps): L = 3.7 nh t d = 6.7 ps L = 1.8 nh t d = 8.5 ps L = 0 t d = 13.4 ps L = 3.7 nh Δt out = 50.8 ps ISI = 16 mui L = 1.8 nh Δt out = 50.0 ps ISI = 0 mui L = 0 Δt out = 48.7 ps ISI = 26 mui 63

64 Other Advantages of Shunt-Peaking CML load is passive & linear Can be shown to be very robust in the presence of parasitic series resistance and shunt capacitance inductors can be placed far away from other CML circuit elements. 64

65 Effect of Shunt-Peaking Inductor Parasitics (1) L L long metal lines L C P C P L R P R P R R R R C L C L C L C L Series resistance R P simply adds to R Shunt capacitance C P resonates with L 65

66 Effect of Shunt-Peaking Inductor Parasitics (2) C P = 0 Moderate amount of parasitic capacitance has similar effect to slightly larger inductor. L C L R 2 = 0 L C L R 2 = 0.6 L C L R 2 = 0.3 Disadvantages of using passive inductors: Consume huge die area Difficult to design & model C P = 0.2C L L C L R 2 = 0 L C L R 2 = 0.6 L C L R 2 =

67 Multi-layer Inductors (1) metal 6 d metal 6 metal 5 metal 5 d Distance d between two metal layers is much smaller than lateral distances (e.g., w, l, s) 67

68 Multi-layer Inductors (2) 2-port representation of coupled inductors: M = k L 1 L 2 i 1 i 2 series connection of coupled inductors: i M + φ 1 L 1 L 2 φ 2 φ 1 _ L 1 L 2 φ 2 _ Passivity constraint: k 1 i 2 φ 1 φ 2 = L 1 M i 1 M L 2 i 2 For metal geometries close to each other, k is close to unity. φ series = φ 1 +φ 2 = (L 1 + M)i 1 + (L 2 + M)i 2 i series = i 1 = i 2 For L 1 = L 2 = L, we have: L series = 2L + 2M = 2L(1+ k) 4L In general, for n layers we have: L series n 2 L L series = φ series i series = L 1 + L 2 + 2M Multi-layer inductors are more appropriate for shunt-peaking than resonant structures due to additional contact resistance. 68

69 Multi-layer Inductors (3) Effective Capacitance: L effective 4L C effective 1 3 C i C j C i C j For more details, see: A. Zolfaghari, A. Chan & B. Razavi, Stacked inductors and transformers in CMOS technology, IEEE Journal of Solid-State Circuits, vol. 36, April 2001, pp

70 Multi-layer Inductors (4) Area comparison: metal 6 only 100µ x 100µ w = 4; s = 2; n = 4 L=2.0 nh R=6.9 Ω metal 6 over metal 4 46µ x 46µ w = 4; s = 2; n = 2.5 L=2.0 nh R=12.5 Ω + 70

71 Active Inductors (1) Ideal gyrator: Impedance inversion: i 1 R gyr i 2 i in R gyr v 1 _ v 2 _ v in _ C v 1 v 2 v 2 = R gyr i 1 v 1 = R gyr i 2 Matrix representation (Z-parameters): 0 R = gyr i 1 R gyr 0 i 2 2 Z in = R gyr ( sc) Port 1 exhibits inductance when port 2 is connected to a capacitance. 71

72 Active Inductors (2) Consider common-drain configuration: i 1 applied with port 2 open-circuited: v 2 = 1 g m i 1 R G i 2 + v 2 i 2 applied with port 1 open-circuited: v 1 = R G 1 g m i 2 (Assume R G g m > 1) v 1 i 1 + Complete Z-parameters (lossy/active gyrator): v 1 v 2 ( ) = 1 g m R G 1 g m 1 g m 1 g m i 1 i 2 72

73 Active Inductors (3) Interpretation of non-ideal matrix entries: v 1 v 2 = 1 g m 1 g m R G i 1 1 g m 1 g m i 2 + v in _ 73

74 Active Inductors (4) Impedance at port 1 with port 2 terminated with transistor C gs : At low frequencies (C gs open) Z source = 1/g m At high frequencies (C gs short) Z source = R G Z source = 1 g m 1+ sc R gs G 1+ s C gs g m 74

75 Active Inductors (5) Equivalent circuit: R G Z source L eff C gs R G g m = R G ω T + 1 g m 1 g m 1 g m ω v in _ C gs R G g m R G 1 g m C gs R G C gs g m R G > 1 75

76 CML Buffer with Active Inductor Load Low-frequency gain: A v = g m 1 g m 2 = W 1 W 2 For shunt peaking: L 0.3C L R 2 W L 1 = W L 2 = C gs R G g m 2 = 0.3 C L g 2 g m 2 R G = 0.3 C L m 2 C gs I SS = 400 µa 76

77 Active Inductor AC Response R G = 4k R G = 2k R G = 0 77

78 Active Inductor Transient Response (1) Differential signals: R G = 0 PW = 97ps R G = 5k PW = 100 ps R G = 10k PW = 104 ps 78

79 Active Inductor Transient Response (2) Single-ended signals: Problem: n-channel load shifts output by V t. V sb > 0; body effects exacerbates this effect.. Single-ended input Single-ended outputs 79

80 Active Inductor Alternate Topology Alternate topology: p-channel load exhibits lower V t (V bs = 0) differential single-ended 80

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