1 Introduction 1. 2 Elements of filter design 2. 3 FPAA technology Capacitor bank diagram Switch technology... 6

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1 MS Thesis of hristian Birk Application and Evaluation of FPAA Table of contents 1 Introduction 1 Elements of filter design 3 FPAA technology apacitor bank diagram Switch technology Analysis of s/c circuits, theory and technique Basic concept of the s/c technique Analysis of parasitic insensitive integrators Non-inverting integrator Inverting integrator Signal flow graph analysis Sources of error in FPAA operation apacitor error model Quantization error Macroscopic manufacturing errors Microscopic manufacturing errors Additional interconnect capacitances Operational amplifier errors Limited bandwidth Finite gain...19

2 Table of contents Finite input and zero output impedance Errors due to time-discrete filter implementation omparison of continuous and s/c biquad filter Approximation methods for z- to s-domain mapping Forward Euler transform Backward Euler transform Bilinear transform alculation of new capacitor size selection rules Low-Q filter implementations High-Q filter implementations Low-pass filter realizations Low-pass, low-q filter Low-pass, high-q filter High-pass filter realizations High-pass, low-q filter High-pass, high-q filter Band-pass filter realizations Band-pass, low-q filter Band-pass, high-q filter Band-stop filter realizations Band-stop, low-q filter Band-stop, high-q filter apacitor size scaling Filter measurements Measurement setup Evaluation of the chip performance omparison between z-domain analysis and measurements...43

3 Table of contents 7.. Variations among different cells omparison of capacitor size selection rules Low-pass, low-q filter measurements Low-pass, high-q filter measurements High-pass, low-q filter measurements High-pass, high-q filter measurements Band-pass, low-q filter measurements Band-pass high-q filter measurements Band-stop, low-q filter measurements Band-stop high-q filter measurements Analysis of results alculation of an overall error bound Definition of error in db Magnitude error in db Magnitude error bound in db Error bound graphs Low-Q filter error bound High-Q filter error bound omparison of error bounds and measurements Measured error and error bound for low-pass, low-q filter Discussion of other filter implementations haracterisation of s/c circuits Switched current technique onclusions and further research References 87

4 Table of contents

5 1 1 Introduction This document deals with the design and evaluation of electronic filters implemented on a Field Programmable Array (FPAA). Filters occur widely in electronic circuits associated with modern audio, communications, and signal processing fields. In audio systems, filters are used for pre-amplification, equalization, and tone control. ommunication circuits use them for the tuning of specific frequencies and the elimination of others. In telephony, filters are used to decode the tone frequencies used for dialing. Digital signal processing systems incorporate filters to prevent aliasing and to reconstruct the signal. In fact, it is difficult to find any moderately complex electronic device that does not contain one or more filters. Variations in filter implementations have evolved drastically over the years as a result of changes in technology. Originally, electrical filters were realized in the form of RL circuits. As it is difficult to have accurate inductors for mass production, the fact that active components of good quality were developed improved the situation. Especially when operational amplifiers became available in large scale, they provided a means for eliminating inductors, thus leading to active R filters. With the introduction of fully integrated monolithic filters, new techniques like switched capacitors found a very broad range of applications, as the use of MOS switches and capacitors allowed for eliminating chip-area consuming resistors on the chip. Applying the FPAA, filters are set up using switched capacitor (s/c) technology with variable capacitor sizes to implement a desired filter. As it will be shown, not only the variety of possible circuits that can be implemented on the chip makes the FPAA so outstanding but also the accuracy of its operation confirmed by measurements.

6 Elements of filter design Electronic filters comprise a specific class of systems which can be looked at as frequency-selective signal transmission devices. Signals of certain ranges of frequencies belonging to the pass-bands are passed from the input to the output, while others in the stop-bands are rejected. Using a FPAA, numerous applications incorporating filters are possible. Signal conditioning of sensors may include amplification, linearization and filtering, which all can be done on one FPAA. Apart from that, filtering in audio-frequency applications, remote sensing, and even adaptive filter implementations are possible areas were a FPAA can be successfully utilized. The usual way filters are designed is to have a concrete specification of the transmission characteristics of the filter. This, of course, does not mean a specification in the form of an ideal characteristic, since physical circuits are unable to realize idealized characteristics. What we have to specify is bounds for the deviation of the pass-band transmission from the ideal db and what is allowed to be transmitted in the stop-band, specified by a minimum attenuation. Apart from that, a transition band is introduced which extends from the pass-band edge frequency to the stop-band edge frequency in the case of a low-pass filter. The ratio of these two is a measure for the sharpness of the low-pass filter response. To summarize the low-pass example, there are four parameters to be set, the pass-band edge frequency, the maximum allowed variation in pass-band transmission, the stop-band edge frequency, and the minimum required stop-band attenuation. For high-pass filters the requirements are identical, whereas in the band-pass and band-stop case there are some more parameters needed. Once all the specifications are fixed for the respective application, one has to think about how to transform the filter information into an actual transfer function. This process is called filter approximation. Usually, this is performed using computer programs. Functions which are frequently used for the approximation procedure are Butterworth filter functions, hebyshev filter functions, and Elliptic or auer filter functions. [Huelsman 1993, Van Valkenburg 198].

7 Elements of filter design 3 As a result of the approximation, we get the transfer function in the s-domain. Its order is dependent on how tight the specifications are formulated. The most straightforward way how filters are implemented on the Field Programmable Analog Array is that we cascade second order filter transfer functions, and, in the case of an odd filter order, one first order transfer function. As the output impedance of each block is taken at the output terminal of an operational amplifier where the impedance level is low (ideally zero), the transfer functions of the individual blocks are not changed by cascading. Due to the availability of operational amplifier cells, it is possible to realize a filter of th order on one FPAA-chip. In the following text, we will only concentrate on second order transfer functions, as they are the major building blocks for higher order filters. If the behavior of the second order transfer function implementation is known and understood, it is only a very small step to implement filters of higher order. Then, the main issue is the filter approximation.

8 4 3 FPAA technology The FPAA in its current version, the MPAA, is an electronic breadboard that provides an ideal medium for quickly designing, debugging, and implementing a wide array of analog circuits, which reduces development cycle times and enables the user to meet market introduction timelines. The technology for the FPAA is based upon switched capacitor circuit technology. Analog resources in the MPAA are contained in configurable analog blocks (AB s) which incorporate a switched capacitor MOS operational amplifier, comparator, capacitor banks, MOS switches and SRAM. The function of each cell may be programmed to connect with any of the other cells in the array. Data stored in SRAM control the switches that program various capacitance values, for both static and dynamic capacitors, in the input and feedback signal paths of the operational amplifier. Analog functions such as programmable gain stages, adders, subtractors, rectifiers, sample & hold circuits, and first order filters can be implemented in a single cell (AB). Higher level functions such as biquad filters, which are subject of this study, PLL s, level detectors, and others can be implemented using two or more cells. The MPAA contains 41 operational amplifiers, 1 programmable capacitors, and 6864 switches. The switches control circuit connectivity, capacitor values, and other selectable features. The array is structured in a grid that contains AB s arranged in a 4 5 matrix. The programmable AB s rely on the configuration logic on the chip to control the connectivity within the array and functionality in each AB. An 8-bit programmable band-gap voltage reference is available to each cell. onfiguring an analog design within the array is performed by downloading 6K bits of data via RS3 communications from a P or EPROM. The data stream contains information to configure the individual cells, the cell to cell interconnections, internal voltage reference as well as the input and output connections. During the configuration download process, all cells are placed in a power-down mode, which is exactly what is done with individual cells not in use by the actual design in order to minimize the power dissipation. [Motorola 1997b, Motorola 1997c, Motorola 1997d].

9 3 FPAA technology apacitor bank diagram Generally, in s/c circuits unit capacitors within one capacitor bank are connected together in parallel to obtain the desired capacitor value. The number of possible capacitor values is only limited by the bank size if a binary configuration is used, which is shown in the following diagram: Figure 3-1. Schematic of capacitor bank organization. In Figure 3-1, the squares represent unit capacitors of size u. Their number defines the maximum size of a capacitor that can be implemented using a single bank. The bank capacitors are arranged in groups of unit capacitors as shown in Figure 3-1, so that these unit capacitors add up. Such connected capacitors are called sub-arrays, and these sub-arrays are organized in binary fashion, so one capacitor bank consists of sub-arrays with capacitor values 1u, u, 4u, 8u, 16u, 3u,.... In the case of the MPAA, all capacitor banks consist of 56 unit capacitors, which means that the largest sub-array is composed of 18u. Altogether, we can realize all integer capacitor sizes between 1u and 55u. One unit capacitor, in the above diagram the first one, is not used and therefore has only dummy function. The reason why it has been implemented is to maintain the square symmetry of the whole capacitor bank layout.

10 3 FPAA technology 6 The fact that we can only realize integer capacitor values will be accounted for in a following section, as quantization effects significantly contribute to the circuit performance. Wherever the design allows for, we try to parallel two capacitor banks within on cell to double the maximum capacitor value. A more detailed description of the capacitor bank including a capacitor error model is presented in [Palusinski et al. 1997b]. 3. Switch technology Dynamic and static switches on the FPAA are implemented in MOS technology. Not only does a MOS transmission gate offer extremely low power consumption, but also effects caused by clock feed-through can be eliminated or minimized by proper design. Apart from that, MOS has a wider valid input signal range than for example a single NMOS switch. V dd Signal In F F Signal Out V ss Figure 3-. MOS transmission gate used as a switch. In the text to follow, wherever a MOS transmission gate according to Figure 3- is employed, we will simply draw a switch symbol for the sake of drawing simplicity. However, for practical implementations the actual realization should always be kept in mind.

11 7 4 Analysis of s/c circuits, theory and technique Switched capacitor circuits operate as time-discrete signal processors without the use of A/D or D/A converters. As a result, these circuits are most easily analyzed with the use of z-transform techniques. Typically, anti-aliasing and smoothing or reconstruction filters are required. Especially for filtering, switched capacitor circuits have become extremely popular due to their accurate frequency response as well as good linearity and dynamic range. Accurate discrete-time frequency responses are obtained since filter coefficients are determined by capacitor ratios which can be set quite precisely in an integrated circuit (in the order of.1 percent). Such an accuracy is orders of magnitude better than that which occurs for integrated R time constants (which can vary by as much as percent). Once the coefficients of a switched capacitor discrete-time filter are accurately determined, the overall frequency response remains a function of the clock frequency. Fortunately, using crystal oscillators, clock frequencies can be set very precisely. [Johns and Martin 1997]. 4.1 Basic concept of the s/c technique The switched capacitor technique is based on the realization that a capacitor switched periodically between two circuit nodes is equivalent to a resistor connecting these nodes if we are interested in an average value of current over a period of time exceeding a number of times the switching period. A circuit diagram for this basic s/c circuit is shown in Figure 4-1: v in 1 v out Figure 4-1. Basic s/c circuit replacing a resistor for high switching frequencies. During the time when the switch is in position 1, the capacitor is charged to the voltage applied to the input, v in. So the total charge on the capacitor is Q 1 = v in in steady state. When the switch changes to

12 4 Analysis of s/c circuits, theory and technique 8 position, the new charge on the capacitor for the steady state will be Q = v out. The net charge transferred from the input to the output during one switching period is then DQ = Q - Q = vin - v 1 ( out ). (4-1) This is equivalent to a current i flowing from the input to the output, D Q ( vin - vout ) i = =, (4-) T T and from this equation we can easily calculate an equivalent resistor value T R =. (4-3) It can be seen that in order to determine the resistance value both, the clock period and the capacitance, have to have specific values. 4. Analysis of parasitic insensitive integrators 4..1 Non-inverting integrator v in Φ 1 Φ 1 Φ Φ 1 _ v out Figure 4-. A realization of a non-inverting integrator using s/c circuit simulating a negative resistor. The output voltage v out is only valid during clock phase F 1 when F 1 is high and appropriate switches are closed. Figure 4- as well as all of the following s/c circuits make use of both clock phases, F 1 and F, which are defined according to the following clocking scheme (Figure 4-3):

13 4 Analysis of s/c circuits, theory and technique 9 Φ 1, Φ v on Φ Φ 1 Φ Φ 1 Φ Φ 1 v off n-3/ n-1 n-1/ n n1/ n1 t T Figure 4-3: Two phase non-overlapping clocking scheme used in s/c circuits. To analyze the circuit in Figure 4-, the charge behavior has to investigated. Obviously, a virtual ground appears at the operational amplifier s negative input. Assuming an initial integrator output voltage of v ( out nt - T ), then the charge on is equal to v ( nt - T ) at time ( nt - T ). At that time, F 1 is just out turning off (F is off), so the input signal v in is sampled, leading to a charge on 1 being equal to 1 v ( nt - T ). When F goes high, 1 is forced to discharge as it is connected to ground with the left in plate and to virtual ground with the right plate. The discharging current flows through, so the charge on 1 is added to. A positive input voltage will result in a positive voltage across and therefore a positive output voltage. At the end of F we obtain the charge equation vout ( nt - T / ) = vout ( nt - T ) 1 vin( nt - T). (4-4) The charge on at time ( nt ) at the end of the next F 1 is equal to that at time ( nt - T / ), so we can write v ( nt ) = v ( nt - T ) v ( nt - T ). (4-5) out out 1 in Dividing equation (4-5) by and applying the z-transform yields -1 1 V z z V z z -1 V z out ( ) = out ( ) in ( ). (4-6) Therefore, the transfer function can be expressed as Vout ( z) H ( z) = = V ( z ) in 1-1 z 1- z -1, (4-7)

14 4 Analysis of s/c circuits, theory and technique 1 which comprises a non-inverting discrete-time integrator with a delay of a full clock period from input to output (represented by the z -1 in the numerator). Or, in other words, equation (4-7) states the Forward Euler z-transform of a non-inverting continuous-time lossless integrator. 4.. Inverting integrator v in Φ 1 Φ 1 Φ 1 Φ _ v out Figure 4-4. A realization of an inverting integrator using s/c circuit simulating a positive resistor. As can be seen from comparison of Figure 4- and Figure 4-4, the only difference between these two circuit diagrams is that two switches with their respective on-phases are exchanged. Using similar arguments as before, the above circuit (Figure 4-4) can be analyzed which yields the charge equation vout ( nt ) = vout ( nt - T ) - 1 vin ( nt ). (4-8) Analogously dividing by and taking the z-transform, we get vout ( z) H ( z) = = - v ( z) in z - 1, (4-9) which is the transfer function for a delay-free inverting discrete-time integrator or, to be more precise, the Backward Euler z-transform of an inverting integrator. 4.3 Signal flow graph analysis It would be quite tedious to perform charge analysis on larger circuits, therefore simpler, more general analysis rules can be set up on the basis of the discussion of non-inverting and inverting integrators. onsider the integrator with multiple inputs shown in Figure 4-5.

15 4 Analysis of s/c circuits, theory and technique 11 V 1 (z) 1 A V (z) Φ 1 Φ Φ 1 Φ _ V out (z) V 3 (z) Φ 1 3 Φ 1 Φ Φ Figure 4-5. Integrator with different input circuits. Using the principle of superposition, we can analyze the circuit in Figure 4-5 by looking at one input only and setting the other two inputs to zero. Therefore, the following transfer functions are obtained: H H 3 Vout ( z) 1 H1 ( z ) = = -, V ( z) Vout ( z ) ( z) = = V ( z) Vout ( z ) ( z ) = = - V ( z) 3 1 A 3 A A (4-1) -1 z 1 1-, (4-11) - z (4-1) z - Summation of (4-1), (4-11), and (4-1) yields the overall transfer function of the circuit in Figure Now, if the operational amplifier stage is expressed as - 1 z A circuits can be calculated using the transfer functions for each branch., the formulas for the three input 1 From H 1 ( z ) we get a transfer function of ( 1 - z - ) for the non-switched capacitor input, H ( z ) yields - 3. z for the non-inverting input, and from H ( z) the transfer function of the inverting input is simply 3 These results are summarized in the following signal flow graph, Figure 4-6:

16 4 Analysis of s/c circuits, theory and technique 1 V 1 (z) 1 (1-z -1 ) V (z) - z z A V out (z) V 3 (z) 3 Figure 4-6. Signal flow graph for integrator with different input stages. It has to be mentioned that all biquad filters can be analyzed using the above derived rules for the different building blocks. The direction of the signal arrows can be determined by the assumption that the signal branches have as input signals the operational amplifier output voltages and as output signals the operational amplifier input currents. Table 4-1 shows a summary of the derived representations of s/c circuit elements which occur in s/c biquad circuits: unswitched capacitor - -1 ( 1 z ) Φ 1 Φ negative resistor - Φ Φ 1 - z 1 Φ 1 Φ 1 positive resistor Φ Φ integrator _ z Table 4-1. Basic s/c building blocks. See [Moschytz 1984] and [Johns and Martin 1997].

17 13 5 Sources of error in FPAA operation 5.1 apacitor error model The existing error model is stated in [Palusinski et al. 1997a] and explained in more detail in [Palusinski et al. 1997b]. Therefore, a very comprehensive description is not given here, but the resulting relative error bound equation is stated and its components are explained in detail. The capacitor error is defined as follows: l is the ideal capacitor of size l times the unit capacitance u, whereas l is the real capacitor value containing an error. Therefore, the relationship between l and l introducing a relative error, a( l ), can be written as: = 1 a( ). (5-1) l l l The relative error bound d ( l ) of the relative error a( l ) is expressed as 1 1 s( e) d ( l ) = q l( l) l l u, (5-) where 1 l represents the quantization error, q 1 s ( e) the microscopic manufacturing error and l( l ) the l u error due to macroscopic manufacturing errors Quantization error The first component in the equation for the capacitor error bound is the quantization error. According to chapter 3.1, on one capacitor bank we can implement integer multiples of the unit capacitor size u, expressed as lu with l in the range from 1 to 55. As it is very probable that a non-integer multiple of u is needed, we have to quantize its value to the nearest integer l in its respective range. Since we can at most require a capacitance halfway between lu and (l1)u, we can account for this error with the value of the worst case. So the relative error bound d Q = 1 l (5-3) accounting for quantization effects is obtained.

18 5 Sources of error in FPAA operation Macroscopic manufacturing errors hip manufacturing errors can be divided into two categories, which are the macroscopic and the microscopic errors. Macroscopic errors effect all capacitor banks on the chip with negligible variations, as they have a larger extent. They can even effect all of the chips on a wafer. Possible sources are edge effects on the perimeter of wafers and gradients in the oxide thickness developed during fabrication. We try to take this macroscopic errors into account by adding a bias value to the model for the relative error bound, d M = l( l). (5-4) Although we do not know exactly yet in what way the bias l really depends on the selected capacitor size, the notation l( l ) expresses that influence on the bias error could be significant in some way. However, this is not exploited yet, and more measurements and statistical analysis would be needed Microscopic manufacturing errors Microscopic errors are the error contributions inside a single capacitor bank of unit capacitors. This error is comprised of random variations between capacitors, like varying oxide thickness, size and shape of the unit capacitors caused by the plate formation and etching process. Unfortunately, we can account for this error only by a statistical statement. e is the microscopic error of a unit capacitor and is assumed to be an independent zero-mean random variable with normal probability distribution, and s ( e ) is its standard deviation. Summing up l times the e in the standard deviation for a capacitor of size l =lu yields the standard deviation of a new random variable z and can be expressed as s ( z ) = l s ( e). Then a tolerance level qs( z) is chosen, where q=3 defines 6-sigma quality requirements. So the error contribution becomes q l s( e) / u, and for the relative error we get d m = q 1 s( e) l u. (5-5)

19 5 Sources of error in FPAA operation 15 If we now assume that the macroscopic an microscopic error components are additive and independent, we obtain the relative error bound expression by adding all relative error components, d ( l ) = d Q d M d m, resulting in equation (5-). 5. Additional interconnect capacitances Apart from the capacitor error model described above, there are more error sources which are caused by the capacitor layout. Within one capacitor bank and for capacitor bank interconnections, stray capacitors effect the accuracy of the wanted capacitor size. We will refer to them as additional interconnect capacitances. Although the effort to compensate those capacitor errors is huge, they cannot be eliminated totally. Detailed observations of the actual chip behavior and theory developed from the layout diagram still confirm the existence of errors due to interconnect capacitances. In the following, we investigate bank interconnection capacitance caused by overlap of the bottom layer and the metal layer. bottom plate top plate metal layer metal layer/top plate interconnection Figure 5-1: Simplified part of the capacitor bank layout Figure 5-1 shows a simplified part of the capacitor bank layout, representing a sub-array consisting of two unit capacitors. We see that the bottom plate of a single unit capacitor is larger than its top plate. To

20 5 Sources of error in FPAA operation 16 connect a single capacitor either with the other capacitors within a sub-array or to connect two sub-arrays, metal connections (hatched area) are needed. These interconnections link the respective top plates. By inspection of Figure 5-1 it can be seen that each sub-array has a specific area of overlap of the metal layer and the bottom plate (gray-hatched area). These regions of overlap occur either due to interconnections within the sub-array or due to the connection of different sub-arrays. Therefore, depending on the capacitor size to be realized in one bank, the additional interconnection capacitor area will increase or decrease. At this point it is important to mention that the performance of a s/c circuit is not dependent on a single capacitor value but on the ratio of two capacitors. Therefore, the main goal is to keep the tracking error (i.e. the error in the ratio) as small as possible. If we now try and design the capacitor bank to get an additional interconnect capacitance exactly proportional to each possible capacitor size, the tracking error will disappear. To obtain an adequate representation, a new approach to describe the implemented capacitor of size l is chosen: M M k  k  k = k = [ l] [ ] [ ] [ l] = a a D c, a k Œ, 1 k k k p (5-6) where M equals 7 for a capacitor bank size of 55. a k stands for the binary digits in the digital capacitor size representation of l, [ k ] is the ideal capacitance containing k [ unit capacitors, and D k ] is the error term due to the aforementioned error sources plus the sub-array internal interconnections. c [ l] finally represents the interconnection capacitance between different sub-arrays. Therefore, the ideal capacitor of size l u can be expressed as   L 7 = k = k N M 7 = k = [ l] [ k ] k a a u. (5-7) k O QP The sub-array internal interconnect capacitance x [ l] of a capacitor incorporating l unit capacitors can be written in analogy to (5-7) as

21 5 Sources of error in FPAA operation 17 7 Â [ l ] [ ] x = a x = a b ( a u) k k= k = k 7 Â k k. (5-8) The b k whose numerical values are shown in Table 5-1 represent numbers in proportion to the additional capacitor area obtained by measuring the area size in the capacitor bank layout. A scaling factor a has to be introduced, so that x [ l] represents a capacitance. Its numerical value has to be determined by capacitor error measurements, which has not been done yet. b 7 b 6 b 5 b 4 b 3 b b 1 b Table 5-1. Numerical values for b k obtained by capacitor bank layout analysis. For the interconnection capacitances c [ l] between different sub-arrays, we get equation (5-9) from analysis of the layout. c [ l ] R S 3 Â a u ; a4 a > k = k = T ; otherwise, (5-9) where again the scaling factor a from above is used. Applying the above equations for each possible capacitor size to be set up with in bank, a graph (Figure 5- ) can be plotted showing the results for the different capacitor sizes. It is important to mention that the scaling factor a from the above equations (5-8) and (5-9) was chosen to be 1 as statistical capacitor error measurements were not yet available. This has no influence on the general shape of the curves.

22 5 Sources of error in FPAA operation 18 Title: ic_cap.eps reator: MATLAB, The Mathworks, Inc. reationdate: /4/98 14:31:36 Figure 5-. Additional interconnection capacitance and its linearity error. Looking at the upper half of Figure 5-, one could suppose that the curve is linear. If there were no error, we would in fact get an ideal curve of linear shape. But as can be easily seen from the computation of the relative linearity error in the lower half of Figure 5-3, there are discontinuities at certain capacitor sizes in the plot. Especially at small capacitor values, these discontinuities introduce a strong non-linearity in the graph (it wobbles ). Speaking in terms of the tracking error, it is obvious that using small capacitors in the s/c circuit decreases the accuracy of the desired capacitor ratio due to the interconnection capacity. This leads to a deterioration of the overall circuit performance. [Anderson et al. 1998].

23 5 Sources of error in FPAA operation Operational amplifier errors Limited bandwidth The operational amplifiers used as core amplifiers in each cell are designed in such a way that there is no deterioration of FPAA signals due to the maximum bandwidth of the amplifier. The maximum clocking frequency of the MPAA is 1MHz, thus the allowable input signal frequency range is limited to 5kHz by the sampling theorem. Now, the core amplifiers are designed to have a bandwidth of more than one order of magnitude higher than the highest valid input frequency. Therefore, we can neglect the error caused by bandwidth limitations of the core amplifiers Finite gain The open loop gain of the core amplifiers is higher than 9dB, which in practical terms is quite close to the ideal operational amplifier with infinite gain. So in comparison with other error sources the deviation due to the finite but very high open loop gain is negligible Finite input and zero output impedance The core amplifiers are required to have infinite input impedance and zero output impedance. This is very important for the behavior of higher order filters which are composed of second and first order building blocks in cascade. Again, due to the extremely well designed core amplifiers, we can neglect any influence of cascading on the behavior of signals. The largest potential source of error, which may be due to the connections through input and output pins on the chip is reduced by providing unity gain buffers to all input and output pins. So, for example, if a current is drawn due to a load at the output, this does not influence the internal signal at all as the current required is provided by the buffer amplifier. Therefore, we can assume ideal behavior of core amplifiers also in this case.

24 5 Sources of error in FPAA operation In general, it is not necessary to include operational amplifier errors (also those ones not mentioned here like slew rate, MRR, etc.) in the present analysis as capacitor effects dominate the error behavior of the MPAA.

25 1 6 Errors due to time-discrete filter implementation 6.1 omparison of continuous and s/c biquad filter The general second order filter transfer function (also called biquad) is usually expressed in the form K s K s K H ( s ) = - biquad w s Q s w 1 (6-1), where the parameters K, K 1, K, w, and Q specify the filtering behavior. [Sedra, Smith 1991]. An active-r realization of a low-q biquad filter is shown in Figure 6-1: R R4 V in R 1 _ A OP 1 R R 1 ' _ R OP R 3 _ B OP 3 V out 1 " Figure 6-1. Active R-realization of low-q biquad filter. The operational amplifier block in Figure 6-1 consisting of OP and the two identical resistors R in the middle of the schematic functions as a unity gain signal inverter, so for the construction of a s/c version of the circuit, the resistor R 3 can be interpreted as a negative resistor. Using KVL and KL to analyze the remaining circuit, the ideal transfer function in the s-domain for the low-q biquad circuit is H ideal lowq " s 1 A ( s) = - s A B A R s 1 ' R R A R s 1 R R 4 3. (6-)

26 6 Errors due to time-discrete filter implementation Now, if all resistors are replaced by their ideal switched capacitor equivalents, which means that the T resistor values are substituted by R = (holding for very high clock frequencies), we get the following expression: H contlowq " ' s 1 s T A T ( s) = Bs s 4 T T A (6-3). This is an approximate transfer function, valid only for rough calculations, as the error introduced by the assumption of an infinite clock frequency increases with increasing signal frequencies. In the actual circuit implementation, instead of replacing the resistors in Figure 6-1 by the stray sensitive basic s/c circuit in Figure 3-1, the s/c building blocks from Table 4-1 are used, as these circuits not only offer insensitivity against stray capacitances but also positive and negative equivalent resistor. The following schematic given in Figure 6- is identical to the circuit of Figure 6-1 with the resistors simply replaced by their s/c equivalents. Φ Φ Φ 1 Φ 1 Φ 4 Φ Φ 1 Φ 1 V in Φ 1 Φ Φ 1 Φ 1 _ A Φ 1 3 Φ Φ Φ 1 _ B V out Φ ' 1 Φ Φ 1 Φ 1 1 " Figure 6-. Implementation of low-q biquad filter circuit in s/c technology.

27 6 Errors due to time-discrete filter implementation 3 To perform exact analysis, it is convenient to transform the original s/c circuit (Figure 6-) into a signal flow chart. To do so, we use the rules stated in chapter 4.3, which yield the representation shown in Figure 6-3: 4 V in z A z z B V out 1 ' " ( 1 z ) Figure 6-3. Signal flow chart representation of the s/c circuit implementing a low-q biquad. Analysis of this circuit in the z-domain yields the transfer function H ' " ' " " ( 1 1 ) z ( ) z ( z) = - / ( ) z ( - - ) z s c lowq A A A A B 4 A 3 4 A A B A B. (6-4) At this point it is important to mention that the actual s/c implementation of the above filter circuit looks slightly different. areful examination of the circuit in Figure 6- reveals that some of the switches are redundant. Using the technique called switch sharing, circuit designers implement the s/c filter in the fashion presented in Figure 6-4, without any degradation of performance.

28 6 Errors due to time-discrete filter implementation 4 Φ 1 Φ V in Φ Φ 1 1 Φ Φ 1 _ A Φ 1 Φ 4 3 Φ Φ 1 _ B V out 1 ' 1 " Figure 6-4. Switch sharing applied to the s/c circuit of a low-q biquad. As mentioned before, the discussed implementation yields low-q filters. The same derivation is now done for a high-q biquad filter, which can be realized in active-r fashion as shown in Figure 6-5. R 1 ' 4 V in R 1 _ A OP 1 R _ R OP R 3 _ B OP 3 V out 1 " Figure 6-5. Active R-realization of high-q biquad filter. Analysis of the circuit in Figure 6-5 yields the s-domain transfer function of this high-q biquad implementation: H ideal highq " s 1 A ( s) = - s A B ' R s 1 R R R s 1 R R , (6-5)

29 6 Errors due to time-discrete filter implementation 5 Replacing the resistor values R1, R, R3 by their equivalent capacitor values, we obtain the equation H conthighq " ' 1 1 s s 1 A ( s) T T = ABs s T T. (6-6) Analogously, we exchange all resistor symbols in the above circuit diagram by their s/c equivalents. Applying the aforementioned switch sharing technique, we get the actual s/c circuit implementation of the high-q biquad shown in Figure 6-6. Φ 1 Φ 1 ' 4 A V in Φ Φ 1 1 Φ Φ 1 _ Φ 1 3 Φ Φ Φ 1 _ B V out 1 " Figure 6-6. Implementation of s/c circuit for high-q biquad using switch sharing. Now, we again apply the time discrete analysis in the z-domain by transforming the s/c circuit diagram into a signal flow chart. The different circuit components are substituted by their proper z-domain equations, which yields the diagram shown in Figure 6-7. ' 1 ( 1 z ) ( 1 z ) V in z A z z B V out " 1 ( 1 z ) Figure 6-7. Signal flow chart of s/c high-q biquad circuit.

30 6 Errors due to time-discrete filter implementation 6 The z-domain transfer function of the high-q biquad is H " ' " " ' z ( - ) z - 1 A A 1 A 1 3 ( z ) = - / z ( - ) z - s c highq A B A B A B 3 4. (6-7) A valuable reference for this section is [Gregorian and Temes 1986], where the above transfer functions are confirmed. 6. Approximation methods for z- to s-domain mapping The capacitor size selection rules implemented for filter design in the EasyAnalog TM software are based on continuous s/c circuit analysis. However, as is explained before, this analysis does not yield very accurate solutions. In order to obtain a s/c filter circuit which is as close as possible to the desired theoretical transfer function, new capacitor size selection rules based on z-domain analysis should be derived. To do so, the z-domain equations of the s/c biquad circuits in Figure 6- and Figure 6-6 have to be transformed into s-domain representations and then comparison with the ideal filters may be used to develop capacitor size selection rules. It is worth mentioning that the capacitor sizes cannot be completely determined by such comparison, and thus additional assumptions will have to be made. A very important step influencing the accuracy of the results is the transition of the filter transfer function from the z-domain into the s-domain. For the highest possible accuracy, this transform is accomplished by setting z = e st [Kammeyer and Kroschel 1996]. If we expand the exponential function into a Taylor series [Bronstein and Semendjajew 3 n st ( st ) ( st ) ( st ) 1991], z = , it is obvious that replacing all the z in a transfer 1!! 3! n! function yields to polynomials of infinite order in the numerator as well as in the denominator. Now if we want to keep the error between the desired theoretical biquad transfer function and the implemented transfer function as small as possible, the difference between these two has to be minimized

31 6 Errors due to time-discrete filter implementation 7 (and, to further improve the filter performance, weighting of the variable s with an appropriate weight function could be performed). Unfortunately, analytical minimization of the error leads to a highly nonlinear system of equations, such that this approach is not practical. Therefore a compromise is needed, which means that precision is traded for an ease of solution Forward Euler transform The easiest way to obtain an approximation function for the transition from a time-discrete to a time continuous transfer function is to compare continuous integration with a numerical approach (in steps). Y( s) The transfer function of an ideal integrator is represented in the s-domain by G( s) = = 1. Numerical X ( s) s integration algorithms can be expressed by difference equations, the so called Forward Euler integration method is recursively written as y( nt ) = y( nt - T ) T x( nt - T ). Simple transformation into the z domain yields Y ( z ) = z Y ( z ) T z X ( z ), and by rearranging this expression the Forward Euler transfer - Y ( z) T z function can be derived, and we get G( z) = = X ( z) 1 - z 1-1. omparison of the two integrators yields the expression z = 1 st, which in general can be used to transform a z-domain transfer function into a s- domain transfer function by substitution. It has to be mentioned that Forward Euler is only conditionally stable, i.e. stability is guaranteed only for sufficiently small T. The two other methods are considered unconditionally stable. The Forward Euler approximation is used in most of the available literature about switched capacitors for the transition from the z- to the s-domain. Theoretical capacitor size selection rules for this approximation exist [Palusinski et al. 1997a], but the practical filter performance using the rules has not yet been evaluated.

32 6 Errors due to time-discrete filter implementation Backward Euler transform Similar to the Forward Euler method, the Backward Euler method can be expressed in difference equation form as y( nt ) = y( nt - T ) T x( nt ). Transforming this into the z-domain and rearranging the terms, the Y ( z) T transfer function G( z) = = X ( z) z 1 is obtained, leading to the approximation formula z - 1 = 1 - st. The error caused by the Backward Euler transform has exactly the same magnitude as the error of Forward Euler, the only difference lies in the inverted phase sign and absolute stability Bilinear transform A more sophisticated approximation method is the bilinear transform, also known as trapezoidal rule with the difference equation x( nt ) x( nt - T ) y( nt ) = y( nt - T ) T. (6-8) Applying the z-domain transform to this equation we get Y z z Y z T X z z -1 - ( ) ( ) ( ) X ( z 1 ) =. The transfer -1 Y ( z) T 1 z function then can be written as G( z) = = -, so again comparison with the ideal integrator 1 X ( z) 1- z leads to st z - = - 1. (6-9) st The impact of these three different approximation rules on the resulting filter is shown in Figure 6-8, which compares the plots of the magnitude of the frequency response H, and the relative errors defined as H - H approx ideal e rel = H ideal. (6-1)

33 6 Errors due to time-discrete filter implementation 9 Title: bilfe.eps reator: MATLAB, The Mathworks, Inc reationdate: 3/3/98 13:45:3 Figure 6-8. Effects on transfer function using different mapping approximations Applying one of the mentioned first order approximations to a time discrete filter transfer function, it is obvious that the filter order is not changed by the transition into a continuous function as it would be the case for higher order approximation functions. This makes the derivation of new capacitor size selection rules straightforward [Birk 1998]. 6.3 alculation of new capacitor size selection rules According to the equations (6-4) and (6-7), which define the transfer functions for the two described s/c circuits for low-q and high-q filter implementations, the transfer function of the s/c biquad implementation in the z-domain can be written in general as a z a z a H s / c ( z ) = - b z b z b 1 1. (6-11)

34 6 Errors due to time-discrete filter implementation 3 Substituting the bilinear approximation formula for z- to s-domain mapping, equation (6-9), into equation (6-11), the general s-domain equivalent for biquad transfer functions is obtained: ( a - a1 a ) s T 4 ( a - a ) st 4 ( a a1 a ) H s/ c ( s) = - ( b - b b ) s T 4 ( b - b ) st 4 ( b b b ) 1 1. (6-1) Subsequent derivations are split into two parts according to the low-q and high-q implementations of biquads Low-Q filter implementations For the low-q circuit implementation, the parameters a, a 1, a and b, b 1, b in equation (6-11) are defined by the s/c low-q transfer function (6-4). omparison between these two equation yields the numerator and denominator coefficients as functions of capacitor values: a = " 1 A a = - ' - " A 1 ' " a = ( 1 1 ) A b = b = - - b = ( ) A B A A A B B 4 A Inserting these coefficients into the general s-domain representation of the s/c circuit function, H s/c (s), which is stated in equation (6-1), the transfer function in the s-domain for the s/c low-q biquad circuit with bilinear approximation can be written in the form: H s / clowq ' " ' ( 1 A 4 1 A - 13 ) s T 4 1A st 4 13 ( s) = - ( 4 - ) s T 4 st 4 4 A A B 3 4 A 3. (6-13) omparison of equation (6-13) with the desired biquad filter transfer function, K s K s K H ( s ) = - biquad w s Q s w 1 (6-1) yields the necessary values for the parameters of low-q filters dependent as functions of the capacitor values. K K T ' " 1 A 4 1 A = 4-4 A A B 3 4 = A A B 3 ' 4 (6-15) 1 A (6-14) K1T = 4-4 A A B 3 3 (6-16) w T = 4-4 A A B 3 (6-17) Q = ( 4 - ) 3 4 A A B 3 4 A. (6-18)

35 6 Errors due to time-discrete filter implementation High-Q filter implementations For high-q biquad filters, we can proceed analogously to the low-q case. The coefficients in equation (6-11) are obtained from equation (6-7) and result in " ' a = - 1 A 1 3 ' " a 1 = A a = " 1 A b = - 34 b 1 = b =. A B A B A B Substituting the values a, a 1, a, b, b 1, and b in equation (6-1), we obtain the s-domain transfer function H s/ chighq " ' ' ( 4 1 A ) s T 4 13 st 4 13 ( s) = - ( ) s T 4 st 4 A B , (6-19) and comparison with the theoretical biquad transfer function in equation (6-1) yields the coefficients K K T " ' 4 A = A B = A B ' 4 13 (6-) K T = A B (6-) w T = A B (6-1) (6-3) Q = ( ) 3 A B (6-4) Additional basic assumptions on which new capacitor size selection rules are based stem from the developed capacitor error model. The relative quantization error decreases with increasing capacitor size, the error due to variations of the tracking error (i.e. the error in the capacitor ratio) caused by manufacturing imperfections exhibits analogous behavior. onsequently for the capacitors A and B, the largest possible values are chosen. To specify new capacitor size selection rules we rearrange the above equations for the filter coefficients depending on the capacitor sizes so that we get the capacitor sizes as functions of the coefficients. These rearrangements cannot be performed analytically for the general case due to the nonlinear system of equations to solve, we have to do that separately for each filter implementation (low-q and high-q circuit) between low-pass filters, high-pass filters, band-pass filters, and band-stop (notch) filters. Thanks

36 6 Errors due to time-discrete filter implementation 3 to this distinction we can take advantage of the fact that for each realization different capacitors are set to zero, which simplifies the equations and allows for an analytical solution of the system. onsidering all possible filter realizations with the two biquad circuits, there are eight sets of new capacitor size selection rules to derive. This derivation is presented in the following chapters. 6.4 Low-pass filter realizations To obtain a general low-pass filter response of second order, we are required to realize a transfer function of the form G H ( s ) = - w low pass w s Q s w, (6-5) for both, low-q and high-q cases. From the general biquad filter transfer function, equation (6-1), it becomes evident that to realize equation (6-5), we have to set the numerator parameters K 1 and K to zero Low-pass, low-q filter Unfortunately, from equation (6-13) in the low-q case we see that we cannot exactly realize the low-pass filter function in equation (6-5). Therefore, we go back to equation (6-3), which was obtained by performing s-domain analysis. Obviously, in order to realize the above ideal function we just have to set ' " 1 = and 1 =. Doing so, we conclude that also the z-domain equation (6-13) yields an approximation close to the ideal transfer function. In our case of the low-q filter we can rearrange the equation (6-17) for w T and (6-18) for Q. These two equations are independent of the capacitors 1, 1 ' and 1", wherever A and B are known. An elegant approach to isolate some of the capacitors is to first compute the product of the coefficients, =, (6-6) 3 w T Q 4 A and then the ratio of the same coefficients,

37 6 Errors due to time-discrete filter implementation 33 w T 4 4 = Q 4 -w T Q 4 B 4. (6-7) From the latter expression, equation (6-7), the capacitor size selection rule for 4 can be derived: 4 = w 4w T B T Q 4 Q - w T. (6-8) Due to the fact that the capacitors and 3 are both of the same order of magnitude, we further assume that = 3, and so an equation for these two capacitor values can be set up using the equations (6-6) and (6-8). For simplicity, this common capacitor value of and 3 is called,3 : =, 3 w T Q A B w T Q 4 Q - w T. (6-9) As in the s-domain equation obtained by z-domain analysis for the low-pass low-q filter, equation (6-13), the second order term in the numerator does not disappear completely (as the first order term does). Therefore, we have to treat it as an error term. However, due to the definition of the pass-band gain this additional term will disappear. For the D gain we obtain the exact expression by setting G = Hs / c lowq ( s = ) = ' " 1, 1 = 1 (6-3) in equation (6-13), so rearranging yields the capacitor formula for the last unknown depending on the pass-band gain G, = G. (6-31) Low-pass, high-q filter The high-q transfer function (6-19), reveals that again we cannot exactly realize the low-pass filter function in equation (6-5). Therefore, going back to the equation obtained by performing s-domain ' " analysis on the continuous high-q filter circuit, equation (6-5), we are required to set 1 = and 1 = as in the low-q case. As before, the factor K in the general biquad transfer function (6-1) does not disappear but becomes very small compared to K, so the error introduced by it is neglected in the further

38 6 Errors due to time-discrete filter implementation 34 considerations. For the calculation of the gain expression this parasitic term in the numerator of the s/c transfer function has no impact. If we use the same approach as above to get new capacitor size selection rules for the high-q case and simplify the expressions, we obtain the new equations w T Q = (6-3) 4 and w T 4 3 = Q 4 w T Q - - w T Q A B 3 3. (6-33) Solving this system of the two equations (6-3) and (6-33) for 4 yields the formula 4 = A B w T Q w T Q 4 Q, (6-34) and with = 3 =,3, we can derive = w, 3 T Q A B w T Q w T 4 Q. (6-35) Analogous to the low-q filter implementation, the pass-band gain is G = Hs / c highq ( s = ) = ' " 1, 1 = 1, (6-36) so we obtain the third and last equation specifying the parameters in the low-pass filter high-q case: = G. (6-37) High-pass filter realizations The general high-pass biquad transfer function is expressed as G s H ( s ) = - high pass. (6-38) w s Q s w