Lecture 27: Latches. Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory
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1 EE241 - Spring 2008 Advanced Digital Integrated Circuits Lecture 27: Latches Timing Announcements Wrapping-up the class: Final presentations May 8, 1-5pm, BWRC Final reports due May 7 Final exam, Monday, May :30pm, 241 Cory Presentations 12 minutes (max 10 slides) + 3 minutes for Q & A 2 1
2 Agenda Wrap up latches Synchronization and timing 3 Pulsed latches 2
3 Pulse-Triggered Latches First stage is a pulse generator generates a pulse (glitch) on a rising edge of the clock Second stage is a latch captures the pulse generated in the first stage Pulse generation results in a negative setup time Frequently exhibit a soft edge property Note: power is always consumed in the pulse generator 5 Pulsed Latch Simple pulsed latch Kozu, ISSCC
4 Intel/HP Itanium 2 Naffziger, ISSCC 02 7 Pulse-Triggered Latches Hybrid Latch Flip-Flop, AMD K-6 Partovi, ISSCC 96 Vdd Q Q D 8 4
5 HLFF Operation 1-0 and 0-1 transitions at the input with 0ps setup time 9 Hybrid Latch Flip-Flop Skew absorption Partovi et al, ISSCC
6 Pulse-Triggered Latches AMD K-7 Courtesy of IEEE Press, New York Pulse-Triggered Latches Semi-Dynamic Flip-Flop (SDFF), Sun UltraSparc III, Klass, VLSI Circuits 98 Vdd Vdd Q Q D Pulse generator is dynamic, cross-coupled latch is added for robustness. Loses soft edge on rising transition Latch has one transistor less in stack - faster than HLFF, but 1-1 glitch exists Small penalty for adding logic 12 6
7 Pulse-Triggered Latches 7474, from early 1960 s S R Q Q D 13 Pulse-Triggered Latches Case 4: Sense-amplifier-based flip-flop, Matsui DEC Alpha 21264, StrongARM 110 First stage is a sense amplifier, precharged to high, when = 0 After rising edge of the clock sense amplifier generates the pulse on S or R The pulse is captured in S-R latch Cross-coupled NAND has different propagation delays of rising and falling edges 14 7
8 Sense Amplifier-Based Flip-Flop Courtesy of IEEE Press, New York Sampling Window Comparison Naffziger, JSSC 11/
9 Local Clock Gating D CKI D I CKIB CKIB Q 0.5 Data-Transition Look-Ahead Pulse Generator XNOR CP CKIB CKI Clock on demand Flip-flop 17 Timing 9
10 Timing Overview Synchronization Approaches Synchronous Systems Timing methodologies Latching elements Clock distribution Clock generation Asynchronous Systems 19 References Chapter 10 in Rabaey Chapter 11 in Bowhill Clocked storage elements, by H. Partovi High-speed CMOS design styles, Bernstein, et al, Kluwer Unger/Tan IEEE Trans. Comp. 10/86 Harris/Horowitz JSSC 11/97 Messerschmitt JSAC 10/90 Stojanović/Oklobdžija JSSC 4/
11 Issues in Timing D. Messerschmitt, Oct 1990 Boolean signal - stream of 0 s and 1 s, generated by saturating circuits and bistable memory elements but finite rise and fall times inter-symbol interference metastability leads to non-deterministic behavior signal transitions are crucial typically defined with respect to slicer/sampler associated clock with uniformly spaced transitions 21 Issues in Timing Clock signal : f + Δf dφ/dt average frequency instantaneous frequency deviation Single Boolean signal equal Isochronous f + Δf = constant Anisochronous f + Δf constant not equal 22 11
12 Issues in Timing Two Boolean Signals together Synchronous f + Δf identical Δφ(t) = 0 (or known) middle Mesochronous Δφ(t) variable (but bounded) Asynchronous not together different Heterochronous Nominally Different freq near Plesiochronous Average Frequency almost the same 23 Some Definitions Signals that can only transition at predetermined times with respect to a signal clock are called {syn,meso,plesio}chronous An asynchronous signal can transition at any arbitrary time
13 Some Definitions (contd) Synchronous Signal: exactly the same frequency as local clock, and fixed phase offset to that clock. Mesochronous Signal: exactly the same frequency as local clock, but unknown phase offset. Plesiochronous Signal: frequency nominally the same as local clock, but slightly different Mesochronous and plesiochronous concepts are very useful for the design of systems with long interconnections, and/or multiple clock domains 25 Mesochronous Interconnect clock synchronous island Data synchronous island Phase Generator Select Clock (local) Phase Detect Data R1 R2 Local Synchronization samples in certainty period of signal 26 13
14 Mesochronous Communication Variable Delay Line Block A R 1 D 1 Interconnect Delay D 2 D3 R 2 D 4 Block B A B Control Timing Recovery 27 Plesiochronous Communication Timing Cloc k C Clock C 2 1 Recovery Originating Module C 3 FIFO Receiving Module Does only marginally deal with fast variations in data delay 28 14
15 Anisochronous Interconnect 29 Synchronous Pipelined Datapath In R1 D Q Logic Block #1 R2 D Q Logic Block #2 R3 D Q Logic Block #3 R4 D Q CLK t pd,reg t pd1 t pd2 t pd
16 Latch Parameters D Q Unger and Tan Trans. on Comp. 10/86 D PW m T H T SU Q T -Q T D-Q Delays can be different for rising and falling data transitions 31 Flip-Flop (Register) Parameters D Q D PW m T H T SU Q T -Q Delays can be different for rising and falling data transitions 32 16
17 Example Clock System Courtesy of IEEE Press, New York Clock Nonidealities Clock skew Spatial variation in temporally equivalent clock edges; deterministic + random, t SK Clock jitter Temporal variations in consecutive edges of the clock signal; modulation + random noise Cycle-to-cycle (short-term) t JS Long term t JL Variation of the pulse width for level sensitive clocking 34 17
18 Clock Skew and Jitter 1 t SK 2 t JS Both skew and jitter affect the effective cycle time Only skew affects the race margin 35 Clock Uncertainties 4 Power Supply Devices 2 3 Interconnect t 6 Capacitive Load 1 Clock Generation 5 Temperature 7 Coupling to Adjacent Lines Sources of clock uncertainty 36 18
19 Clock Constraints in Edge-Triggered Systems Courtesy of IEEE Press, New York Latch timing t D-Q D Q When data arrives to transparent latch Latch is a soft barrier t -Q When data arrives to closed latch Data has to be re-launched 38 19
20 Single-Phase Clock with Latches φ Latch Unger and Tan Trans. on Comp. 10/86 Logic T skl T skl T skt T skt In Chapter 10: T = T + T sk skl skt PW P 39 Preventing Late Arrivals P PW T SU Data must arrive T -Q T LM T SU T SU PW T D-Q TLM T SU 40 20
21 Preventing Late Arrivals Tskl + Tskt + T SU + Tclk QM PW, P max + T TD QM LM Or: P T clk QM + T LM + T SU + T skl + T skt PW P T D + T QM LM 41 Preventing Premature Arrivals PW T H T -Q T Lm Two cases, reduce to one: T Lm T skl + T skt + T H + PW T Qm 42 21
22 Single-Latch Timing Bounds on logic delay: φ Tskl + Tskt + TSU + Tclk QM PW, P max + TLM TD QM Latch T Lm T skl + T skt + T H + PW T Qm Logic Either balance logic delays or make PW short 43 Latch-Based Design L1 latch is transparent L2 latch is transparent when f = 0 when f = 1 f L1 Latch Logic L2 Latch Logic 44 22
23 Latch-Based Timing As long as transitions are within the assertion period of the latch, no impact of position of clock edges 45 Latch Design and Hold Times 46 23
24 Latch-Based Timing Longest path P 2T + T + T D QM LHM Independent of skew Short paths LLM T CLLm T SK + T H T Qm T CLHm T SK + T H T Qm Same as register-based design but holds for both clock edges 47 Latch-Based Timing φ Static logic Skew L1 Latch Logic L2 Latch L1 latch φ = 1 L2 latch Logic Long path φ = 0 Can tolerate skew! Short path 48 24
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