ESE319 Introduction to Microelectronics Common Emitter BJT Amplifier


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1 Common Emitter BJT Amplifier 1
2 Adding a signal source to the single power supply bias amplifier R C R 1 R C V CC V CC V B R E R 2 R E Desired effect addition of bias and signal sources Starting point  single dc source 2
3 Wrong Way to Combine Sources <> 0 0 Source with low output impedance upsets bias. Thevenin equivalent at base: 3
4 Wrong Way  Continued R S V B V th To analyze, 1. Isolate base circuit, 2. Use superposition, 3. Find Thevenin equivalent for the base bias source, V B : V th R th ' V B V B R S The signal source effectively shorts out the bias source! ( 0) The signal source v S is essentially is unaffected by the bias source V B. (Why? What is its Thevenin equivalent?) 4
5 ESE319 Introduction to Microelectronics The Right Way Use a Blocking Capacitor i Cb v Cb +  C b 0 r bg For convenience lets continue to use the base bias Thevenin equiv. 1. Capacitor C b is an OPEN at dc and R S does not affect the bias! 2. C b charges to the dc bias source, V B, to satisfy Kirchoff's voltage law. 3. The dc bias is in series with the signal source, i.e. DESIGN GOAL: for f f min1, set the value of C b so that its ac voltage drop v Cb is negligible at and above the low frequency cutoff at say f min1. v S V B 5
6 Using superposition, for smallsignal let V B 0. ESE319 Introduction to Microelectronics Blocking Capacitor Selection i b i c apply i b evaluate i e <> i b i e i c 0 r bg r bg v bg i b i e i b i b Use the small signal equivalent circuit and superposition to estimate the input resistance of the transistor. v bg i b r i e R E i b r i b 1 R E r bg v bg i b r 1 R E R E 6
7 Capacitor Selection continued The signal source sees the 20 kω bias source resistance in parallel with. So the signal source equivalent circuit is: i Cb r bg 0 R E 400 k Therefore: v Cb +  C b 0 r BG k r bg R E The capacitor voltage drop is: v Cb 1 i j C Cb b Where the capacitor current is: i Cb R S r bg 1 j C b i Cb 1 j C b > v Cb j C b 1 Goal: C b 1 7
8 i Cb v Cb +  ESE319 Introduction to Microelectronics Capacitor Selection  continued C b 1 v Cb or f RB C j C b 1 b 2 C b CONSERVATIVE DESIGN GOAL: Choose C b for negligible voltage drop at v Cb for f f min1, i.e. OR v Cb j C b 1 for f f min1 v Cb 2 f min1c b C b 2 f min1 DESIGN GOAL: Choose C b so that f RB C b 0.1 f min1, i.e. 1 f Cb 0.1 f 2 C b R min1 C b B 2 f min1 8
9 Capacitor Selection  continued C b 2 f min1 C b min 2 f min1 Select the LOWEST frequency of interest. This sets the lower bound on C b. Using f min1 20 Hz frequency for our example circuit: 2 f min sec 1 C b min F ANY capacitor larger than 4 do the job! F will also 9
10 Common Emitter Unity Gain Amplifier Cb 5 uf Cb 5 uf Equivalent circuits How can we achieve reasonable gain with this circuit? Solution: Split R E and use capacitor bypassing.
11 Cb 5 uf 0 ESE319 Introduction to Microelectronics + v RE1  + v ZE2  Bypass for Gain Procedure: 1. Split the emitter resistor in two. Later, we will show that the voltage gain will be close i e Z E2 R E2 1 j C byp to R C /R E1. 2. Bypass R E2 with a capacitor C byp that looks like a near short circuit at some suitable low frequency (f min2 f min1 ). i.e. v ZE2 << v RE1 for f f min2 ) v RE1 i e R E1 & v ZE2 i e Z E2 11
12 Bypass for Gain  continued Rb 20 k Ohm + v RE1  + Rb 20 k Ohm v ZE20 0 Small signal circuit Desired circuit for f f min2 i.e. CONSERVATIVE DESIGN GOAL: Choose C byp s.t. v ZE2 << v RE1 for f f min2 12
13 Rs Rb b c Need to develop a design equation for C byp s.t. DESIGN GOAL: v ZE2 << v RE1 i b e i c i e + v RE1 +  v ZE2 i e 1 i b  0 r e R E1 v RE1 i e R E1 & v ZE2 i e Z E2 where Z E2 v ZE2 V RE1 Z E2i e R E1 i e C byp R E2 R E1 1 2 f min2 R E2 C byp 2 f min2 R E1 R E2 j C byp R E2 1 R E2 / R E1 j C byp R E2 1 1 j 2 f min2 C byp R E2 1 R E2 R E1 1 2 f min2 R E1 13
14 C b 2 f min1 In Lab 2 Choose C b s.t. 1 2 f min1 C b R in r bg f min1 Hz C b f min1 20 C byp 2 f min2 R E1 Choose C byp s.t. C byp f min2 0Hz 1 R E 2 f min2 C byp f min2 R E /2 1 0 R E 14
15 C byp ESE319 Introduction to Microelectronics 2 f min R E1 2 x 20 x 00 F 79.6 F You may choose C byp 0 F Final Design Cb 5 uf 15
16 Gain Calculation in Passband Simple gain calculation: +  vout i b R s r 1 R E1 1 R E1 v out R C i c R C i b 0 Passband model v out R C v 1 R s E1 A v v out R C R E1 4 16
17 Multisim Simulation 20 Hz Gain I khz Gain 17
18 What if R E is Fully Bypassed? A v v out R C R E 0? 18
19 What if R E is Fully Bypassed? Cb 5 uf vout i b R s r 1 R E v out R C i c R C i b 0 R S r I C 1 ma g m I C /V T 0.04 S r / g m 2.5k 0 v out R C R S r R C r. R C / g m g m R C A v v out g m R C
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