02/07/2011. Dr Thomas Anthopoulos. Feature size down to 25 nm True nanoelectronics..!

Transcription

1 Organic Thin-Film Transistors: Operating Principles and Applications OREA ummer chool - Crete 211 r Thomas Anthopoulos epartment of Physics and Centre for Plastic Electronics Imperial College London United Kingdom Traditional Electronics Inorganic emiconductors 1-11 billion TFTs ilicon (i) 2 Metalloid i atoms covalently bonded i-crystal: strong, very brittle and prone to chipping Excellent semiconductor when doped with high carrier mobility (µ 1 cm 2 /Vs) in single crystal form Amorphous-i is the alternative for large-area application but µ 1 cm 2 /Vs Feature size down to 25 nm True nanoelectronics..! 1

2 Plastic Electronics Inorganic emiconductors 1 6 OTFTs ilicon (i) Pentacene 3 Metalloid i atoms covalently bonded i-crystal: strong, very brittle and prone to chipping Excellent semiconductor when doped with high carrier mobility (µ 1 cm 2 /Vs) in single crystal form Amorphous-i is the alternative for large-area application but µ 1 cm 2 /Vs 6 p-orbitals elocalised orbitals Highest-occupied molecular orbital (HOMO) Lowest-unoccupied molecular orbital (LUMO) Plastic Electronics Inorganic emiconductors ilicon (i) 1 6 OTFTs Pentacene 4 Metalloid i atoms covalently bonded i-crystal: strong, very brittle and prone to chipping Excellent semiconductor when doped with high carrier mobility (µ 1 cm 2 /Vs) in single crystal form Amorphous-i is the alternative for large-area application but µ 1 cm 2 /Vs 6 p-orbitals elocalised orbitals Large number of molecules can in principle be synthesised Easy to process using known as well as new deposition processes Electrical performance adequate for low-end applications 2

3 Plastic Electronics Inorganic Organic: A Paradigm hift for Electronics 5 Batch processes Controlled environment Fixed, long production runs High equipment and infrastructure costs ource: PolyIC (C&E News Feb 6) Additive continuous processes Processing in ambient conditions Flexible, short production runs Plastic Electronics Roadmap for PE Applications Forecast for the Market Entry (large volume) 6 3

4 Plastic Electronics 7 Current status ignificant funding: Europe, UA, Asia Materials commercially available for distinct applications (OLE, OPV, OFET) Increasing processing and manufacturing infrastructure Prototypes available (O-TFT, O-RFI, OPV, Flexible isplays) ifferent development status for different applications Common driver for all organic electronic applications - simplified processes 4

5 Plastic Electronics Charge carrier mobility (cm 2 /Vs) OPV Monochrome E-Paper RFI (nonstandard) Colour, LC display RFI tandard ensors Backplanes for OLE displays 1-3 Time to launch 9 Plastic Electronics Carrier mobility requirements i i F i F Organic/Organic-Inorganic hybrid materials i 1 5

6 Targeted Applications Optical isplays Microelectronics ensors ONY Univ. Tokyo IMEC-Holst ONY Poly IC iemens Targeted Applications Optical isplays Microelectronics ensors ONY Univ. Tokyo IMEC-Holst ONY Poly IC iemens Backplanes Unipolar semiconductor High mobility (>5 cm 2 /Vs) High electrical stability Parameter uniformity ICs p & n-type sem. required High mobility (µ e = µ h ) Easy processing High resolution patterning technology requirements 6

7 Optical isplays AM-LC V Address V ata Mobility cm 2 /Vs Colour, high Performance displays Large area (low performance) witch GN LC pixel E-Paper (small rollable displays) Achievable by polymers 28 Time to launch AM-OLE V ata Mobility cm 2 /Vs 1 High efficiency OLE devices Colour, high Performance displays V Address V 1-1 Large area (low performance) T1 T2 - driver 1-2 E-Paper (small rollable displays) C OLE 13 GN Achievable by polymers Time to launch I. McCulloch Optical isplays Currently external driving circuitry is required Polymer Vision i-based ICs isplay IC 14 7

8 Optical isplays Onboard IC Polymer Vision ATA BU CPU Onboard IC POWER P isplay 15 Target: Manufacture active matrix optical displays using OFET based backplane and driving ICs (e.g. shift registers) TFT Technologies for Large Area Electronics ilicon ilicon (a-i, LTP) TFTs is an established technology : i) a-i; µ=.1-1 cm 2 /Vs; low for application in AM-OLE based displays ii) p-i; µ= 5-2 cm 2 /Vs High Processing temperatures Costly to process onto large area substrates Opaque films hence the emissive pixel fill-factor can be very low Brittlehence incompatible with plastic substrates 8

9 TFT Technologies for Large Area Electronics ilicon Organic emiconductors ilicon (a-i, LTP) TFTs is an established technology : i) a-i; µ=.1-1 cm 2 /Vs; low for application in AM-OLE based displays ii) p-i; µ= 5-2 cm 2 /Vs High Processing temperatures Costly to process onto large area substrates Opaque films hence the emissive pixel fill-factor can be very low Brittlehence incompatible with plastic substrates I. Unlimited library of materials II. Flexible chemistry i.e. tailored physical properties III. Low-temperature processing (e.g. <2 o C) IV. Potential for low-cost, large area processing on different substrates V. Mobilities up to 6 cm 2 /Vs have been obtained from thin-film transistors TFT Technologies for Large Area Electronics ilicon Organic emiconductors Oxide emiconductors ilicon (a-i, LTP) TFTs is an established technology : i) a-i; µ=.1-1 cm 2 /Vs; low for application in AM-OLE based displays ii) p-i; µ= 5-2 cm 2 /Vs High Processing temperatures Costly to process onto large area substrates Opaque films hence the emissive pixel fill-factor can be very low Brittlehence incompatible with plastic substrates I. Unlimited library of materials II. Flexible chemistry i.e. tailored physical properties III. Low-temperature processing (e.g. <2 o C) IV. Potential for low-cost, large area processing on different substrates V. Mobilities up to 6 cm 2 /Vs have been obtained from thin-film transistors I. Large library of materials II. Relatively lowtemperature processing (e.g. RT- 4 o C) III. Low-cost, large area processing using a range of deposition techniques IV. High mobilities (>1 cm 2 /Vs) have been obtained in TFTs V. Highly transparent in the visible range of the electromagnetic spectrum 9

10 Outline of the talk The history of thin-film transistor Thin-film transistors -The metal-oxide-semiconductor capacitor -Qualitative description of thin-film transistor operation -Organic thin-film transistors; materials and device architecture Applications of organic thin-film transistors -Optical displays - Microelectronics The history of thin-film transistors Original idea by Julius Lilienfeld between Patent of Lilienfeld in

11 History of thin-film transistors William hockley sought to make TFTs in late 194s but he was unsuccessful. His original patent application was dismissed due to prior patent of J. Lilienfeld BJT evice finally realised by John M. Atalla at Bell Labs in 196 using hockley's theory Fairchild FI 1 p-channel MO switching transistor The metal-oxide-semiconductor (MO) capacitor 11

12 Operating principles (qualitative) At the heart of any TFT is the MO capacitor V G ielectric Gate (metal) ielectric p-type semicond. Operating principles (qualitative) At the heart of any TFT is the MO capacitor Accumulation (p-type) ielectric V G Gate (metal) ielectric p-type semicond. 12

13 Operating principles (qualitative) At the heart of any TFT is the MO capacitor epletion (p-type) V G ielectric epletion region Operating principles (qualitative) V G Top electrode emiconductor ielectric Gate From MO theory it is know that majority carriers can accumulate at, or deplete from, the dielectric/semiconductor interface This implies that the conductivity of the semiconductor at the very interface can be modulated by the gate bias (V G ) 13

14 Operating principles (qualitative) An TFT can be realised by replacing the top electrode with two Ohmic (for n-type semiconductor) contacts namely the source () and drain () Top electrode emiconductor ielectric Gate V G Operating principles (qualitative) An TFT can be realised by replacing the top electrode with two Ohmic (for n-type semiconductor) contacts namely the source () and drain () Top electrode emiconductor ielectric Gate emiconductor ielectric Gate V G 14

15 Operating principles (qualitative) L is the channel length and W the channel width of the transistor. L W = area of the transistor channel Top electrode emiconductor Channel length (L) ielectric Gate L V G W Operating principles (qualitative) The source terminal () is typically biased at the ground potential ( V) while the source () and gate (G) terminals at different potential(s) depending on the type of the semiconductor (i.e. p/n-type) and the desired operating regime n-type sem. io 2 Gate V V G 15

16 Operating principles (qualitative) By applying a positive bias at the gate, electrons will start accumulating at the dielectric/n-type sem. interface (ideal transistor) V G = V > I ielectric V V G Operating principles (qualitative) By applying a positive bias at the gate, electrons will start accumulating at the dielectric/n-type sem. interface (ideal transistor) The channel current is defined as the current flowing between the and, hence I =I On the other hand, I G = A for an ideal TFT since the dielectric is a perfect insulator and forbids any charge flow between the G and the / terminals I V G = V > I ielectric V G I G = I = I V 16

17 Operating principles (qualitative) By applying a positive bias at the gate, electrons will start accumulating at the dielectric/n-type sem. interface (ideal transistor) Under these biasing conditions the TFT channel is highly conductive i.e. a short circuit: I (=I ) I V G = V > I ielectric V G I G = I = I V Operating principles (qualitative) Under these biasing conditions the TFT channel is very insulating i.e. an open circuit: I = I V G < depleted region ielectric V G I G = I = I V 17

18 Biasing regimes for p/n-type FETs (Qualitative) Transfer characteristics V 2 (> V 1 ) V 1 log (I ) V 2 (> V 1 ) V 1 V G Biasing regimes for p/n-type FETs (Qualitative) Output characteristics I V G V V G 18

19 Operating principles (n-type semiconductor) Mode of operation depends on V G, V, and V V G = V G V V G = V G V V = V V = V G V G V V G V (or V ) V G V G V ource and drain are symmetric terminals By convention, source is the terminal at lower voltage (NMO) Hence V Three regions of operation 1) Cut-off 2) Linear 3) aturation Cut off regime (n-channel FET) when V G V, there is no channel current (ideal FET) I = (because the semiconductor cannot transport h + ) n-type +++ I io 2 G V G V V GN V 19

20 Linear regime (n-channel FET) For V G > V n-channel forms Current flows between and (i.e. e - from ) I increases with increasing V (as long V << V G ) like in a resistor I n-type io 2 G V G V GN V Linear regime (n-channel FET) For V G > V n-channel forms Current flows between and (i.e. e - from ) I increases with increasing V (as long V << V G ) like in a resistor I n-type io 2 G V G V GN V 2

21 Linear regime (n-channel FET) For V G > V n-channel forms Current flows between and (i.e. e - from ) I increases with increasing V (as long V << V G ) like in a resistor I n-type io 2 G V G (increasing) V G V GN V aturation regime (n-channel FET) For V >> V G > V the n-channel pinches off I is independent of V The channel (i.e. I ) current saturates n-type io 2 I saturation G V G V linear GN V 21

22 Operating regimes water analogy of a TFT ource: rain: Gate: water reservoir water reservoir gate between source and drain V G V ource Gate rain Operating regimes water analogy of a TFT ource: rain: Gate: water reservoir water reservoir gate between source and drain V G I = water flow from V ource Gate rain 22

23 Operating regimes water analogy of a TFT Cut-off regime: gate closed; no water can flow regardless of relative height of / reservoirs (I = ) I = no water flow V = V G ource Gate rain Operating regimes water analogy of a TFT Cut-off regime: gate closed; no water can flow regardless of relative height of / reservoirs (I = ) I = no water flow V = V G V ource Gate rain 23

24 Operating regimes water analogy of a TFT Cut-off regime: gate closed; no water can flow regardless of relative height of / reservoirs (I = ) I = no water flow V = V G ource Gate rain Operating regimes water analogy of a TFT Linear regime: gate open but small difference in height between and ; water flows I = water flows I V G V ource Gate rain 24

25 Operating regimes water analogy of a TFT aturation regime: gate open but small difference in height between and ; water flows I = water flows I saturation linear V ource Gate rain Gradual channel approximation WCG I = µ ( V L V ) V 2 V 2 By approximating V << V G, results in a simplified formula for the linear regime: WC L µ G T (( V V V ) G I = G T ) n-type io 2 I µ = V ( linear ) G L WC V G G 25

26 Gradual channel approximation In the saturation regime, V = V G V T can be substituted into the gradual channel approximation for the linear regime: I WC L G = µ ( V V ) 2 G T µ I 2 ( saturation) = 2 VG L WC G n-type (I ) 1/2 io 2 G V T > V Gradual channel approximation In the saturation regime, V = V G V T can be substituted into the gradual channel approximation for the linear regime: I WC L G = µ ( V V ) 2 G T µ I 2 ( saturation) = 2 VG L WC G n-type (I ) 1/2 io 2 G V T = V 26

27 The gate dielectric The geometrical capacitance (C G ) of the channel depends on the permittivity value of the dielectric (ε OX =ε ε ielectric ) and its thickness (t OX ) (ε is the permittivity of free space = F/m) C G = Aε t OX OX The gate dielectric The geometrical capacitance (C G ) of the channel depends on the permittivity value of the dielectric (ε OX =ε ε ielectric ) and its thickness (t OX ) (ε is the permittivity of free space = F/m) C G = Aε t OX OX Hence, C G can be increased by either increasing the dielectric permittivity ( ε ielectric) (or ε r ) and/or by reducing its thickness (t OX ) By increasing the geometrical capacitance of the channel the operating voltage of the transistor can be decreased dramatically Q Channel = C G ( VG VT ) 27

28 Organic Thin-Film Transistors Carrier Injection and Transport EA LUMO E F IP ielectric Φ B(h) Gate p-channel M 1 HOMO 28

29 Carrier Injection and Transport EA IP LUMO M 1 E F Φ B(h) Gate p-channel ielectric HOMO EA n-channel E F Φ B(e) IP LUMO HOMO ielectric Gate M 1 Carrier Injection and Transport EA LUMO p/n-channel Φ B(e) E F Au IP ΦB(h) HOMO M ielectric Gate

30 Carrier Injection and Transport EA LUMO p/n-channel Φ B(e) E F Au IP ΦB(h) HOMO M ielectric Gate EA LUMO p/n-channel E F IP Φ B(e) ielectric Φ B(h) Gate M HOMO M OFET Architectures emiconductor emiconductor ielectric Gate Bottom-Gate, Bottom-Contact ielectric Gate Bottom-Gate, Top-Contact Gate ielectric Gate ielectric emiconductor emiconductor ubstrate ubstrate 3

31 OFET Architectures emiconductor emiconductor ielectric Gate Bottom-Gate, Bottom-Contact ielectric Gate Bottom-Gate, Top-Contact Gate ielectric emiconductor ubstrate Gate-2 ielectric-2 emiconductor ielectric-1 Gate-1 Applications 31

32 2/7/211 How do we get here? Flat Panel isplays why so important..? 32

33 OLE Based isplays Emissive front end FETs can be larger in top emitting device, but multiple FETs/pixel (smaller Mobility cm 2 /Vs 1 Colour, high performance displays ONY W/pixel than EP ) Current driven device - demands transistor performance uniformity and stability E-Paper (small rollable displays) Large area (low performance) Achievable by solution processed materials Time to launch Polymer Vision Compatible with OFET performance Reflective effect OFETs can be larger (i.e. lower µ requirements) Low refresh rates lower pixel charging speeds lower µ requirements Bistable - lower duty cycle, longer lifetimes. Higher resolution and size require larger number of rows/columns higher I ON and faster charging speeds - higher µ. OFET Applications in Optical isplays AM-LC V ata Mobility cm 2 /Vs 1 Colour, high Performance displays V Address 1-1 Large area (low performance) witch GN LC pixel E-Paper (small rollable displays) Achievable by polymers 28 Time to launch AM-OLE V ata Mobility cm 2 /Vs 1 High efficiency OLE devices Colour, high Performance displays V Address V 1-1 Large area (low performance) T1 T2 - driver 1-2 E-Paper (small rollable displays) C OLE GN Achievable by polymers Time to launch 33

34 Active-Matrix Liquid Crystal isplays (LCs) Active-Matrix Liquid Crystal isplays (LCs) 34

35 OFET Applications in Optical isplays AM-LC V ata Mobility cm 2 /Vs 1 Colour, high Performance displays V Address 1-1 Large area (low performance) witch GN LC pixel E-Paper (small rollable displays) Achievable by polymers 28 Time to launch AM-OLE V ata Mobility cm 2 /Vs 1 High efficiency OLE devices Colour, high Performance displays V Address V 1-1 Large area (low performance) T1 T2 - driver 1-2 E-Paper (small rollable displays) C OLE GN Achievable by polymers Time to launch Active-Matrix OLE based isplays (AM-OLEs) 35

36 OTFTs in microelectronics OTFTs emiconductor emiconductor ielectric Gate Bottom-Gate, Bottom-Contact ielectric Gate Bottom-Gate, Top-Contact Gate ielectric Gate ielectric emiconductor emiconductor ubstrate ubstrate 36

37 The Voltage Inverter IN OUT IN 1 OUT 1 Voltage inverter The Voltage Inverter IN OUT Gain = V OUT / V IN IN 1 OUT 1 V OUT (V) Voltage inverter -2-2 V IN (V) 37

38 The Voltage Inverter IN OUT Gain = V OUT / V IN IN 1 OUT 1 V OUT (V) Voltage inverter -2-2 V IN (V) The Voltage Inverter IN OUT Noise Margin Gain = V OUT / V IN IN 1 OUT 1 V OUT (V) NM max NM = V IN /2 Noise Margin Voltage inverter -2-2 V IN (V) 38

39 The Voltage Inverter IN OUT IN 1 OUT V OUT (V) Unipolar inverter circuit based on pentacene 1 Voltage inverter V IN (V) The Voltage Inverter High NM Noise Margin Gain = V OUT / V IN V OUT (V) IN OUT Noise Margin -2-2 V IN (V) 39

40 The Voltage Inverter High NM Noise Margin Gain = V OUT / V IN HIGH V OUT (V) IN OUT Noise Margin LOW -2-2 V IN (V) The Voltage Inverter High NM Noise Margin Gain = V OUT / V IN HIGH V OUT (V) IN OUT Noise Margin LOW -2-2 V IN (V) Circuits with high NM can tolerate input noise. 4

41 The Voltage Inverter Low NM HIGH V OUT (V) IN OUT LOW V IN (V) The Voltage Inverter Low NM HIGH V OUT (V) IN OUT LOW V IN (V) 41

42 The Voltage Inverter Low NM HIGH V OUT (V) IN OUT LOW V IN (V) Circuits with small NM are highly sensitive to input/signal noise ifferent Logic Families - V V V OFET 1 p-type Ambipolar V OUT V IN V OUT V IN V OUT -V IN OFET 2 n-type Ambipolar Unipolar (V G = V) Complementary Complementary-likelike 42

43 Unipolar Logic V G = V, Logic iode-load Logic V V IN T OUT IN T OUT T L T L GN GN Choice of logic depends on the operating characteristics of the individual OFETs Unipolar Logic V OFET 1 V OUT V IN OFET 2 Unipolar (V G = V) 43

44 Unipolar Logic V V OFET 1 R1 V OUT V IN = LOW V IN OFET 2 R2 = GN V OUT = V Unipolar (V G = V) V OUT = High Unipolar Logic V V V OFET 1 R1 R1 = V OUT V IN = LOW V IN = HIGH V IN OFET 2 R2 = GN V OUT = V GN R2 V OUT = GN Unipolar (V G = V) V OUT = High V OUT = Low 44

45 Unipolar Logic V OFET 1 OFET 1 V OUT V IN OFET 2 OFET 2 Unipolar (V G = V) Unipolar organic inverter Unipolar Logic V V IN OFET 1 V OUT OFET 2 Unipolar (V G = V) imple fabrication - ingle semiconductor - ingle contact material Complex design -Extra vertical interconnects Poor noise margins -Low yield (i.e. high cost) High power consumption 45

46 Unipolar Logic V -1. V IN OFET 1 V OUT OFET 2 V OUT (V) T1: L=1, W=1 T2: L=1, W= tatic power (a.u.) Unipolar (V G = V) V IN (V). Complementary Logic IN V T PU T P OUT Complementary logic circuits: Complementary logic is the dominant logic used in ibased electronics. This is due to its high performance characteristics i.e.: GN High gain Low static-power dissipation Excellent noise margin 46

47 Complementary Logic V p-type V IN V OUT n-type Complementary Complementary Logic V V p-type R1 V IN V OUT V IN = LOW n-type R2 = GN V OUT = V Complementary V OUT = High 47

48 Complementary Logic V V V p-type R1 R1 = V IN V OUT V IN = LOW V IN = HIGH n-type R2 = GN V OUT = V GN R2 V OUT = GN Complementary V OUT = High V OUT = Low Complementary Logic V IN V p-type n-type V OUT imple design - Minimum interconnects Low power consumption High noise margins - i.e. high yield Complex fabrication - Two semiconductors - Two electrode materials Complementary Complementary organic circuits 48

49 Complementary Logic V V IN p-type n-type V OUT V OUT (V) T1: L=1, W=2 T2: L=1, W= tatic power (a.u.) Complementary V IN (V). Unipolar vs. Complementary Logic V V OFET 1 p-type V OUT V IN V OUT V IN OFET 2 n-type Unipolar (V G = V) Complementary 5 V OUT (V) V OUT (V) V IN (V) Unipolar V IN (V) Complementary 49

50 Ring Oscillator cope 1st n GN A ring oscillator is a concatenation of an odd number of inverters, as shown in the figure above. uch circuits can provide valuable information related to: evice/material processing Circuit layout Material properties (mobility, parameter uniformity, stability etc.) Ring Oscillator cope 1st n GN L 5

51 Ring Oscillator cope 1st n GN L H Ring Oscillator Output(n) Input(1 st ) cope 1st n GN L H L H When output(n) input(1st) the circuit oscillates 51

52 Ring Oscillator state-of of-the-art Output(n) J. Mater. Res., 19, 1963 (24) f OC = (2 n τ INV ) -1 Unipolar polymer-based ring-oscillators Ring Oscillator state-of of-the-art V Blend OFET Output Input Blend OFET Ground Input Output 7-stage ring oscillator (p-type) f OC (khz) Output signal (a.u.) Time (µs) F TE TE V = -12 V f OC (khz) * * n F N R V = -6 V -75 V -1 V -12 V Channel length (µm ) dif-at:ptaa V (Volt) High performance 7-stages ring-oscillators (L = 1.5 µm) based on BG-BC OFETs Oscillation frequency ~ 1 khz tage delay ~ 712 ns J. mith et al. Appl. Phys. Lett. 93, (28) 52

53 Ring Oscillator state-of of-the-art J. Appl. Phys., 89, 5125 (21) mall-molecule molecule complementary ring-oscillators Ring Oscillator state-of of-the-art Complexity Unipolar logic: khz [1] High power dissipation imple technology Low yield Complementary logic: khz [2] Low power dissipation Complicated technology High yield [1] Nature Materials 3, 16 (24) [2] Nature 43, 521 (2) peed Unipolar circuits: Poly-3alkylthiophene based ringoscillators [3] : 22 ms Complementary circuits: H-a5T and F 16 CuPc based ringoscillators [4] : 1 1 ms [3] J. Mater. Res., 19, 1963 (24) [4] J. Appl. Phys., 89, 5125 (21) 53

54 Thank you 54