EE 330 Lecture 6. Improved Switch-Level Model Propagation Delay Stick Diagrams Technology Files - Design Rules

Transcription

1 EE 330 Lecture 6 Improved witch-level Model Propagation elay tick iagrams Technology Files - esign Rules

2 Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain rain G Gate n-channel MOFET ource G = 0 G = 1 Conceptual view of basic switch-level model

3 Review from Last Time MO Transistor Qualitative iscussion of n-channel Operation ource Gate rain Bulk Insulator rain For V G small n-channel MOFET Gate Bulk ource ource Gate rain Bulk Insulator ource Gate rain Bulk Insulator Resistor For V G large n-channel MOFET

4 MO Transistor Qualitative iscussion of n-channel Operation Bulk ource Gate rain Insulator rain For V G small n-channel MOFET ource Gate rain Gate Bulk Bulk Insulator ource For V G large n-channel MOFET Thin film resistor is electrically created Capacitance from gate to channel region is distributed Lumped capacitance much easier to work with

5 Improved witch-level Model rain Gate ource G C G R W V G witch closed for V G = 1 witch-level model including gate capacitance and channel resistance till neglect bulk connection and connect the gate capacitance to the source

6 Improved witch-level Model rain Gate G = 1 G = 0 ource n-channel witch-level model G C G R W V G witch closed for V G = large lt: switch closed for G = 1 witch-level model including gate capacitance and channel resistance

7 Improved witch-level Model rain Gate G = 0 G =1 ource p-channel witch-level model G C G R W V G witch closed for V G large and neg lt: If near V, closed for G=0 witch-level model including gate capacitance and channel resistance

8 Improved witch-level Model rain Gate G ource R W C G V G witch closed for G =1 witch-level model including gate capacitance and channel resistance C G and R W dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C G 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C G and R W

9 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf.01uf rea allocations shown to relative scale:

10 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf 10fF 1fF.01uf 1pf rea allocations shown to relative scale: Not enough information at this point to determine whether this very small capacitance can be neglected Will answer this important question later

11 rain Model ummary (for n-channel) Gate 1, witch-level model ource G = 1 G = 0 2, Improved switch-level model G C G R W V G witch closed for V G = large witch open for V G = small Other models will be developed later

12 Example What are t HL and t LH? 1pf ssume V =5V With basic switch level model? With improved switch level model?

13 Example Inverter with basic switch-level model G p-channel Model G V n-channel Model

14 Example What are t HL and t LH? G p-channel Model 1pf G V n-channel Model 1pF With basic switch level model t HL =t LH =0

15 Example (cont) With simple switch-level model t HL =t LH =0 1pf Inverter With improved model? 1pf

16 Example (cont) Inverter with improved model Inverter with Improved Model G p-channel Model R Wp C Gp Inverter G V n-channel Model R Wn C Gn

17 Example (cont) With improved model t HL =? G p-channel Model R Wp 1pf G C Gp V n-channel Model 1pF R Wn C Gn To initiate a HL output transisition, assume has been in the high state for a long time and lower switch closes at time t=0 5V C Gp V C Gn R Wn =2K 5V 1pf C L 5V is the initial condition on C L

18 Example (cont) With improved model R t HL =? Wn =2K 5V C Gp C Gn 5V 1pf C L V Recognize as a first-order RC network Recall: tep response of any first-order network with LHP pole can be written as y(t) F τ I Fe where F is the final value, I is the initial value and τ is the time constant of the circuit t For the circuit above, F=0, I=5 and R C Wn L

19 Example (cont) With improved model =V OUT t HL =? 5V C Gp V C Gn R Wn =2K 5V 1pf C L OUT t V (t) F I F e τ t V (t) 5e τ OUT I R C Wn L F t HL =? t HL =? t how is t HL defined?

20 Example (cont) V OUT R t HL =? Wn =2K 5V C Gp C Gn 5V 1pf C L V F I I/e I=5V, F=0V R C Wn L efine t τ I V (t) F F e OUT t HL t HL to be the time taken for output to drop to I/e I e F I F e t HL as defined has proved useful at analytically predicting response time of circuits t HL τ t

21 Example (cont) With improved model F I I/e I=5V, F=0V R C Wn L t I e I e HL F Ie t HL t 1 HL e τ e t τ τ I Fe t HL t HL t HL =R C Wn L

22 Example (cont) With improved model tlh =? G p-channel Model R Wp C L 1pf G C Gp V n-channel Model 1pF R Wn C Gn ssume output in low state for a long time and upper switch closes at time t=0 V OUT 5V C Gp C Gn V V =5V R Wp =6K 0V 1pf C L 0V is the initial condition on C L

23 Example (cont) With improved model t LH =? V OUT 5V C Gp C Gn R Wp =6K 0V 1pf V V =5V C L y(t) F τ I Fe t For this circuit, F=5, I=0 and R C Wp L

24 Example (cont) With improved model V OUT t LH =? 5V C Gp C Gn R Wp =6K 0V 1pf t τ I V (t) F F e OUT V V =5V C L R C Wp L t V (t) 5 1- e τ OUT F I t LH =? t LH =? t how is t LH defined?

25 Example (cont) V OUT With improved model F F(1-1/e) I t LH =? efine t LH as shown on figure 5V C Gp C Gn V V =5V I=0V, F=5V R C Wp L R Wp =6K 0V 1pf C L t t LH t LH as defined has proven useful for analytically predicting response time of circuits t τ I V (t) F F e OUT 1 F F Fe e τ 1 I t LH

26 Example (cont) With improved model t LH =? 1 F F I Fe e t 1 LH τ F1 F Fe e τ 1 1 τ 1 1 e e t LH t LH F(1-1/e) I F t LH I=0V, F=5V R C Wp L t tlh t =R C LH Wp L

27 V OUT Example (cont) 5V C Gp C Gn R W 1pf With improved model V C L V OUT 5V C Gp C Gn R Wp =6K 0V 1pf V V =5V C L 2K 1pF 2n sec t R C HL Wn L 6K 1pF 6nsec t R C LH Wp L Note this circuit is quite fast! In the ON 0.5u process Note that t HL is much shorter than t LH Often C L will be even smaller and the circuit will be much faster!!

28 ummary: What is the delay of a minimum-sized inverter driving a 1pF load? X C L 1pF 2K 1pF 2n sec t R C HL Wn L 6K 1pF 6nsec t R C LH Wp L In the ON 0.5u process

29 rain Improved switch-level model Gate G ource C G R W V G witch closed for V G = large witch open for V G = small Previous example showed why R W in the model was important But of what use is the C G which did not enter the previous calculations? For minimum-sized devices in a 0.5u process C G 1.5fF R sw 2KΩ 6KΩ n channel p channel

30 One gate often drives one or more other gates! What are t HL and t LH?

31 Example: What is the delay of a minimum-sized inverter driving another identical device? X G p-channel Model R Wp? C Gp Load on first inverter C and C both 1.5fF Gn Gp G C Gn V n-channel Model R Wn C C 1.5fF Gn Gp Loading effects same whether C Gp and/or C Gn connected to V or GN C Gp +C Gn 3fF For convenience, will reference both to ground

32 Is a capacitor of 1.5fF small enough to be neglected? 1pf 100pf 10fF 1fF.01uf 1pf rea allocations shown to relative scale: This example will provide insight into the answer of the question

33 Example: What is the delay of a minimum-sized inverter driving another identical device? ssume V =5V X X 3fF

34 Generalizing the Previous nalysis to rbitrary Load C L t R C HL Wn L t R C LH Wp L

35 Example: What is the delay of a minimum-sized inverter driving another identical device? X X 3fF 2K 3 ff 6 p sec t R C HL Wn L 6K 3 ff 18 p sec t R C LH Wp L o gates really operate this fast? What would be the maximum clock rate for acceptable operation?

36 Example: What is the delay of a minimum-sized inverter driving another identical device? X T CLK t R C HL Wn L t R C LH Wp L 6 p 18 p sec sec What would be the maximum clock rate for acceptable operation? T = t t CLK-min HL LH 1 1 f CLK-max = = = 40GHz TCLK-min 24psec nd much faster in a finer feature process!!?????? What would be the implications of allowing for 10 levels of logic and 10 loads (FO=10)?

37 Example: What is the delay of a minimum-sized inverter driving another identical device? UMMR X X 3fF 2K 3 ff 6 p sec t R C HL Wn L 6K 3 ff 18 p sec t R C LH Wp L Note this is very fast but even the small 1.5fF capacitors are not negligable!

38 Response time of logic gates C L t R C HL Wn L t R C LH Wp L - Logic Circuits can operate very fast - Extremely small parasitic capacitances play key role in speed of a circuit

39 tick iagrams It is often necessary to obtain information about placement, interconnect and physical-layer structure tick diagrams are often used for small component-count blocks pproximate placement, routing, and area information can be obtained rather quickly with the use of stick diagrams

40 tick iagrams Metal 1 poly n-diffusion p-diffusion Metal 2 Contact dditional layers can be added and color conventions are peronal

41 tick iagram V B B B stick diagram is not a layout but gives the basic structure (including location,, orientation and interconnects) that will be instantiated in the actual layout itself Modifications can be made much more quickly on a stick diagram than on a layout Iteration may be needed to come up with a good layout structure

42 B tick iagram lternate Representations B B B

43 emiconductor Fabrication Technology Technology Files Fabrication C Provide Information bout Process Process Flow (Fabrication Technology) Circuits Model Parameters esign Rules erve as Interface Between esign Engineer and Process Engineer Insist on getting information that is deemed important for a design Limited information available in academia Foundries often sensitive to who gets access to information Customer success and satisfaction is critical to foundries evices

44 End of Lecture 6