Digital VLSI Design I

Transcription

1 The University of Toledo Section f04ms - EES:460/560 Digital VLSI Design I: Basic Subsystems Digital VLSI Design I MIDTERM EXAMINATION Problems Points Total Was the exam fair? yes no

2 The University of Toledo Section f04ms - EES:460/560 Digital VLSI Design I: Basic Subsystems Problem 4 points Mark your yes, no, or not applicable answers for all the given choices!.. onsidering unit size tranzistors on the same chip, which of the following driving circuits will charge a large capacitive load, LOAD, within the shortest time: x two transmission-gates in parallel. x two p-channel transistors in series, x two p-channel transistors in parallel, x two n-channel transistors in parallel, x two transmission-gates in cascade,. P-well manufacturing process is used to fabricate: x TTL familiy logic circuits, _x MOS familiy logic circuits, _x BiMOS familiy logic circuits, x I L familiy logic circuits,.3 Integrated circuits with enhanced radiation tolerance are manufactured using: x the MOS p-well process; x the BiMOS n-well process; x the MOS twin-tub process; _x the silicon on insulator process..4 Design rules dictated by the I manufacturing processes: _x specify the minimum feature sizes, x specifythe maximum feature separations, x specify the maximum feature sizes, _x specify the minimum feature separations, _x are dependent on the layers in which features are located, x are determined by the layout designer.

3 The University of Toledo Section f04ms - 3 EES:460/560 Digital VLSI Design I: Basic Subsystems. 5 The most important measure of the quality of a VLSI layout design is: x the size of the chip area occupied by the design, x the number of logic gates in the layout. x the dynamic power consumed by the layout, x the number of transistors in the layout,.6 Gate logical effort g G of a logic gate G is dependent on: x gate s own parasitic capacitances, _x parasitic input capacitance of G, x the capacitance L loading the output of G, _x parasitic input capacitance of the reference inverter..7 Gate branching effort g B of a combinational logic gate G is dependent on : _x the the number of gates whose inputs are connected to the output of G, x the number of inputs of G, x the the logic functions of gates whose inputs are connected to the output of G, _x the number of outputs of G.

4 The University of Toledo Section f04ms - 4 EES:460/560 Digital VLSI Design I: Basic Subsystems Problem points Figure. Shows the logic model of a combinational circuit, and the electrical model of its reference inverter, which were manufactured on the same integrated circuit substrate. Minimum size, X, +V DD Gi = Ri = 5fF L = 450fF r Gi G G G3 L Ri Ro L (a) (b) Fig.. ombinational logic circuit. (a)logical model. (b)electrical model of the reference inverter.. symmetrical reference inverter G s transistors are characterized by the following properties: - L p = W n = L n = λ, - transistor device transconductances k n and k p of the reference inverter circuit have been made equal by adjusting the aspect ratio r of the p-channel transistor to the value r =.5, r = W p L p = µ n µ p =.5 Determine the following characteristics of the cascade of logic gates in Figure.(a): - expression which shows the path effort of a cascade of logic gates, and calculate its value in the case of the cascade of Figure.(a), - expression and the value of the minimized path effort delay D F of the cascade of Figure.(a) which would be realized if all gates in the cascade were designed to have the same optimal value of the gate effort. Hint # For full credit, give answers to all questions, prepare all required circuit diagrams, write all equations for which the space is left, and show all symbolic and numerical expressions whose evaluation produces shown numerical results.

5 The University of Toledo Section f04ms - 5 EES:460/560 Digital VLSI Design I: Basic Subsystems Solution An explicit demonstration of understanding the following solution steps is expected.. Prepare the expression of the parasitic input capacitance Ri of the reference inverter as a function of the aspect ratio r, and the parasitic input capacitance gn of the n-channel transistor in the reference inverter circuit, and write it in the space reserved for equation (-). Ri = gn + gp = ox (A cn +A cp ) = ox W n L n (+r) = gn (+r) (-). Solve the formula (-) for the parasitic capacitance gn and calculate its value, showing your calculation in the space reserved for equation (-). gn = Ri 5 = = ff +r +.5 (-). 3 Figure. shows the electrical models of the NAND and NOR gates of Figure.. +V SS +V SS r r r r (a) (a) Figure. Electrical models of the MOS gatess in Figure.. (a)nand. (a)nor. Using the parasitic capacitance gn as the base unit of input capacitance, derive expressions for the input capacitances of the NAND and NOR gates of Figure., and calculate their values; write the calculations in the space reserved for equation (-3). Gi = NANDi = gn (+ r) = 4.3( +.5) = 9.35fF G3i = NORi = gn (+r) = 4.3( +.5) = 5.8fF (-3)

6 The University of Toledo Section f04ms - 6 EES:460/560 Digital VLSI Design I: Basic Subsystems. 4 Prepare expressions of the logical efforts of the gates of Figure. and calculate their values; write the calculations in the space reserved for equation (-4). g G = g R = + r +.5 g G = g NAND = = =.3 + r +.5 (-4) +r +.5 g G3 = g NOR = = + r +.5 =.7. 5 Prepare the expression of the path logical effort of the cascade of logic gates of Figure.(a) and calculate its value; write the calculations in the space reserved for equation (-5), G = g G g G g G3 =.3.7 =. (-5). 6 Prepare the expression of the path electrical effort of the cascade of logic gates of Figure.(a) and calculate its value; write the calculations in the space reserved for equation (-6) H = L Gi 450 = = 30 (-6) 5. 7 Prepare the expression of the path effort of the cascade of logic gates of Figure.(a) and calculate its value; show your calculation in the space reserved for equation (-7). Since there is not any branching witin the path, the path branching effort equals one, and the path effort of the cascade is, F = G B H =. 30 = 66. (-7). 8 Prepare the expression of the common gate effort, f, of the gates in the cascade of Figure.(a), which will provide the minimum path delay for the cascade, and calculate its value; show your calculation in the space reserved for equation (-8). f = F N = 66 3 = 4.04 = 4 (-8).9 Prepare the expression of the minimized path effort delay D F of the cascade of Figure.(a), which would be realized if all gates in the cascade were designed to have the same optimal value of the gate effort obtained in equation (-8); calculate its value and show your calculation in the space reserved for equation (-9). D F = N f = 3 4 = (-9)

7 The University of Toledo Section f04ms - 7 EES:460/560 Digital VLSI Design I: Basic Subsystems Problem 3 5 points Given is a logic function of five variables, Z = (A+B +D) E. Design a static MOS gate that implements Z using a single unbroken row of p-diffusion for all p- channel transistors, and a single unbroken row of n-diffusion for all n-channel transistors. In your design show the following steps Draw an electrical model of the gate and show it in the space reserved for Figure onstruct a graphical representation of the graph of the electrical model G EM in which: - circuit nodes are represented by vertices, and transistors are represented by edges, - p-block subgraph is drawn in red colour, and n-block subgraph in black color, - edges are labelled by the signals on the corresponding transistor gates, show the prepared graphical representation of G EM in the space reserved for Figure 3.. V DD B A D I I E V DD E B I A E I 3 Z = (A+B +D) E Z D I B E I 4 D A A I3 D B V SS V SS I4 3. Electrical model of the static MOS gate. 3. Graph of the electrical model G EM.

8 The University of Toledo Section f04ms - 8 EES:460/560 Digital VLSI Design I: Basic Subsystems Prepare the list of - Euler trails in the p-block subgraph, - Euler trails in the n-block subgraphs, - all pairs of Euler trails common to the n-block and p-block subgraphs( which have the same ordering of line labels in both subgraphs). p-block n-block common to p and n blocks ADEB BEDA ABDE EDBA BADE EDAB ADEB BEDA ADBE EBDA BADE EDAB BADE EDAB BEDA ADEB BDAE EAD B BADE EDAB DABE EBAD BEDA ADE B DBAE EABD Draw a sticks layout representation of the single-metal-layer layout with horizontal diffusion rows, and vertical signal lines, using: - yellow lines for p-diffusion, - green lines for n-diffusion, - red lines for polysilicon, - blue lines for meta, show the prepared sticks layout representation in the space reserved for Figure 3.3 B A D E Z Y V DD Legend p-dif n-dif poly metal cont.cut V SS Figure 3.3 Sticks representation of the layout.