Multiple Valued Logic - MVL
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1 Multiple Valued Logic - MVL Olivier entieys Juin 21 1 What is MVL? Currently, computers and other electronic devices run as 1111 binary logic with 2 logical states:, 1 Multivalued logic offers many logical states:, 1, 2, 3, 4,5 and more complex functions in less time and space than binary applications Until the U-LOC technology was developed, MVL was impractical or unachievable through conventional means, and drew only theoreticians and researchers looking for the key to making it usable U-LOC was invented in the 199 s by an Olson and is proving to be the long sought solution 2 1
2 Technical advantages of U-LOC MVL circuits and devices A decrease in required power A decrease of passive parasitic values Ability to perform multiple logic functions in one operation e.g. (A+) AN An increase in data density Reduced package size due to fewer required pins uperior performance (more bandwidth) with a reduced clock rate 1 Mbit/s = 125 kbyte/s 1 byte = 5-6 ternary digit 75 ktit/s 3 Introduction Les bases pour aborder la MVL Les fonctions à 1 entrée Les fonctions à 2 entrées 4 2
3 Transistors à enrichissements Le MOFET à enrichissement avec un canal N G Vgs Conduction : Vgs > Vt n > e.g..45v Id > Vds > Quand la ource est reliée au ulk En logique binaire G G Le MOFET à enrichissement avec un canal P Vgs Conduction : Vgs < Vt p < e.g G Id > Vds < Quand la ource est reliée au ulk En logique binaire G G 5 Les transistors à appauvrissements Le MOFET à appauvrissement avec un canal N Conduction : Vgs > V't n < e.g. -.45V G G Le MOFET à appauvrissement avec un canal P G G Conduction : Vgs < V't p > e.g
4 Les caractéristiques : Id = F(Vgs) Id PMO à Enrichissement PMO à Appauvrissement NMO à Appauvrissement NMO à Enrichissement Vtp V'tn V'tp Vtn Vgs 7 Number representation ecimal inary Ternary A Z Y X W V ##### ##### ##### ##### ##### ##### ##### ##### 8 4
5 Les Fonctions à 1 entrée Les fonctions élémentaires L inverseur binaire L inverseur ternaire 9 Les fonctions élémentaires Les fonctions logiques binaires X E Id Not E es fonctions logiques ternaires (27) X E E 1 E 2 C C 1 C 2 N(x) Id(x)
6 L inverseur binaire Vgs=-5V -3.25V Vdd E = 1 Vdd = 5V E = Vgs=V 3.25V Vss E Vgs=V Vdd Vss = V E = V E = 3.25V Vgs=5V Vss 11 La logique 3 valeurs F(x) = <2 > = C(x) X 1 2 F 2 ifférentes négations X N(x) = < 2 1 > C(x) = < 2 2 >
7 C + Q5 Q4 GN 13 The three requirements of U-LOC: There must be one controllable path, or branch, from a source of power to an output terminal of a circuit, per output logic level Only one controllable path, or branch, conducts from a source of power to an output terminal per input logic level, contiguous group of input logic levels, or unique combination of input logic levels There must be «r» different sources of power, each source of power represents only one of «r» different logic levels 14 7
8 Inverseur 3-VL = Figure 5 = 1 Figure 6 = 2 Figure 7 V1 Q2 Q3 Q1 Q4 15 Inverseur 3-VL - = Vgs=-5V Vgs=-2.5V -3.25V V1 =2.5V =5V Q1 PMO à PMO à Enrichissement Appauvrissement Id NMO à Appauvrissement NMO à Enrichissement.75V Q2 Vt-p Vp-n Vp-p Vt-n Vgs V Q3 Vgs=-5V Vgs=V 3.25V Q4 Retour 16 8
9 Inverseur 3-VL - =1 Vgs=-2.5V Vgs=V -3.25V V1=2.5V =5V Q1 PMO à PMO à Enrichissement Appauvrissement Id NMO à Appauvrissement NMO à Enrichissement.75V Q2 1 Vt-p 1 Vp-n Vp-p Vt-n Vgs -.75V Vgs=V Q3 Vgs=2.5V 3.25V Q4 Retour 17 Inverseur 3-VL - =2 Vgs=V Vgs=2.5V -3.25V V1=2.5V =5V Q1 PMO à PMO à Enrichissement Appauvrissement Id NMO à Appauvrissement NMO à Enrichissement.75V Q2 2 Vt-p Vp-n Vp-p Vt-n Vgs -.75V Vgs=5V Q3 Vgs=5V 3.25V Q4 Retour 18 9
10 Inverter delay and Power.25 micron technology Cl = 5fF ELO simulator inary delay power ->1 8ps 3,1 uw 1-> 8ps 265 nw Ternary delay power 2->1 14ps 47 nw 1->2 85ps 97 nw 2-> 16ps 411 nw ->1 11ps 436 nw 1-> 82ps 35 nw ->2 142ps 1,5 uw 19 Les Fonctions à 2 Entrées ET/OU X.Y = MIN(X,Y) X+Y = MAX(X,Y) Associativité, commutativité C(X+Y) = C(X).C(Y) C(X.Y) = C(X)+C(Y) Idem avec N(x) A plus, N(A plus ) 2 1
11 Les Fonctions à 2 Entrées Etude de la fonction CGAN3 ( NAN2) (CGAN = Complementing Generalized AN) A CGAN3 A La fonction CGAN3 éfinir les paramètres du circuit évelopper le tableau de Karnaugh éterminer les liens logiques entre les entrées et la sortie Concevoir le circuit 22 11
12 Etape 1 - CGAN Logique ternaire [ 1 2] V = Volts V1 = 2.5 Volts = 5 Volts LV = 2.5 Volts (Logic tep Voltage) OP = 7 % (Overlap Percentage) X 1 2 LV (Volts) V (volts) X=1 OP (%) t (temps) 23 Etape 2 - CGAN A
13 Etape 3 - CGAN A A A Etape 3 - CGAN A = x = 2 x = = 2 = 1 1 = 1 1 = 1 = 1 = 2 = 2 = 26 13
14 Etape 4 - CGAN ranches extrêmes E > : canal NMO E < : canal PMO ranches intermédiaires E < : canal PMO E et NMO E = : canal PMO et NMO E > : canal PMO et NMO E Vtn = Vi - (Vo + (OP*LV)) : transistor N Vtp = Vi - (Vo (OP*LV)) : transistor P 27 Etape 4 - CGAN Q1 Q2 V1 Q3 V1 A A 3.129V Q4 Q V Q6 V 4.348V Q V Q8 V GN 28 14
15 Etape 4 - CGAN Q1 V 2 Q2 Q16 Q17 V 1 Q18 V 1 C C Q2 Q3 A A Q4 Q19 Q14 Q5 Q6 Q2 Q13 Q7 Q8 Gnd 29 Additionneur ternaire Equations logiques Logique binaire Logique ternaire Complexité 3 15
16 Logique binaire a i b i c i i c i i = aibici v aibici v aibici v aibici ci+1 = aibici v aibici v aibici v aibici ci+1 = aibi v aici v bici 31 Logique ternaire a i b i c i i c i i = e1c(ai)c1(bi)c(ci) V e 1C1(ai)C(bi)C(ci) V e 1C2(ai)C2(bi)C(ci) V e 1C(ai)C(bi)C1(ci) V e 1C1(ai)C2(bi)C1(ci) V e 1C2(ai)C1(bi)C1(ci) V C(ai)C2(bi)C(ci) V C 1(ai)C1(bi)C(ci) V C 2(ai)C(bi)C(ci) V C (ai)c1(bi)c1(ci) V C 1(ai)C(bi)C1(ci) V C 2(ai)C2(bi)C1(ci) Ci+1 = e1[c1(ai)c2(bi) v C2(ai)C1(bi) v C2(ai)C2(bi)] v c i[c2(bi) v C1(ai)C1(bi) v C2(ai)] 32 16
17 Logique ternaire 33 Additionneur ternaire Optimisation FA ternaire A plus A plus plus carry A plus plus C plus carry Comparaison avec binaire inaire : adder 16 bits Ternary : adder 1 tits 34 17
18 C + Q5 Q4 GN 35 C1 M5 + M1 M2 M3 M4 MbreakN MbreakN+ M6 MbreakN+ GN 36 18
19 C2 M1 + M2 M3 M4 MbreakN+ MbreakN GN 37 AN à 3 entrées Q1 Q2 Q16 C C V1 Q15 Q3 V1 Q9 V1 Q1 A A Q14 Q5 Q4 Q6 Q11 Q12 Q13 Q7 GN Q
20 OR à 3 entrées Q1 Q2 Q16 C A C A V1 Q15 V1 Q6 Q2 Q9 V1 V1 Q1 Q11 Q14 Q4 Q3 Q12 L = 4u W = 3u Q13 L = 4u W = 3u Q7 L = 4u W = 3u Q8 GN 39 Goal of our project emonstration of the U-LOC technology efficiency for MVL (3L, 4L) Power-peed Efficiency Telecommunication application context igital ignal Processor Architecture edicated Processing Unit (arithmetic unit, hard-wired multiplier, register file) Internal Memories (ROM, RAM) imple control model 4 2
21 chedule (1) tudy the power-speed efficiency of U-LOC circuits on representative blocks (arithmetic, memory, etc.) Ternary and Quaternary Logic Compare the results with their equivalent in binary Adder Multiplier Register 41 chedule (2) efinition of a library of U-LOC standard cells at the transistor level (flip-flop, latch, logic gates, arithmetic functions, multiplexer). Characterization in terms of power, speed, area efinition of VHL-based models of U-LOC standard cells at the gate (and transistor?) level
22 chedule (3) esign of typical arithmetic and logic elements of a P (multiplier, ALU, barrel shifter, register files). esign of a igital ignal Processor. VHL based design imulation for verification imulation for characterization efinition of a CA tool for designing U-LOC structures 43 What we have done esign of basic U-LOC structures using pice models Ternary Full-Adder Porting of the structures in TM.25µ technology (depletion transistors extrapolated) efinition of a VHL package for simulation T_TERNARY_LOGIC 44 22
23 Research directions Logic ynthesis and Mapping for MVL and U/LOC I/MVI (UC) CA Tools Technology OI, new transistors Communications in higher radix than
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