Impact of Solder Voids in Copper Clip Junctions on SOA of Trench Power MOSFETs

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1 Faculty 06 Department of Applied Sciences and Mechatronics Impact of Solder Voids in Copper Clip Junctions on SOA of Trench Power MOSFETs Master Thesis of Milan-Marcel Buttberg Supervisor: Prof.Dr.Rer.Nat. Alfred Kersch Dipl.-Ing. Rainald Sander (Infineon Technologies AG) September 30, 2018


3 Abstract As the trend in automotive industry goes from power bond wires to copper clips, in this thesis the impact on SOA of solder voids in the copper clip junction of a power MOSFET was investigated by measurements and simulation. Therefore artificial voids were created using selective wet etching of the solder layer. The MOSFET used for experimentation has a split gate and can therefore be biased on the left or right side of the temperature compensation point. Both has been simulated with the Infineon simulator Eltic. It was found that for biasing the device in thermal instability condition, voids can only be a second order effect, worsening an already bad situation due to process variations. For biasing the device in the temperature stable region it was found that the process of selective etching weakened the devices by being not selective enough and therefore etching the source metallization, which is crucial for thermal performance of the device. As this effect was found by simulation by predicting the location of burnmarks, the simulator Eltic was greatly approved as powerful development tool. I

4 Contents Introduction 1 1 Power MOSFET Technologies for Automotive Applications Concept of Safe Operating Area (SOA) Integrated Smart Switches and Power Trench MOSFET Technologies High Power Package with Copper Clip Formation of Solder Voids in Chip Junctions Thermal Run-Away in Power Trench MOSFETs Materials and Methods MOSFET used for Experiments Processing Artificial Voids FVM Simulator: Eltic SOA Test Bench Detection of Solder Voids in X-ray Images using Matlab App Designer Impact of Solder Voids on Safe Operating Area Fully Activated Devices Experimental and Analytical Investigation Investigation by Electro-Thermal Simulation Conclusion Partially Activated Devices Experimental and Analytical Investigation Investigation by Electro-Thermal Simulation Conclusion Summary and Outlook 37 A Appendix: Source Code for Void Detection MATLAB App 39 References 44 List of Figures 46 II

5 List of Tables 46 List of Abbreviations 47 Acknoledgements 48 III

6 Introduction In automotive industry there is a high demand to replace electro-mechanical relays by smart switches or power metal-oxide semiconductor field-effect transistors (MOSFETs). The respective integrated and power MOSFET technologies need to provide higher efficiency at lower costs. In recent years this was achieved by reducing the feature size and using vertical trench technologies for power MOSFETs. Trench technologies have a lower area resistance and are capable of higher current densities than former technologies. As the technologies get better and better aluminium bond wires used to connect the MOSFET die with the package pins have been the bottle neck in terms of maximum current. Also the minimum on-resistance, R DSon, is limited by using bond wires. For example, one third of the R DSon of a 1.5 mω switch is due to bond wires. Hence a new approach of connecting the die to the package is by using a so called copper clip. Instead of supersonic bonding, the clip is soldered to the die and the package pins in the same reflow solder process connecting the die with the leadframe. Using copper instead of aluminium has many profits. Compared to aluminium copper has around a factor of 1.5 better electrical conductivity ( S m 1 vs S m 1 ) and a factor of two better thermal conductivity, (236 W m 1 K 1 vs. 401 W m 1 K 1 ). Also the clip provides an increased contact area and cross section, minimizing the overall resistance of a copper clip device while increasing the total power dissipation by better cooling connection. But as promising as this all sounds, there are some downsides. In a reflow solder process at atmospheric pressure using lead containing solder there will be solder voids in the junction due to evaporated solder flux being trapped within the solder junction under the clip. As using copper clips is new in automotive industry, yet there is no experience of how solder voids in copper clip junctions can alter the electro-thermal behaviour. For a new automotive power technology combined with copper clip a wide distribution in SOA is observed. What are the parameters that lead to such a wide distribution? Randomly distributed voids between clip and chip, but also between leadframe and chip could be the answer. But also the chip tilt, leading to inhomogeneous solder thickness between chip and clip thermally isolating areas below thicker solder due to its low thermal 1

7 conductivity of 53 W m 1 K 1. As there is no experience of the influence of solder voids between chip and clip, in this thesis the influence of solder voids between chip and clip will be investigated. Therefore chapter 1 will give a short introduction on the overall topic. Vertical power trench MOSFETs will be explained, as well as the concept of Safe Operating Area (SOA). An outline will be given on high power packages with copper clip and how solder voids formate in copper clip solder junctions. Chapter 1 ends with a description of thermal run-away mechanism in power trench MOSFETs. This mechanism is crucial in understanding of how electro thermal simulations of power trench MOSFETs are modelled. Materials and methods used for experimentation and simulation will be shown in chapter 2; the MOSFET used for all experiments, how artificial voids can be made by a selective wet etch process and how the Infineon simulator Eltic works. Also, the test bench for SOA measurements will be described and how to create a void detection app, using Matlab app designer. In chapter 3 electro thermal simulations done with ELTIC are used to investigate SOA of a MOSFET with copper clip and corresponding artificial voids in the solder clip junction. Those simulations are covered by SOA measurements with and without artificial voids. Finally simulation and measurement results are compared to verify the electro thermal model and to get an insight on how strong voids are impacting the electro-thermal behaviour of the investigated MOSFET layout. 2

8 1 Power MOSFET Technologies for Automotive Applications Automotive electronic applications and its components have higher requirements in functionality and safety than regular electronic consumer products. Therefore intensive characterisation and testing is needed before a new technology or fabrication process is verified and appropriate products can be delivered. During such a testing of a new technology, the so called copper clip, replacing power bond wires in power MOSFET devices, a wide distributions in the SOA was detected for high drain to source voltages. As the copper clip is not attached by ultra sonic bonding, but by reflow soldering, this might be a source of distribution widening. Reflow soldering processes are commonly used in power MOSFET technologies to connect die and lead frame and are known for the occurrence of solder voids, which are small gas filled pockets trapped within the solder junction. This is known to sometimes have an impact on thermal and electrical characteristics of a device, depending on the void location and void size [1]. For later analysis of the influence of solder voids on copper clip junctions, the following sections give a short introduction on the overall topics like safe operating area (SOA), vertical power MOSFETs, the split gate MOSFET, which was used for the analysis, how solder voids form and how thermal runaway works in power trench MOSFETs. 1.1 Concept of Safe Operating Area (SOA) Safe operating area (SOA) of a MOSFET is the area in the drain-to-source voltage, V DS, - drain current,i D, diagram, where the device can be operated without failure. Such diagrams are standard in almost every MOSFET data sheet. Figure 1 shows an example of a SOA diagram for a NexFET TM Power MOSFET from Texas Instruments. The current in the first region, called on-resistance,r DS(on), limitation is simply limited by the on-resistance of the device, calculated by the well known ohmic law R DS(on) = U DS /I D, with U DS being the drain to source voltage across the device and I D the drain current through the device. Further increasing U DS leads to the power 3

9 Figure 1: Safe Operating Area diagram of an CSD19536KTT NexFET TM Power MOS- FET from Texas Instruments, showing different areas of limitation [2]. limitation area, where current is limited by the maximum allowed current through the weakest part of the device, for example the power bond wires. This region is followed by the maximum power limitation region, or also called the thermal impedance limitation, showing the maximum power the device is able to dissipate before failing. Necessarily this part has a slope of -1 on a double logarithmic scale plot. Derivation from this slope indicates the occurrence of thermal instabilities also referred to as thermal runaway, which will be explained later on (see section 1.5). The steeper the slope, the more prone the device is for thermal runaway. As thermal instabilities are time depending, for shorter pulse lengths, a higher maximum current is allowed. Therefore different timing lines are plotted. Finally the SOA is limited by the break through voltage, BV DSS, which is the maximum allowed voltage of the device. Exceeding this value will result in avalanche breakdown, which will mostly destroy the device [2]. To obtain data for such a diagram, you need a special tester, that can apply rectangular pulses of demanded U DS and control the drain current by regulating the gate to source voltage, U GS, for the desired pulse length. By repeating the measurement with increasing current until device breaking is 4

10 observed, the maximum ratings can be determined. 1.2 Integrated Smart Switches and Power Trench MOSFET Technologies Metal-oxide semiconductor field-effect transistors (MOSFETs) are the most important devices for high density integrated circuits such as microprocessors and semiconductor memories. But also in the field of power switching, MOSFETs play an important role.[3]. Especially in automotive there is high demand to replace electro mechanical relays by integrated smart switches. Integrated smart switches contain a power MOSFET, controlled by a logic circuit. Power MOSFET and logic circuit can be realized in one monolithic chip or be separated on different chips. When using the latter, both chips are connected within the package using bond wires. To make the switch a Figure 2: Schematic diagram of a trench power MOSFET. The conducting channel forms in the red areas, if the gate is biased positive. smart switch, usually there are certain security features implemented like open load detection, over temperature detection, short circuit detection and current monitoring, varying from variant to variant. But to make all of these features work, a low ohmic power trench double diffused metal-oxide semiconductor (DMOS) is needed. For N-channel devices (electrons are the 5

11 channel carriers) a cross section of a corresponding technology cell is shown in Fig. 2. On a highly n-doped substrate an epitaxial layer is grown usually using vapour-phase epitaxy (VPE), a modification of chemical vapour deposition (CVD). Adding a gaseous arsenic or phosphorous compound results in n-doped expitaxial layers [4]. After double diffusion of p-body and N + -source contacts, an etched trench of narrow width (around 1 µm) is oxidized to form a gate oxide lining the trench. The isolated trench then is filled with polysilicon by CVD. Subsequent thermal oxidation then caps and seals the polysilicon with a protective layer of oxide.. After contact etching to expose a gate contact and the source/body regions, all trench DMOS cells are interconnected by photo-lithographic deposition of metal, shorting the p-body to source, to form a three terminal trench MOSFET [5]. Except for the gate contact, a nearly planar surface is achieved that can easily be used for bonding or copper clipping the die to the package. An important parameter for describing and comparing power MOSFETs is the on-state resistance between drain and source contact, R DSon. A lower R DSon leads to less power dissipation P which can be calculated with the well known equation P = R DSon ID. 2 Lower power dissipation leads to lesser heating, resulting in a longer live time of the device. P-channel devices are rather uncommon for power devices as the mobility of the channel carriers, µ H, (holes for p-channel) is only around the half of the mobility µ E of electrons in case of n-channel devices. As the mobility µ is proportional to the conductance σ (hence also inversely proportional to the R DSon ) the area of a p-channel device needs to be twice as large compared to a n- channel device to achieve the same R DSon. This follows from the well known correlation I D C ox µ E/H (1) with the drain current, I D, the mobility µ E/H for electrons and holes,and the oxide capacitance, C ox = A ɛ r /d respectively, which contains the area A, that needs to be increased to compensate for the lower mobility of holes µ H in p-channel devices. For an idealized MOSFET, the basic output characteristics are shown in Fig. 3. The source contact is used as voltage reference throughout the rest of the chapter. The different graphs represent different gate voltages. The 6

12 Figure 3: Idealized drain characteristics for a MOSFET. The dashed lines separate the linear, nonlinear and saturation region[3]. operational area can be divided into three regions: the linear region the non-linear region or pinch-off the saturation region If we bias the gate so that V G > V th, (2) with the threshold voltage V th, electrons will accumulate in the p-body next to the trench and form a conducting channel, also called inversion layer. If a positive drain voltage, V D, is applied and increased, a proportional drain current will flow. The MOSFET operates as an ohmic resistor. This is why the linear region sometimes is also called the ohmic region. If V D is further increased, the drain current deviates from the linear relationship. The nonlinear region is reached. This region is characterized by V G V th V D. If this is the case, the electric field at the gate next to the drain becomes zero, hence also the charge, leading to a pinch-off of the inversion layer. Practically this means that the current cannot be increased further. Increasing V D beyond this point drives the device into saturation. The drain current remains nearly the same (for an ideal device) and the pinch-off point moves towards the source terminal. If V D is further increased, the technology maximum 7

13 voltage, called breakdown voltage, BV DSS, is reached. This mostly leads to device failure, due to avalanche breakdown, which causes an exponentially increasing current that heats up the device until destruction. 1.3 High Power Package with Copper Clip In the previous section there was explained how a power MOSFET is produced and how it can be used. But the die alone cannot be operated as there are no terminals or pins yet that can be easily connected to a circuitry. This is where some light should be put onto the package side of a MOSFET. After processing a wafer and sawing out the single dies, they need to be built into a package. This can be done (for a power MOSFET) by soldering the die to a copper leadframe using a reflow solder process. The top side is connected by wedge or ball bonding. For the source contact (where the power current flows) mostly wedge bonding is used due to bigger contact area. This lowers the current density along the source metal plate, resulting in less heating. But another option to bonding, now is the use of a copper clip, that is also soldered in a reflow solder process to the top metallization. Fig. 4 shows the interior of an opened TO-Leadless (TOLL) package. The opening was done by laser ablation. Following parts can be identified: 1. Leadframe 2. MOSFET die 3. Copper clip 4. Bond wires for gate and sensors 5. Pins As the soldering is done with a reflow solder process, the solder paste is applied to the surface of the leadframe. Then the chip is set onto the solder paste. Again solder paste is applied but to the chip surface and future pins of the leadframe. After putting the copper clip on top, the full stack is reflow soldered in a reflow ofen using a special temperature profile. The goal of such a reflow solder process is keeping device stress due to up heating during soldering as low as possible while ensuring a well soldered connection. A 8

14 Figure 4: A TOLL package. Removal of mold compound was done with laser ablation. 1) leadframe 2) MOSFET die 3) copper clip 4) Bond wires 5) Pins (mostly covered with mold mass). simplified sideview of the full stack can be seen in Fig. 5. Note that the sideview is not to scale. Figure 5: Side view of the TOLL package stack (not to scale). 1.4 Formation of Solder Voids in Chip Junctions When soldering is done, either by hand or in a (reflow) solder process, usually the solder contains solder flux, which has various functions. The simplest is being an reducing agent, preventing surfaces from oxidizing and dissolving oxides that are already present. While tin-lead solder attaches very well to copper, it poorly connects to oxidized copper. Adding solder 9

15 Figure 6: cross section of a MOSFET with copper clip, similar to Fig. 5. Different kind of voids can be observed: a surface void on top of the solder layer and a full void, reaching from top to bottom of the solder layer. flux to the soldering process leads to better coverage, avoiding the formation of beads, like it would happen on oxidized surfaces. While solder flux is mostly inert at room temperature, an increase of temperature brings the needed characteristics [6]. As the temperature rises, the flux starts to get gaseous, leading to out-gassing of the solder flux from the joint. If the gas cannot escape the solder, because there is something on top, like a chip or a copper clip, it is encapsulated within the solder, forming solder voids. These solder voids are gas filled bubbles below the surface. Some voids reach from the top surface down to the bottom, while others are located directly under the surface. For this thesis, the assumption is made, that voids always reach to the bottom. Solder voids can be detected by X-ray or by a cross section and optical inspection. The latter has been used to create Fig. 6, showing a surface void and a full void, reaching from top to bottom of the solder layer. In this thesis, the focus will be on the copper clip solder layer, as the backside solder, also called die attach, has been investigated over years and is well specified. 1.5 Thermal Run-Away in Power Trench MOSFETs Thermal runaway can occur when the MOSFET is biased on the left side of the temperature compensation point (TCP)1, where the drain current has a positive temperature coefficient (see fig. 7). For higher currents the coefficient becomes negative. As a MOSFET can be divided into many different cells that are connected in parallel, some cells have a higher/lower thermal For very high temperatures, thermal runaway can occur over the full VGS range due to leakage 1 10

16 Figure 7: I D -V GS -characteristics for different temperatures. The dashed line separates the areas with positive and negative temperature coefficient. Data from [7]. resistance R T, mostly depending on the layout. That means that cells with the highest R T will form hotspots, small areas with a temperature up to several hundred degrees higher than the rest of the device. This can be explained as follows: at low drain currents the decrease of threshold voltage is dominating the temperature behaviour, leading to current increase with increasing temperature. At higher drain currents, the decrease in channel mobility prevails, leading to a negative temperature coefficient or decreasing current with increasing temperature, respectively. At the TCP the temperature dependence disappears as both effects compensate themselves. The condition for thermal instability can be modelled as P G T P D T with P G the electrical power and P D the thermally dissipated power. For power MOSFETs this can be written as (3) V DS I D T 1 R Th (t) (4) where R Th (t) is the time depending thermal resistance and I D / T = 11

17 Figure 8: Main current contributors in a power MOSFET [7]. α T (I D ) is the temperature coefficient of the drain current. Equation 4 can only be fulfilled for a positive temperature coefficient α T (I D ) [8]. Hence, the stability criterion S can be introduced as S 1, unstable S = V DS α T R Th, (5) S < 1, stable. To better understand the mechanism of thermal runaway, the understanding of the dependence of the drain current on the temperature is essential. The operation points of interest are in the saturation region of the MOSFET (V DS V GS ), but below the breakthrough voltage. There, the dependence of I D on V DS is minimal and can be neglected [9]. The models shown here only account for the temperature and V GS dependence of I D. In the temperature and bias range, I D in a power MOSFET can be divided into three parts: the MOSFET current I MOS impact ionisation current I ii collector current I J of the parasitic npn-bipolar transistor Fig. 8 shows the three contributors in an equivalent circuit. R b is the internal body resistance and is generally low in power trench MOSFETs 12

18 due to basic device geometry. I MOS can be described with the well known formula for the MOSFET current in saturation region I MOS (V GS, T ) = µ eff (T ) K 2 (V GS V Th (T )) α (6) with µ eff (T ) the effective temperature depending carrier mobility, a constant K ɛox W L d ox accounting for the gate oxide capacitance, channel width and channel length. V Th is the temperature dependent threshold voltage, which can be described as V Th (T ) = φ poly,s (T ) Q ox C ox + 2ψ B (T ) + n i (T ) = φ poly,s (T ) = kt ( ) q log ND,poly N A n i (T ) 2 4qN A ɛ S ψ B (T ) C ox (7) ( N C N V exp E ) ( g(t ) T (3/2) exp E ) g(t ) 2kT 2kT with φ poly,s (T ) the work function difference between gate n + -poly-silicon and the p-body of the MOSFET, N D,poly the donor impurity concentration of the poly-silicon gate, N A the acceptor impurity concentration of the body, n i the intrinsic carrier concentration, Q ox the charge per unit area due to oxide traps, interface states, etc., C ox the gate oxide capacitance, ψ B (T ) the Fermi potential, ɛ s the permittivity of silicon and µ eff (T ) the effective carrier mobility. Impact ionisation occurs when the electric field within the bodydrain region becomes large enough, for example near the breakdown voltage of the device. As this effect has a negative temperature coefficient, it can not be responsible for a positive temperature coefficient of the drain current on the left side of TCP. The collector current I J of the parasitic npn-bipolar transistor can be described as the sum of two main parts: the electron diffusion current I ne injected at emitter-base junction and the reverse current I cb of the base-collector pn-diode due to electron-hole generation in the base-collector junction. I C (T ) = I ne (T ) exp ( ) qvbe kt (8) (9) + I cb (T ) (10) with V BE the base-emitter voltage. If operated in active operation, the current would rise exponentially with V BE. 13 But in trench power MOSFET

19 Figure 9: Same power pulses with different bias values lead to different temporal temperature profiles at thermally critical cells. Data from [8]. technologies the base resistance R b is very low, suppressing the active operation due to a low voltage drop V BE. As I ne (T ) n 2 i the temperature dependence is dominated by the intrinsic carrier concentration. I cb is also depending on n 2 i. Thus, for high temperatures, I C is rising drastically [3][7]. This electro-thermal coupling can further aggravate self heating, which is crucial in modern power technologies, due to the very low area-specific onresistance, which can lead to biasing on the left side of the TCP for regular operation points. Thus device dimensioning and layout is crucial for the reliability of power MOSFET application. The dependence of temperature coefficient from the operating point leads to various interesting effects. Applying constant power pulses to a device at different operating points ( P = U DS I D = const.) lead to different temporal temperature profiles in a thermally critical cell (see fig. 9). If the device is biased at higher current, it is on the right side of the TCP. So cells that are badly thermally connected, self-regulate themselves by increased electrical resistance and so lower current, resulting in less power dissipation and less heating. Not so for lower drain current, where the temperature rises exponentially after the onset of thermal runaway at about 10 ms. Therefore it is desired to bias devices on the right side of the TCP. One approach to full-fill this requirement, is to not switch on all DMOS cells, but for example 50 % of all cells (= every 2nd cell). For the desired operation point, now a higher V GS is needed, therefore the operation point may shift to the temperature stable area. 14

20 2 Materials and Methods In this chapter the experimental approach will be shown. To test the influence of voids on the SOA of a new developed MOSFET with copper clip, a process has been developed that is capable of processing artificial voids between copper clip and MOSFET at four different locations of the clip, more specifically at the four corners. The idea is to produce huge voids up to an area of 50 % to find a correlation between void size and SOA. The devices with artificial voids are then tested on a SOA test bench until failure. Then they can be compared to regular devices without artificial voids. Regular devices still have regular voids of up to 10 % area of the clip solder area due to the solder process (see sec. 1.4). To determine the void area, a MATLAB app has been created using MATLAB App Designer, that is capable of determining the void area from an X-ray image. It is important to create the X-ray images after the SOA measurement, because X-ray is not a non-destructive analysis method. As X-ray is ionizing radiation, it can alter the threshold voltage of a device by ejecting electrons from the gate oxide, leading to permanently trapped positive charge, that leads to a decrease of V Th in case of a N-FET. As we have seen in section 1.5, effects like thermal runaway are strongly depending on the gate and threshold voltage. So it is crucial to not affect this parameters by experimental methods. Figure 10 shows how strong the drift of V Th can be. As the drift is proportional to the absorbed dose D = E/m, that is measured in [Gy] = [J kg 1 ], the Figure 10: Drift of threshold voltage V Th with increasing absorbed dose. Data from [10]. 15

21 effect worsens for longer X-ray timings as the energy is proportional to the number of absorbed photons with energy ω. So the absorbed energy E abs can be written as E abs = ω n(ω) dt (11) with ω taking the spectral distribution into account, n(ω) the absorption rate and the time t. This is why the effect worsens over time. For this exemplary observation an N-FET was used. After taking the X-ray images for all tested devices, the mold mass is removed completely and the burn marks are detected by optical measures. Burn marks are the areas of failure, where the device started melting due to too much thermal stress. Using the Infineon finite volume simulator Eltic, the observed behaviour is simulated. 2.1 MOSFET used for Experiments For all experiments, a newly developed MOSFET base chip for an upcoming integrated smart switch has been used. This MOSFET has a split gate. One gate only controls a percentage of the active area (called G lin ) so that the device will be biased on the right side of TCP, while the other one controls the remaining area. Fully activated device will be used throughout this thesis when biasing the device with both gates is meant. This leads to biasing the device on the left side of the TCP, where thermal runaway can occur. The basic circuit of the device is shown in Fig. 11. Figure 11: Split gate circuitry of the MOSFET used for the experimentation. The device after packaging can be seen in Fig. 12. The device on the left hand side is a regular one, just how it comes out of production. The middle device is partially opened by laser ablation. Below the very thin bond wires some mold mass rests can be seen. On the right hand side, one can see 16

22 a device without any mold mass. Here the mold mass was wet chemically dissolved. The bonded pins were also removed, as the bond wires with a diameter of 30 µm cannot hold the pins alone without mold mass. Figure 12: Overview of different package opening states. 2.2 Processing Artificial Voids The first step in processing artificial voids is the partial opening of the package by laser ablation. This has been done in the Infineon Failure Analysis (FA) Munich. Four different locations have been chosen (fig. 13). The locations are named for future reference: upper right (UR) upper left (UL) lower left (LL) lower right (LR) The laser ablation process needs around 9 runs to remove nearly all of the mold mass within the marked area. As the laser might penetrate the metallization and weaken the underlying structures, it is important to leave a last layer of mold mass. At 26.0 A and 20 khz with a velocity of 250 mm s 1 8 runs are needed. The rest of the mold mass was removed with wet etching. Therefore 9:1 mixed HNO 3 (nitric acid) and H 2 SO 4 (sulfuric acid) was dropped into the resulting gap for just some seconds, afterwards rinsing 17

23 Figure 13: Four different package opening positions, upper right (UR), upper left (UL), lower left (LL) and lower right (LR). with deionized water and drying. For a selective under-etching of the leadtin solder layer between copper clip and copper metallization, a 1:1 mixture of C 4 H 4 O 2 (acetic acid) and H 2 O 2 (hydrogen peroxide) was prepared and heated to 50 C. All devices were put into a big beaker and then the heated acid was carefully added to not change the orientation of the devices (top to top) (see Fig. 14). After the etch time, the acid was poured out and deionized water was added into the beaker. After removal of the water and drying the devices with N 2, they were ready for SOA measurements. Figure 14: Void etch process in the Failure Analysis Lab in Munich. In the beginning, it was planed to achieve different void sizes with different etch timings. Therefore a measurement series was prepared to find the right timings for voids of 15 % to 25 %. In the end an etch time of 2.5 min was chosen, as the void size did not directly correlate with the etch time. This has various reasons: Depending on the solder thickness, the lateral etch rate is bigger for thinner solder. Also the position of the copper clip varies. As the position of the gaps are based on the leadframe and are therefore 18

24 always at the same position but not the clip, the etch rate varies depending on how much of the copper clip corners are exposed to the etch. All of this effects make it hard to control this process. The chosen etch time of 2.5 min resulted in a wide variation of void sizes (see fig. 15). Figure 15: Distribution of void sizes with constant etch time of 2.5 min. The dashed line indicates a regular standard normal distribution. The derivation, resulting in the tails on the left and right end of the distribution, result from the superposition with other variables, like change in solder thickness and clip position. As has been lately found, the selectivity for copper is not zero. This leads to an etching of the top copper layer. While acetic acid would only remove copper oxide, hydrogen peroxide is strongly oxidizing copper [11] [12], resulting in a low, non-zero copper etch rate. In the end a selectivity of 500:1 (solder : copper) can be estimated. This systematic error has a strong impact on the experimental results and will be discussed in Sec FVM Simulator: Eltic For simulations the Infineon simulator Eltic was used, originally developed by Martin Pfost. This powerful simulator is capable of directly deriving a 3-D model from a 2-D chip layout. The resulting geometry is build up as layer model. Eltic is a 3-D numerical temperature simulator for solving the heat conduction equation: c v (T ) = T t = div (λ(t )grad(t )) + p (12) 19

25 Figure 16: a) top view and b) cross section (not to scale) of a 3-D simulation mesh for five MOSFETs. Heat sources correspond to red boxes. Source metallization and mould mass have been neglected for better visualisation [9]. Both, the specific thermal conductivity λ(t ) and the heat capacitance c V (T ) are depending on the temperature. As the thermal conductivity of silicon decreases significantly in the simulated range (decrease by 55 % from 25 C to 300 C), the well known power law approximation is used: ( ) T α λ Si (T ) = λ(t 0 ) (13) T0 For α = 1.28 and λ(t 0 ) = 147 W m 1 K at 300 K an excellent match with literature data is obtained. Highly doped substrates, which are common in high power MOSFET technologies, have a considerable lower thermal conductivity [13]. Therefore the approximation given in [14] is used. For accurate results also the specific thermal capacitance of silicon c v,si is well approximated as (T/T 0 ) β c v,si (T ) = c 0 + c 1 (14) (T/T 0 ) β + c 1 /c 0 with c 0 = 711 m 2 s 2 K 1, c 1 = 255 m 2 s 2 K 1 and β = 1.85 for T 0 = 300 K [15]. Other materials, like metallization and mould mass, are considered as temperature independent, which is a good approximation as variations did not impact the simulation result as much as the silicon. As the simulator uses finite volume method (FVM), cuboids are used as meshing volumes. This is a very favourable choice for semiconductor devices, as they mostly are designed in Manhatten-like geometries. This makes it very easy to generate non-uniform meshes that can adapt to the geometry. An example of the meshing can be seen in Fig

26 Figure 17: Finite volume (one box of Fig. 16 describing the numerical problem. In the end thousands of boxes are interconnected [16]. The automatic mesh adaptation is done while solving. After the initial mesh was generated, a first solution is obtained. If certain criteria are violated (for example the maximum temperature difference between two adjacent boxes) the mesh if refined by splitting those boxes. To avoid big jumps in box sizes, adjacent boxes must only be twice as large as their neighbours. Figure 17 shows a single box with an equivalent thermal network. Each box contains a node with the temperature T, which is connected by conductances to its neighbours to take the heat flow into account. The heat capacitance is modelled by a capacitor. Thermal conductivity and thermal capacitance are depending on the temperature (12), also as the heat source p v to account for electro-thermal coupling. On the resulting thermal network, Kirchhoffs current law is applied, taking advantage from the analogy between thermal and electrical currents. At this point the advantage of using FVM shows up, due to the compliance of conservation laws, like conservation of heat flow and thus conservation of energy. As the desired operational points for significant self-heating are always in the saturation region of the MOSFET, the V DS dependence can be neglected. Thus the dissipated power P dis can be written as P dis = V DS I D (T,V GS ), (15) which describes the controlled heat source p v in Fig. 17. To determine the current in each box, the temperature is taken directly from the node. V GS is modelled to be constant along the whole MOSFET, which is a key simplifi- 21

27 cation. Therefore there is only one unknown in each box, the temperature. Additionally also V DS is said to be constant throughout the MOSFET. This greatly improves performance, as the electrical potential does not have to be solved. This approach is only valid, if the drain and source potentials are uniform along the device. This is true for low ohmic metal resistances which are featured in modern power MOSFET technologies. As the total power dissipation P dis is known, the simulator has to find V GS so that the sum of the dissipated power in each box is equal to the desired total power dissipation. This leads to an additional iteration loop. After determining the overall temperature distribution, the overall power dissipation is calculated. If the calculated power dissipation differs too much from the desired power dissipation, V GS is updated and the process is repeated, until a good match has been reached. For modelling the I D V GS characteristics, device simulations are used. Thereby also the influence of the parasitic NPN-transistor is taken into account, which is crucial for observing thermal runaway if the MOSFET is biased on the left side of the TCP. To show the importance of electro-thermal coupling compared to pure thermal simulation, Fig. 18 was created for a case study. The same power pulse was applied to a test chip layout. The temperature distribution on the surface was plotted, to show the difference in temperature uniformity. While a pure thermal simulation leads to a very uniform heating, the electro-thermal simulations leads to hotspots, which are several hundred degrees hotter, than the pure thermal simulation [9]. As will be shown later, the simulated hotspot locations are the areas where burnmarks occur in real measured devices. As there are many simplifications in this simulator, there should be put some light onto the impact of those simplifications. One key simplification is the assumption of constant V GS and V DS throughout the device. This is justified, as the voltage drop across the source metallization is in the order of some tens millivolt, which leads to T of some Kelvin. As the interest lies on temperature swings of several hundred degrees, this can be neglected. For biasing the device on the right side of the TCP (temperature stable region), this is not valid. Thus the simulator will overestimate the peak temperature. Compared to process and technology variations (for example chip thickness, solder thickness, voids...) this effect is negligible. For simulation of SOA a maximum device failure temperature of 550 C is supposed, also called the intrinsic temperature, defined as the temperature 22

28 Figure 18: Case Study: Comparison of thermal vs. electro-thermal simulation. Top view of the temperature distribution on the source metallization of a test chip for a 100 µs power pulse. where intrinsic carrier concentration and doping concentration become the same. This leads to failure by intrinsic conduction effects [17]. 2.4 SOA Test Bench For SOA measurements, a highly automated SOA test bench was used (Fig. 19). The test bench is capable of applying a constant drain-source voltage V DS for a given pulse length t while controlling the drain current I D by the gate voltage V GS. Therefore a common oscilloscope, a power supply with big capacitor bank, a gate control circuit with various security measures and a switch for switching on and off the pulse, are used. For current measurement a shunt resistor and a Rogowski coil was used. All components are controlled by a PC with LabView. The device under test (DUT) was connected with a special socket to avoid irreproducible solder contacts (Fig. 20). Parameter Symbol full active G lin Drain-source voltage V DS 40 V 40 V Pulse length t 100 µs 100 µs Starting current I D 10 A 120 A Pulse delay t del 2 s 2 s Table 1: Summary of SOA test parameters. 23

29 Figure 19: Highly automated SOA test bench: 1) oscilloscope (measurement of UDS, UGS and ID ) and power supply, 2) DUT, 3) gate control, over-current shutdown, pulse generation, Vsd measurement, 4) slave with high speed driver for on and off switching of the pulse, below a shunt resistor and a discharge circuit, 5) capacitor bank, 6) connection to PC with LabView program. In a text-file, the test conditions for all DUTs can be defined. All measurements where done with parameters according to table 1. After the first pulse, the current is incremented by 5 % until the DUT is destroyed. To avoid full destruction of the DUT, device failure is measured and ID is shutdown immediately. In this way burnmarks can be found, indicating where the device failure started. Note the only difference in parametrization for starting current ID for fully activated and Glin devices, respectively. To check if a device was heated up during the measurement, the bulk diode voltage VSD is measured and compared to value at test begin. If a difference is detected, the next pulse is delayed until the device cooled down. As one see in table 1, a manual delay was set. This manual delay was chosen after simulations showed that in case of thermal runaway, where hotspots have a temperature several hundred degrees hotter than the average, no thermal relaxation was achieved after only 500 ms at the desired biasing conditions. 24

30 Figure 20: Socket used for SOA measurements. 2.5 Detection of Solder Voids in X-ray Images using Matlab App Designer Figure 21 a) shows an X-ray image of a device with regular voids out of production. b) shows an X-ray image of a device with regular voids and an artificial void in the UL area. The copper clip can easily be recognized. As the solder contains lead, the two solder layers give a strong contrast. Figure 21: X-ray image of a MOSFET die and copper clip with a) regular voids and b) additional artificial void. The copper clip also gives a good contrast, due to its thickness, around ten 25

31 times thicker than the solder. All images have been taken with constant acceleration voltage of 85 kv and constant distance between X-ray source and device surface. Calculating the voided area in a 8 bit gray scale image can be achieved by binarizing the image using global threshold and counting all non zero elements. In a binarized image a pixel value of 0 corresponds to black and a value of 1 corresponds to white. To use a global threshold for binarizing the image a flat topology is needed. As there might be a gradient in the thickness of both solder layers resulting in a brightness gradient in the image, that needs to be removed, a structuring element is used [18]. This can be created with strel- function in MATLAB. As the strel- function is used on the original image, an new object is created, called background. The difference from image and background leaves a new image with a flattened topology. Using mat2gray restores full 8 bit gray scale. Now two binarized images can be created with two different global thresholds: One that includes all voids and another one that contains only the backside voids between leadframe and chip. This is possible because the gray value for backside voids is higher than for topside voids. The difference of both results in a binarized image that only contains topside voids. To reduce grain and artefacts at the edges of the voids, multiple median filtering was done. In the end, the voided area is calculated by counting all non-zero elements. As the X-ray images differ from chip to chip, this cannot be done with constant threshold parameters. Therefore a MATLAB app was created using App Designer, where the gray scale threshold values for all voids and the backside voids can be entered by hand, as well as the size of the structuring element. To make the void detection easier, only the image part with the clip containing the desired voids, is used for evaluation. Fig. 22 shows the void detection application with buttons to load a new image, binarize the image and calculate the void area in percentage to the overall image area. Also the strel - size can be entered, also as the threshold for all voids (Th all voids) and the threshold for the backside voids (Th backside). Arrow a) shows a backside void, being detected only in the backside void image but not in the final image. Arrow b) shows a another void, that is slightly darker and hence a topside void, that is contained in the final image only. The full source code for the void detection app can be found in appendix A. 26

32 Figure 22: Void Detection App created with MATLAB App Designer. Arrow a) indicates a backside void, only contained in the backside void image, arrow b) indicated a topside void only contained in the final image for area calculation. 27

33 3 Impact of Solder Voids on Safe Operating Area The following sections compare measurements and simulations results of devices with and without artificial voids (AVs). First fully activated devices will be discussed, followed by G lin devices. The lack of correlation between artificial and also regular void size and SOA will be shown. As the artificial void etch process attacked the source copper metallization, this effect will be simulated to show the impact of this systematic error. To protect intellectual property of Infineon Technologies AG, SOA measurements are normalized. Measurements are plotted as quantile-quantile plots. The dashed lines indicate a standard normal distributions as it would look like according to the data. Derivations from a straight line indicate the superposition of other normal distributed parameters. 3.1 Fully Activated Devices Experimental and Analytical Investigation A sample size of 25 pieces has been measured to get a distribution of devices without artificial voids. Note that those devices still contain voids up to 10 % from the soldering process. 40 samples (10 per AV position: UR, UL, Figure 23: Distribution of SOA measurements a) vs. standard normal quantiles b) vs. void size with and without AVs for fully activated devices. LL, LR) have been prepared and measured. After SOA measurement X-ray 28

34 images have been taken, the void size was determined and the burnmark location was checked after full removal of mold mass. Fig. 23 a) shows both distributions, regular devices and AV devices, respectively. Both distributions overlap and have a long tail on the right side and a short tail on the left side. This clearly shows that AVs do not impact SOA of fully activated devices. Also Fig. 23 b) shows that there is no correlation between (artificial) void size and SOA. The arrows indicate the strongest and the weakest devices with AV and the corresponding AV area. Both AVs have a size around 25 %. Burn marks only occurred in the hot spot areas, predicted by simulation. Also regular devices show the same behaviour. The best regular device has a regular void size of around 5 %. The same like the worst device. This all shows that there is no correlation between void size and SOA for fully activated devices Investigation by Electro-Thermal Simulation Fig. 24 shows the normalized power density and the surface temperature for a 100 µs rectangular power pulse on the left side of the TCP. For fully Figure 24: Simulated surface temperature for fully activated device without AV. Thermal runaway occurs at the hotspot positions. activated devices this power pulse leads to thermal runaway in cells with the highest thermal resistance R th and the lowest thermal capacitance C th resulting in hotspots several hundred degrees hotter than the average device. The positive temperature-current feedback leads to an extremely high power 29

35 Figure 25: Simulated surface temperature for fully activated device with AV. Thermal runaway occurs at the same location like without AV. density in the hotspot areas caused by the positive temperature coefficient of the parasitic npn-bipolar transistor. Below the copper clip, the MOSFET is well cooled, leading to a lower power density. If we compare this to a simulation with AV (Fig. 25), the overall result remains the same: Hotpots several hundred degrees hotter than the average MOSFET with extremely high power density in the hotspot locations. In the UL void area, that is around 25 % of the overall contact area, the temperature is increased due to missing cooling by the copper clip. But the void is not sufficient to cause thermal runaway within the void area, so that the hotspot locations stay the same. The results only slightly change for the other three AV locations. Burn mark locations where only found at the hotspot locations, predicted by simulation. 2/3 of all burnmarks (with and w/o AVs) occurred on the right side of the die, where the simulation shows the highest peak temperature Conclusion The experimental and simulation results clearly show that thermal runaway is crucial in fully activated devices for short pulses of around 100 µs. Depending on the chip layout, hotspots several hundred degrees hotter than the average device temperature form, possibly leading to device failure. Adding voids of up to 25 % of the copper clip contact area does not change the SOA measurement results, nor the distribution of burnmark locations. 30

36 Both measurements showed 2/3 of all burnmarks on three different hotspots on the right side, the other 1/3 occurred on the left side in the predicted hotspots. While the absolute SOA current could not be simulated with high accuracy (simulation always higher than measurements, see Sec. 2.3), the failure locations could be simulated very well possibly indicating a weakness. So for fully activated devices it was found, that voids up to a size of 25 % do not affect electro-thermal behaviour of the device. Device weaknesses due to design could be well predicted using Eltic, confirming the simulator and therefore saving costs and time in future design cycles. Nevertheless further investigations are needed to find the reasons for wide distributions in SOA of copper clip technology. 3.2 Partially Activated Devices Experimental and Analytical Investigation For investigation of G lin devices a sample size of 25 regular devices and 40 devices with the four different AV locations have been measured. Addition- Figure 26: Distribution of SOA measurements a) vs. standard normal quantiles b) vs. void size with and without AVs for G lin devices. ally 20 samples only opened by laser ablation (see Sec. 2.2) without any void etch, were measured to determine the influence of package opening on the electro-thermal behaviour. Fig. 26 a) shows all three measurements, while b) shows the corresponding void sizes. Devices only opened by laser ablation show a worsening of about 5 %, while devices with AVs are about 15 % worse in the median with some outliers overlapping with both regu- 31

37 lar and laser opened devices. Regular and laser opened devices are normal distributed, not so the AV devices. The distribution shows a long tail on the right side and a short tail on the left side indicating the overlap of various distributions and therefore hidden parameters. Again, there is no correlation again between SOA and void size leading to the conclusion that AVs are not the reason for electro-thermal weakening of the devices. It was found that burnmark locations for AV devices always occurred within the opened gap for void etching. As this could not be predicted by simulation (Sec ), it turned out, that the void etch process was not selective enough. Acetic acid and hydrogen peroxide in combination also attacked the copper metallization (Sec. 2.2), thinning it about 50 %. Fig. 27 shows a cross section next to the copper clip through an opening for void etch. This effect will be further investigated in the following section. Figure 27: Crossection through an opened gap for void etch. The void etching process also attacked the copper metallization and removed around 50 % of the layer thickness Investigation by Electro-Thermal Simulation Fig. 28 shows the power density distribution and the surface temperature of a regular G lin device. Below the copper clip, where the device is well cooled, increased power density can be observed. Hotspots are forming that are several ten degrees hotter than the surrounding area, but show no increased power density. Therefore the increased temperature results from high thermal resistance and low thermal capacitance in the appropriate areas, in- 32

38 Figure 28: Normalized power density and surface temperature distribution for a G lin device without AV. No thermal runaway occurs, but hotspot locations stay the same due to cells with highest R th and lowest C th. dicating layout weaknesses. This confirms the theoretical expectations of biasing the device on the right side of the TCP leading to self-regulation, but also increased temperature in thermally poorly connected areas. Adding an AV of 25 % in the UL position to the simulation, leads to increased temperature up to the average device temperature within the void area (Fig. 29). Hotspots stay at the same positions. For the other three AV positions, the simulations results stay the same. As the maximum simulated current does not change significantly, the measurement results of 15 % weakening of AV devices cannot be explained. As it has been shown in Fig. 27, the copper metallization thickness was locally reduced by approximately 50 % within the opening gap. Simulating this locally reduced copper thickness leads to a local temperature above the average device temperature with a small hotspot (Fig. 30) in the thinned copper area. This greatly matches the experimental results for burnmark locations. While burnmarks for regular devices only occurred in the predicted hotspot areas, the burnmarks for AV devices only occurred within the opening gaps. Combining both, void and thin copper below voids, lowers the simulated SOA by around 10 % which is in the order of the experimental results. 33

39 Figure 29: Normalized power density and surface temperature distribution for a G lin device with AV. Figure 30: Normalized power density and surface temperature distribution for a G lin device with locally thinned copper. A hotspot forms in the region where burnmarks were observed. 34