Enhancement and Technical Notes

Size: px
Start display at page:

Download "Enhancement and Technical Notes"

Transcription

1 BSIM4.4.0 Release Enhancement and Technical Notes BSIM group University of California, Berkeley BSIM4.4.0 March 004 1

2 OUTLINE New Features of BSIM4.4.0 release Trap-assisted tunneling and recombination current model Flatband voltage offset parameter for overlap gate overlap tunneling current Length reduction parameter offset for flicker ise Bug Fixes BSIM4.4.0 March 004

3 Source/Body, Drain/Body Junction Diode Model with Trap-Assisted-Tunneling Current in BSIM4 I bs,d = I sbs,d W P A + V effcj s,deff s,deff bs,d qvbs,d exp NJS, D k NF J J J G tssws,d tss,d min tsswgs,d B T 1 f breakdown Vbs,d VTSSWGS, D (T ) exp NJTSSWG(T ) Vtm0 VTSSWGS, D V Vbs,d VTSSWS, D (T ) exp NJTSSW(T ) Vtm0 VTSSWS, D V Vbs,d VTSS, D (T ) exp NJTS(T ) Vtm0 VTSS, D V bs,d 1 bs,d 1 bs,d 1 Vtm0 = k B TNOM q BSIM4.4.0 March 004 3

4 Proposed Temperature Model Eg(TNOM ) T J tsswgs,d (T ) = J tsswgs,d (TNOM ) exp X tsswgs, d 1 k BT TNOM Eg( TNOM ) T J tssws,d ( T ) = J tssws,d ( TNOM ) exp X tssws, d 1 k BT TNOM Eg(TNOM ) T J tss,d (T ) = J tss,d (TNOM ) exp X tss, d 1 k BT TNOM T NJTSSWG(T ) = NJTSSWG( TNOM ) 1 + TNJTSSWG 1 TNOM T NJTSSW( T ) = NJTSSW (TNOM ) 1 + TNJTSSW 1 TNOM T NJTS (T ) = NJTS (TNOM ) 1 + TNTJS 1 TNOM BSIM4.4.0 March 004 4

5 Proposed TAT Model New Parameters Parameter Name Description Default Value Binnable? Note JTSS, JTSD Bottom trap-assisted saturation current density JTSSWS, JTSSWD STI sidewall trap-assisted saturation current density JTSSWGS, JTSSWGD Gate-edge sidewall trap-assisted saturation current density NJTS Non-ideality factor for JTSS, JTSD NJTSSW Non-ideality factor for JTSSWS, JTSSWD NJTSSWG Non-ideality factor for JTSSWGS, JTSSWGD XTSS, XTSD Power dependence of JTSS, JTSD on temperature XTSSWS, XTSSWD Power dependence of JTSSWS, JTSSWD on temperature XTSSWGS, XTSSWGD Power dependence of JTSSWGS, JTSSWGD on temperature VTSS, VTSD Bottom trap-assisted voltage dependent parameter 1 VTSSWS, VTSSWD STI sidewall trap-assisted voltage dependent parameter 1 VTSSWGS, VTSSWGD Gate-edge sidewall trap-assisted voltage dependent parameter 1 TNJTS Temperature coefficient for NJTS TNJTSSW Temperature coefficient for NJTSSW TNJTSSWG Temperature coefficient for NJTSSWG BSIM4.4.0 March 004 5

6 Simulation Results (TI) 1E-5 48X196X1 1E-4 1E-7 1E-6 48X196X1 I DIODE 1E-9 I DIODE 1E-8 1E-11 1E-13 N+/P GEDL with temperature (NMOS) simulation Temp=r.t. Temp=150C Temp=-55C E-10 1E-1 P+/N GEDL with temperature (PMOS) simulation Temp=r.t. Temp=150C Temp=-55C V B V B BSIM4.4.0 March 004 6

7 Simulation Results (TI) 1E-3 1E-4 1E-6 NMOS STI sidewall RT T=150C simulation T=150C 1E-4 1E-5 1E-6 1E-7 PMOS STI sidewall RM 150C simulation I DIODE 1E-8 1E-10 RT I DIODE (A) 1E-8 1E-9 1E-10 1E-11 T=150C RT 1E-1 1E-1 1E-13 1E E V B (V) VB(V) BSIM4.4.0 March 004 7

8 Simulation Results (Renesas) 0.1 1E-3 1E um Sidewall 5C 85C 15C I jsidewall 1E-7 1E-9 1E-11 1E Vj(V) BSIM4.4.0 March 004 8

9 Simulation Results (Renesas) 1E um Sidewall 5C 85C 15C 1E-7 I jsidewall /µm 1E-9 1E-11 1E Vj(V) BSIM4.4.0 March 004 9

10 Simulation Results (Renesas) um Junction Bottom 15C 85C 5C 0.1 /µm 1E-3 jbottom I 1E-5 1E-7 1E Vj(V) BSIM4.4.0 March

11 Simulation Results (Renesas) um Junction Bottom 15C 85C simulation I jbottom /µm 0.1 1E-3 1E Vj(V) BSIM4.4.0 March

12 Flatband Voltage Offset Parameter for Gate Overlap Tunneling Current VFBSDOFF an offset voltage added to the original source/drain flatband voltage which allows independently setting of V fbsd, to model gate overlap tunneling current accurately. V fbsd = k B T /q log(ngate/nsd) + VFBSDOFF Parameter Name Description Default Value Binnable? Note VFBSDOFF Flatband Voltage Offset Parameter yes BSIM4.4.0 March 004 1

13 Length Reduction Parameter Offset for Flicker Noise LINTNOI an offset to length reduction parameter(lint) for flicker ise For fimod = 1 (unified model) In the inversion region, the ise density is expressed as: S id,inv ( f ) = + W C eff oxe ( L ( L eff eff k B k TI B Tq ds m L eff + LINTNOI ) clm + LINTNOI ) I ds A f bulk ef f ef N NOIA log N NOIA + NOIB N 0 * ( N + N ) l l l + N + N * * + NOIC N + NOIB l NOIC ( N N ) + ( N N ) 0 l 0 l Parameter Name Description Default Value Binnable? Note LINTNOI Length Reduction Parameter Offset BSIM4.4.0 March

APPENDIX A: Parameter List

APPENDIX A: Parameter List APPENDIX A: Parameter List A.1 BSIM3v3 Model Control Parameters none level BSIMv3 model selector 8 none Mobmod mobmod Mobility model selector 1 none Capmod capmod Flag for the short channel 2 none capacitance

More information

BSIM4.3.0 Model. Enhancements and Improvements Relative to BSIM4.2.1

BSIM4.3.0 Model. Enhancements and Improvements Relative to BSIM4.2.1 BSIM4.3.0 Model Enhancements and Improvements Relative to BSIM4.. Xuemei (Jane) Xi, Jin He, Mohan Dunga, Ali Niknejad, Chenming Hu University of California, Berkeley OUTLINE New Features of BSIM4.3.0 beta

More information

APPENDIX A: Parameter List

APPENDIX A: Parameter List APPENDIX A: Parameter List A.1 BSIM3v3 Model Control Parameters none level BSIMv3 model selector 8 none Mobmod mobmod Mobility model selector 1 none Capmod capmod Flag for the short channel 1 none capacitance

More information

APPENDIX D: Binning BSIM3v3 Parameters

APPENDIX D: Binning BSIM3v3 Parameters APPENDIX D: Binning BSIM3v3 Parameters Below is a list of all BSIM3v3 model parameters which can or cannot be binned. All model parameters which can be binned follow the following implementation: P L P

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM

More information

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 116 Lecture #3: CMOS Inverters MOS Scaling Rajeevan Amirtharajah University of California, Davis Jeff Parhurst Intel Corporation Outline Review: Inverter Transfer Characteristics Lecture 3: Noise Margins,

More information

APPENDIX D: Model Parameter Binning

APPENDIX D: Model Parameter Binning APPENDIX D: Model Parameter Binning Below is the information on parameter binning regarding which model parameters can or cannot be binned. All those parameters which can be binned follow this implementation:

More information

The Devices. Devices

The Devices. Devices The The MOS Transistor Gate Oxyde Gate Source n+ Polysilicon Drain n+ Field-Oxyde (SiO 2 ) p-substrate p+ stopper Bulk Contact CROSS-SECTION of NMOS Transistor Cross-Section of CMOS Technology MOS transistors

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET Calculation of t and Important 2 nd Order Effects SmallSignal Signal MOSFET Model Summary Material from: CMOS LSI Design By Weste

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

The Devices. Jan M. Rabaey

The Devices. Jan M. Rabaey The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models

More information

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation EEC 118 Lecture #2: MOSFET Structure and Basic Operation Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation Announcements Lab 1 this week, report due next week Bring

More information

Lecture 3: CMOS Transistor Theory

Lecture 3: CMOS Transistor Theory Lecture 3: CMOS Transistor Theory Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V Characteristics Gate and Diffusion Capacitance 2 Introduction So far, we have treated transistors

More information

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components

Objective and Outline. Acknowledgement. Objective: Power Components. Outline: 1) Acknowledgements. Section 4: Power Components Objective: Power Components Outline: 1) Acknowledgements 2) Objective and Outline 1 Acknowledgement This lecture note has been obtained from similar courses all over the world. I wish to thank all the

More information

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing EE115C Winter 2017 Digital Electronic Circuits Lecture 3: MOS RC Model, CMOS Manufacturing Agenda MOS Transistor: RC Model (pp. 104-113) S R on D CMOS Manufacturing Process (pp. 36-46) S S C GS G G C GD

More information

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L2: MOS Models-2 (1 st Aug. 2013) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L: MOS Models- (1 st Aug. 013) B. Mazhari Dept. of EE, IIT Kanpur 3 NMOS Models MOS MODEL Above Threshold Subthreshold ( GS > TN ) ( GS < TN ) Saturation ti Ti Triode ( DS >

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 6: January 30, 2018 MOS Operating Regions, pt. 2 Lecture Outline! Operating Regions (review) " Subthreshold " Resistive " Saturation! Intro.

More information

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA University of Pennsylvania Department of Electrical Engineering ESE 570 Midterm Exam March 4, 03 FORMULAS AND DATA. PHYSICAL CONSTANTS: n i = intrinsic concentration undoped) silicon =.45 x 0 0 cm -3 @

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

ECE321 Electronics I

ECE321 Electronics I EE31 Electronics I Lecture 8: MOSET Threshold Voltage and Parasitic apacitances Payman Zarkesh-Ha Office: EE Bldg. 3B Office hours: Tuesday :-3:PM or by appointment E-mail: payman@ece.unm.edu Slide: 1

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

The PSP compact MOSFET model An update

The PSP compact MOSFET model An update The PSP compact MOSFET model An update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen NXP Semiconductors Ronald van Langevelde Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha,

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS

Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS Modeling Overview Strain Effects Thermal Modeling TCAD Modeling Outline FLOOPS / FLOODS Introduction Progress on GaN Devices Prospects for Reliability

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

VLSI Design The MOS Transistor

VLSI Design The MOS Transistor VLSI Design The MOS Transistor Frank Sill Torres Universidade Federal de Minas Gerais (UFMG), Brazil VLSI Design: CMOS Technology 1 Outline Introduction MOS Capacitor nmos I-V Characteristics pmos I-V

More information

Nanoscale CMOS Design Issues

Nanoscale CMOS Design Issues Nanoscale CMOS Design Issues Jaydeep P. Kulkarni Assistant Professor, ECE Department The University of Texas at Austin jaydeep@austin.utexas.edu Fall, 2017, VLSI-1 Class Transistor I-V Review Agenda Non-ideal

More information

Chapter 5: BSIM3v3 Characterization

Chapter 5: BSIM3v3 Characterization 5: BSIM3v3 Characterization The BSIM3 model (BSIM = Berkeley Short channel Insulated gate field effect transistor Model) was published by the University of California at Berkeley in July 1993. BSIM3 is

More information

A Multi-Gate CMOS Compact Model BSIMMG

A Multi-Gate CMOS Compact Model BSIMMG A Multi-Gate CMOS Compact Model BSIMMG Darsen Lu, Sriramkumar Venugopalan, Tanvir Morshed, Yogesh Singh Chauhan, Chung-Hsun Lin, Mohan Dunga, Ali Niknejad and Chenming Hu University of California, Berkeley

More information

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling ELEC 3908, Physical Electronics, Lecture 26 MOSFET Small Signal Modelling Lecture Outline MOSFET small signal behavior will be considered in the same way as for the diode and BJT Capacitances will be considered

More information

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS ) ECE 4420 Spring 2005 Page 1 FINAL EXAMINATION NAME SCORE /100 Problem 1O 2 3 4 5 6 7 Sum Points INSTRUCTIONS: This exam is closed book. You are permitted four sheets of notes (three of which are your sheets

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

Diode_CMC model. Klaus-Willi Pieper, Infineon Technologies AG 2015, Nov 6 th

Diode_CMC model. Klaus-Willi Pieper, Infineon Technologies AG 2015, Nov 6 th Diode_CMC model Klaus-Willi Pieper, Infineon Technologies AG 2015, Nov 6 th Agenda Introduction Features of diode models Application of JUNCAP2 and Diode_CMC Scaling of JUNCAP2 and Diode_CMC High injection

More information

Chapter 3-7. An Exercise. Problem 1. Digital IC-Design. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D

Chapter 3-7. An Exercise. Problem 1. Digital IC-Design. Problem. Problem. 1, draw the static transistor schematic for the function Q = (A+BC)D igital I-esign Problem Parameters rom a.35 um process hapter 3-7 n Exercise, draw the static transistor schematic or the unction (+), ind the corresponding domino gate using a PN net 3, ind the Euler path

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

! MOS Capacitances.  Extrinsic.  Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February, 07 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance Model!

More information

CHAPTER 3 - CMOS MODELS

CHAPTER 3 - CMOS MODELS CMOS Analog Circuit Design Page 3.-1 CHAPTER 3 - CMOS MODELS Chapter Outline 3.1 MOS Structure and Operation 3.2 Large signal MOS models suitable for hand calculations 3.3 Extensions of the large signal

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2

More information

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations

MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations ROMANIAN JOURNAL OF INFORMATION SCIENCE AND TECHNOLOGY Volume 10, Number 2, 2007, 189 197 MOSFET Model with Simple Extraction Procedures, Suitable for Sensitive Analog Simulations S. EFTIMIE 1, ALEX. RUSU

More information

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits EE105 - Fall 005 Microelectronic Devices and Circuits ecture 7 MOS Transistor Announcements Homework 3, due today Homework 4 due next week ab this week Reading: Chapter 4 1 ecture Material ast lecture

More information

Classification of Solids

Classification of Solids Classification of Solids Classification by conductivity, which is related to the band structure: (Filled bands are shown dark; D(E) = Density of states) Class Electron Density Density of States D(E) Examples

More information

Physical resistor model n subtype

Physical resistor model n subtype Physical resistor model n subtype ResistorPhyN Terminal0 Terminal1 Terminal2 Description: This element implements a semiconductor resistor based on the n subtype of the Cadence physical resistor model.

More information

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling?

LECTURE 3 MOSFETS II. MOS SCALING What is Scaling? LECTURE 3 MOSFETS II Lecture 3 Goals* * Understand constant field and constant voltage scaling and their effects. Understand small geometry effects for MOS transistors and their implications modeling and

More information

The Intrinsic Silicon

The Intrinsic Silicon The Intrinsic ilicon Thermally generated electrons and holes Carrier concentration p i =n i ni=1.45x10 10 cm-3 @ room temp Generally: n i = 3.1X10 16 T 3/2 e -1.21/2KT cm -3 T= temperature in K o (egrees

More information

MOS Device Modeling. C.K. Ken Yang UCLA Courtesy of Agilent eesoft EE 215B

MOS Device Modeling. C.K. Ken Yang UCLA Courtesy of Agilent eesoft EE 215B MOS Device Modeling C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of Agilent eesoft 1 Overview Reading Rabaey 3.3 W&H 2.2-2.4 Overview This class will look at the iv and CV characteristics of an MOS device

More information

LEVEL 61 RPI a-si TFT Model

LEVEL 61 RPI a-si TFT Model LEVEL 61 RPI a-si TFT Model Star-Hspice LEVEL 61 is an AIM-SPICE MOS15 amorphous silicon (a-si) thin-film transistor (TFT) model. Model Features AIM-SPICE MOS15 a-si TFT model features include: Modified

More information

Non Ideal Transistor Behavior

Non Ideal Transistor Behavior Non Ideal Transistor Behavior Slides adapted from: N. Weste, D. Harris, CMOS VLSI Design, Addison- Wesley, 3/e, 2004 1 Non-ideal Transistor I-V effects Non ideal transistor Behavior Channel Length ModulaJon

More information

in Electronic Devices and Circuits

in Electronic Devices and Circuits in Electronic Devices and Circuits Noise is any unwanted excitation of a circuit, any input that is not an information-bearing signal. Noise comes from External sources: Unintended coupling with other

More information

The Devices: MOS Transistors

The Devices: MOS Transistors The Devices: MOS Transistors References: Semiconductor Device Fundamentals, R. F. Pierret, Addison-Wesley Digital Integrated Circuits: A Design Perspective, J. Rabaey et.al. Prentice Hall NMOS Transistor

More information

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

Scaling Issues in Planar FET: Dual Gate FET and FinFETs Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar

More information

Electronic Circuits for Mechatronics ELCT 609 Lecture 2: PN Junctions (1)

Electronic Circuits for Mechatronics ELCT 609 Lecture 2: PN Junctions (1) Electronic Circuits for Mechatronics ELCT 609 Lecture 2: PN Junctions (1) Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 Electronic (Semiconductor) Devices P-N Junctions (Diodes): Physical

More information

ECE 497 JS Lecture - 12 Device Technologies

ECE 497 JS Lecture - 12 Device Technologies ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density

More information

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline Introduction to MOS VLSI Design hapter : MOS Transistor Theory copyright@david Harris, 004 Updated by Li hen, 010 Outline Introduction MOS apacitor nmos IV haracteristics pmos IV haracteristics Gate and

More information

N Channel MOSFET level 3

N Channel MOSFET level 3 N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate

More information

Tunnel-FET: bridging the gap between prediction and experiment through calibration

Tunnel-FET: bridging the gap between prediction and experiment through calibration Tunnel-FET: bridging the gap between prediction and experiment through calibration Anne Verhulst Quentin Smets, Jasper Bizindavyi, Mazhar Mohammed, Devin Verreck, Salim El Kazzi, Alireza Alian, Yves Mols,

More information

BSIM6.0 MOSFET Compact Model

BSIM6.0 MOSFET Compact Model BSIM6.0 MOSFET Compact Model Technical Manual Authors: Yogesh Singh Chauhan, Mohammed A. Karim, Sriramkumar Venugopalan, Harshit Agarwal, Pankaj Thakur, Navid Paydavosi, Ali Niknejad, and Chenming Hu Project

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 7: February 4, 2016 MOS SPICE Models, MOS Parasitic Details Lecture Outline! MOS Capacitances " Extrinsic " Intrinsic! Lumped Capacitance

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM Department of Electrical and Computer Engineering, Cornell University ECE 3150: Microelectronics Spring 2018 Homework 4 Due on March 01, 2018 at 7:00 PM Suggested Readings: a) Lecture notes Important Note:

More information

Ideal Diode Equation II + Intro to Solar Cells

Ideal Diode Equation II + Intro to Solar Cells ECE-35: Spring 15 Ideal Diode Equation II + Intro to Solar Cells Professor Mark Lundstrom Electrical and Computer Engineering Purdue University, West Lafayette, IN USA lundstro@purdue.edu Pierret, Semiconductor

More information

The HV-EKV MOSFET Model

The HV-EKV MOSFET Model The HV-EKV MOSFET Model Ecole Polytechnique Fédérale de Lausanne (EPFL), Switzerland EPFL Team Yogesh Singh Chauhan, Costin Anghel, Francois Krummenacher, Adrian Mihai Ionescu and Michel Declercq CMC Meeting,

More information

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models

Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Lecture 10 MOSFET (III) MOSFET Equivalent Circuit Models Outline Lowfrequency smallsignal equivalent circuit model Highfrequency smallsignal equivalent circuit model Reading Assignment: Howe and Sodini;

More information

DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction

DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction DKDT: A Performance Aware Dual Dielectric Assignment for Tunneling Current Reduction Saraju P. Mohanty Dept of Computer Science and Engineering University of North Texas smohanty@cs.unt.edu http://www.cs.unt.edu/~smohanty/

More information

MOSFET Capacitance Model

MOSFET Capacitance Model MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 5: January 25, 2018 MOS Operating Regions, pt. 1 Lecture Outline! 3 Regions of operation for MOSFET " Subthreshold " Linear " Saturation!

More information

8. Schottky contacts / JFETs

8. Schottky contacts / JFETs Technische Universität Graz Institute of Solid State Physics 8. Schottky contacts / JFETs Nov. 21, 2018 Technische Universität Graz Institute of Solid State Physics metal - semiconductor contacts Photoelectric

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

Using MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B

Using MOS Models. C.K. Ken Yang UCLA Courtesy of MAH EE 215B Using MOS Models C.K. Ken Yang UCLA yangck@ucla.edu Courtesy of MAH 1 Overview Reading Rabaey 5.4 W&H 4.2 Background In the past two lectures we have reviewed the iv and CV curves for MOS devices, both

More information

BSIM-CMG Model. Berkeley Common-Gate Multi-Gate MOSFET Model

BSIM-CMG Model. Berkeley Common-Gate Multi-Gate MOSFET Model BSIM-CMG Model Why BSIM-CMG Model When we reach the end of the technology roadmap for the classical CMOS, multigate (MG) CMOS structures will likely take up the baton. Numerous efforts are underway to

More information

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors CMOS Devices PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors PN Junctions Diffusion causes depletion region D.R. is insulator and establishes barrier

More information

Integrated Circuits & Systems

Integrated Circuits & Systems Federal University of Santa Catarina Center for Technology Computer Science & Electronics Engineering Integrated Circuits & Systems INE 5442 Lecture 10 MOSFET part 1 guntzel@inf.ufsc.br ual-well Trench-Isolated

More information

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis.

B.Supmonchai June 26, q Introduction of device basic equations. q Introduction of models for manual analysis. June 26, 2004 oal of this chapter Chapter 2 MO Transistor Theory oonchuay upmonchai Integrated esign Application Research (IAR) Laboratory June 16th, 2004; Revised June 16th, 2005 q Present intuitive understanding

More information

Schottky diodes. JFETs - MESFETs - MODFETs

Schottky diodes. JFETs - MESFETs - MODFETs Technische Universität Graz Institute of Solid State Physics Schottky diodes JFETs - MESFETs - MODFETs Quasi Fermi level When the charge carriers are not in equilibrium the Fermi energy can be different

More information

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania

EE 560 MOS TRANSISTOR THEORY PART 2. Kenneth R. Laker, University of Pennsylvania 1 EE 560 MOS TRANSISTOR THEORY PART nmos TRANSISTOR IN LINEAR REGION V S = 0 V G > V T0 channel SiO V D = small 4 C GC C BC substrate depletion region or bulk B p nmos TRANSISTOR AT EDGE OF SATURATION

More information

Avalanche breakdown. Impact ionization causes an avalanche of current. Occurs at low doping

Avalanche breakdown. Impact ionization causes an avalanche of current. Occurs at low doping Avalanche breakdown Impact ionization causes an avalanche of current Occurs at low doping Zener tunneling Electrons tunnel from valence band to conduction band Occurs at high doping Tunneling wave decays

More information

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003

Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model. April 8, 2003 6.012 - Microelectronic Devices and Circuits - Spring 2003 Lecture 16-1 Lecture 16 - The pn Junction Diode (II) Equivalent Circuit Model April 8, 2003 Contents: 1. I-V characteristics (cont.) 2. Small-signal

More information

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number

Circuits. L5: Fabrication and Layout -2 ( ) B. Mazhari Dept. of EE, IIT Kanpur. B. Mazhari, IITK. G-Number EE610: CMOS Analog Circuits L5: Fabrication and Layout -2 (12.8.2013) B. Mazhari Dept. of EE, IIT Kanpur 44 Passive Components: Resistor Besides MOS transistors, sometimes one requires to implement passive

More information

Lecture 12: MOS Capacitors, transistors. Context

Lecture 12: MOS Capacitors, transistors. Context Lecture 12: MOS Capacitors, transistors Context In the last lecture, we discussed PN diodes, and the depletion layer into semiconductor surfaces. Small signal models In this lecture, we will apply those

More information

BSIM4.6.4 MOSFET Model

BSIM4.6.4 MOSFET Model BSIM4.6.4 MOSFET Model -User s Manual Tanvir Hasan Morshed, Wenwei (Morgan) Yang, Mohan V. Dunga, Xuemei (Jane) Xi, Jin He, Weidong Liu, Kanyu, M. Cao, Xiaodong Jin, Jeff J. Ou, Mansun Chan, Ali M. Niknejad,

More information

Lecture 2. Introduction to semiconductors Structures and characteristics in semiconductors

Lecture 2. Introduction to semiconductors Structures and characteristics in semiconductors Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

MOS Transistor Properties Review

MOS Transistor Properties Review MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO

More information

Robert W. Brodersen EECS140 Analog Circuit Design

Robert W. Brodersen EECS140 Analog Circuit Design INTRODUCTION University of California Berkeley College of Engineering Department of Electrical Engineering and Computer Science Robert. Brodersen EECS40 Analog Circuit Design ROBERT. BRODERSEN LECTURE

More information

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.)

Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Lecture 9 MOSFET(II) MOSFET I V CHARACTERISTICS(contd.) Outline 1. The saturation region 2. Backgate characteristics Reading Assignment: Howe and Sodini, Chapter 4, Section 4.4 6.012 Spring 2009 Lecture

More information

Quantum and Non-local Transport Models in Crosslight Device Simulators. Copyright 2008 Crosslight Software Inc.

Quantum and Non-local Transport Models in Crosslight Device Simulators. Copyright 2008 Crosslight Software Inc. Quantum and Non-local Transport Models in Crosslight Device Simulators Copyright 2008 Crosslight Software Inc. 1 Introduction Quantization effects Content Self-consistent charge-potential profile. Space

More information

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson

Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics. Lena Peterson Lecture 13 MOSFET as an amplifier with an introduction to MOSFET small-signal model and small-signal schematics Lena Peterson 2015-10-13 Outline (1) Why is the CMOS inverter gain not infinite? Large-signal

More information

NMOS (N-Channel Metal Oxide Semiconductor) Transistor. NMOS Transistor in Equilibrium

NMOS (N-Channel Metal Oxide Semiconductor) Transistor. NMOS Transistor in Equilibrium NMOS (N-Cannel Metal Oxide Semiconductor) Transistor e e e oxide insulator e e e NMOS Transistor in Equilibrium oxide insulator Wen te transistor is left alone, some electrons from te wells diffuse into

More information

Long-channel MOSFET IV Corrections

Long-channel MOSFET IV Corrections Long-channel MOSFET IV orrections Three MITs of the Day The body ect and its influence on long-channel V th. Long-channel subthreshold conduction and control (subthreshold slope S) Scattering components

More information

Electronic Circuits Laboratory EE462G Lab #2

Electronic Circuits Laboratory EE462G Lab #2 Electronic Circuits Laboratory EE46G Lab # Characterizing Nonlinear Elements, Curve Tracers, Transfer Characteristics, Curve Fit Programs Original slides prepared by Kevin D. Donohue (Spring 007) Modified

More information

Transistor Noise Lecture 14, High Speed Devices

Transistor Noise Lecture 14, High Speed Devices Transistor Noise 016-03-03 Lecture 14, High Speed Devices 016 1 Transistor Noise A very brief introduction 016-03-0 Lecture 13, High Speed Devices 016 Summary hybrid p Noise is a randomly varying voltage/current

More information

Preliminary measurements of charge collection and DLTS analysis of p + /n junction SiC detectors and simulations of Schottky diodes

Preliminary measurements of charge collection and DLTS analysis of p + /n junction SiC detectors and simulations of Schottky diodes Preliminary measurements of charge collection and DLTS analysis of p + /n junction SiC detectors and simulations of Schottky diodes F.Moscatelli, A.Scorzoni, A.Poggi, R.Nipoti DIEI and INFN Perugia and

More information

Nanometer Transistors and Their Models. Jan M. Rabaey

Nanometer Transistors and Their Models. Jan M. Rabaey Nanometer Transistors and Their Models Jan M. Rabaey Chapter Outline Nanometer transistor behavior and models Sub-threshold currents and leakage Variability Device and technology innovations Nanometer

More information