Latch versus Register
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1 Latch versus Register 1 Latch (trasparente su CK=0) stores data when clock is low Clk Q Register stores data when clock rises Clk Q Clk Q Clk Q 1 Elenco registri 2 statico master-slave 1 statico master-slave 2 per i registri statici è necessario generare le due fasi del clock e osservarle in simulazione dinamico master-slave PC2MOS-NC2MOS dinamico master-slave SPLITp-SPLITn progettare in modo gerarchico in modo da fornire I latch come celle di libreria dinamico TSPC con stadio di uscita TSPC1 con stadio di uscita TSPC2 2
2 Master-Slave (Edge-Triggered) Register 3 Master Slave CLK 1 0 Q M 0 1 Q Q M Q CLK CLK Two opposite latches trigger on edge Also called master-slave latch pair 3 Latch statico trasparente durante la fase bassa del clock 4 4
3 Static Register design 5 input data NOT on an high impedance node two clock phases: avoiding clock overlap 5 Registro statico master-slave slave
4 Typical standard cell static register7 Inv1 Inv2 TG1 Inv4 Inv6 Inv3 Inv5 Inv7 Inv8 φ and φ Q and Q locally generated buffered 7 Registro statico master-slave slave
5 Clock F and φ generation 9 9 Latch dinamico trasparente durante la fase alta del clock 10 CK Inv1 TG1 1 S M Cin,2 Inv2 Q M CK Memory = Cin,2 CK= Vdd, CK = 0 latch trasparente CK = 0, CK = Vdd latch in memorizzazione 10
6 ynamic master slave register 11 CK CK Inv1 TG1 1 S M Cin,2 Inv2 Q M Inv3 TG1 2 S M2 Cin,4 Inv4 Q CK CK two clock phases: avoiding clock overlap 11 Single phase dynamic latch pc2mos trasparente F =
7 Single phase dynamic latch SPLITp trasparente F =0 13 V A1,min = -Vtp 13 Single phase dynamic latch nc2mos trasparente F =Vdd 14 14
8 Registro dinamico master-slave slave PC2MOS NC2MOS Single phase dynamic latch SPLITn trasparente F =Vdd 16 V B2,max = Vdd -Vtn 16
9 Registro dinamico master-slave slave SPLITp-SPLITn SPLITn memorizzazione C Q Registro dinamico TSPC
10 Register Parameters Q Setup e hold sono calcolati rispetto al fronte di campionamento 19 Clk Clk T t hold t su Q t c-q elays can be different for rising and falling data transitions 19 Maximum Clock Frequency 20 CLK In R Combinational 1 R Logic 2 X Y Out t clk,q + t p,rc > t hold t clk-q + t p,rc + t setup T ck 20
11 Setup/Hold Illustrations (dynamic latch) 21 CN Inv1 TG1 1 S M Cin,2 Inv2 Q M CP Memory = Cin,2 CN= Vdd, CP = 0 latch trasparente CN = 0, CP = Vdd latch in memorizzazione 21 Setup Illustrations (dynamic latch) 22 Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP T Clk-Q ata Clock T Setup-1 T Setup-1 t=0 22
12 Setup Illustrations 23 Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP T Clk-Q ata Clock T Setup-1 T Setup-1 t=0 23 Setup Illustrations 24 Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP T Clk-Q ata Clock T Setup-1 T Setup-1 t=0 24
13 Setup Illustrations 25 Circuit before clock arrival (Setup-1 case) CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 T Clk-Q CP ata Clock T Setup-1 T Setup-1 t=0 25 Hold Illustrations 26 Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP 0 T Clk-Q Clock ata T Hold-1 T Hold-1 t=0 26
14 Hold Illustrations 27 Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP 0 T Clk-Q Clock ata T Hold-1 T Hold-1 t=0 27 Hold Illustrations 28 Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 CP 0 T Clk-Q Clock ata T Hold-1 T Hold-1 t=0 28
15 Hold Illustrations 29 Hold-1 case CN TG1 1 S M Inv2 Q M Clk-Q elay Inv1 T Clk-Q CP 0 Clock T Hold-1 ata T Hold-1 t= Es: 1 Registro dinamico master-slave slave PC2MOS-NC2MOS Tsu, =L Tsu =H 30
16 Registro dinamico master-slave slave 1 memorizzazione C Q1 Q1 Thold =L se =H dopo la commutazione del CK, per non avere errrore M2 deve essere OFF Thold =H se =L dopo la commutazione del CL, per non avere errore M1 deve essere OFF 31 M1 M2 31 Registro dinamico master-slave slave 1 memorizzazione C Q1 TCKQ,HL TCKQ,LH 32 32
17 Es. 2:Registro statico master-slave slave 1 memorizzazione: bistabile Tsu Registro statico master-slave slave 1 34 Thold 34
18 Registro statico master-slave slave 1 35 T CK,Q Es: 3 Registro dinamico master-slave slave SPLITp-SPLITn SPLITn memorizzazione C Q1 MN 76 36
19 Es. 4: Registro dinamico TSPC memorizzazione C O1 37 single PC2MOS Latch ntspc1 O2 O1 37 Latch TSPC1 a precarica durante F = 0 (memorizzazione) F = 0 primo stadio in precarica, uscita in alta impedenza F = Vdd primo stadio in valutazione, uscita segue l ingresso l unica transizione ammessa all ingresso è L-H 38 38
20 Registro dinamico TSPC memorizzazione C O1 Tsu ato = L carica O1 Tsu ato =H scarica O1 (e verificare che la durata della fase bassa del clock assicuri la precarica di O2 ) 39 O2 O1 39 Registro dinamico TSPC memorizzazione C q1 Thold ato =H carica O1 interrotta da M1 Thold ato =L la tensione sul nodo O1 deve rimanere costante durante il transitorio di scarica di O2 40 M1 O1 O2 40
21 Registro dinamico TSPC memorizzazione C q1 TCKQ,LH scarica O2, carica Q0 TCKQ,HL scarica Q0 (O2 è già al valore di precarica) 41 O2 M1 O1 41 Alternativa: stadio di uscita con latch TSPC2 42 IMP: osservare l andamento dei nodi interni! V z V Y V out V n V X 42
22 area Esempio di caratterizzazione 43 potenza statica (pw) CMOS 0.13um segnale di clock: Cin (pf) durata minima delle fasi alta e bassa del clock (ns) Energia associata alle transizioni del clock per differenti valori di Q e (pj) 43 segnale di dato: Cin (pf) 44 Energia associata alle transizioni del dato per differenti valori di Q e del clock (pj) hold time in funzione della durata della transizione del segnale di clock (ns) setup time in funzione della durata della transizione del segnale di clock (ns) 44
23 45 T P,CKQ e T slope,out in funzione della capacità di carico e della durata della transizione del segnale di clock 45 Esercitazione: progetto e caratterizzazione di registri 46 46
24 Convenzioni Convenzioni 48 per calcolare setup e hold è necessario osservare in simulazione alcuni nodi interni 48
25 Convenzioni
26 51 51 One-phase logic (F Section) 52 52
27 Latch TSPC2 a precarica durante F = 0 (memorizzazione) One-phase Logic (F( Section) 54 54
28 Latch TSPC2 a precarica durante F = Vdd (memorizzazione) 55 55
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