ICSSSTUB32871A. 27-Bit Registered Buffer for DDR2. Integrated Circuit Systems, Inc. Pin Configuration. 96 Ball BGA (Top View)

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1 Integrated Circuit Systems, Inc. ICSSSTUB32871A 27-Bit Registered Buffer for R2 Recommended Application: R2 Memory Modules Provides complete R IMM solution with ICS98ULPA877A, ICS97ULP877, or ITCSPUA877A Optimized for R2 400/533/667 JEEC 4 Rank VLP IMMS Product Features: 27-bit 1:1 registered buffer with parity check functionality Supports SSTL_18 JEEC specification on data inputs and outputs Supports LVCMOS switching levels on RESET input 50% more dynamic driver strength than standard SSTU32864 Low voltage operation V = 1.7V to 1.9V Available in 96 BGA package Pin Configuration A B C E F G H J K L M N P R T 96 Ball BGA (Top View) Functionality Truth Table Inputs Outputs RESET CS0 CS1 CSGate Enable n, OTn, En Qn QCS QOT, QE H L L X L L L L H L L X H H L H H L L X L or H L or H X Q 0 Q 0 Q 0 H L H X L L L L H L H X H H L H H L H X L or H L or H X Q 0 Q 0 Q 0 H H L X L L H L H H L X H H H H H H L X L or H L or H X Q 0 Q 0 Q 0 H H H L L L H L H H H L H H H H H H H L L or H L or H X Q 0 Q 0 Q 0 H H H H L Q 0 H L H H H H H Q 0 H H H H H H L or H L or H X Q 0 Q 0 Q 0 L L L L

2 Ball Assignments 27 bit 1:1 Register A E0 0 V REF V QE0 QE1 B E1 1 GN GN Q0 Q1 C 2 OT1 V V Q2 NU OT0 PTYERR GN GN QOT0 QOT1 E 3 4 V V Q3 Q4 F 5 6 GN GN Q5 Q6 G PAR_IN RESET V V NC NC H CS0 GN GN QCS0 QCS1 J CS1 V V NC NC K 7 8 GN GN Q7 Q8 L 9 10 V V Q9 Q10 M GN GN Q11 Q12 N V V Q13 Q14 P GN GN Q15 Q16 R V V Q17 Q18 T CSGateEN V Q19 Q

3 General escription This 27-bit 1:1 registered buffer with parity is designed for 1.7V to 1.9V V operation. All clock and data inputs are compatible with the JEEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the R2 IMM load. The ICSSSTUB32871A operates from a differential clock ( and ). ata are registered at the crossing of going high, and going low. The device supports low-power standby operation. When the reset input (RESET) is low, the differential input receivers are disabled, and undriven () data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is low all registers are reset, and all outputs except PTYERR are forced low. The LVCMOS RESET input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. In the R2 RIMM application, RESET is specified to be completely asynchronous with respect to and. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the ICSSSTUB32871A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both CS0 and CS1 inputs and will gate the Qn outputs from changing states when both CS0 and CS1 are high. If either CS0 or CS1 input is low, the Qn outputs will function normally. The RESET input has priority over the CS0 and CS1 control and will force the Qn outputs low and the PTYERR output high. If the CS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for CS would be the same as for the other data inputs. The ICSSSTU32871A includes a parity checking function. The ICSSSTUB32871A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the -inputs and indicates whether a parity error has occurred on its open-drain PTYERR pin (active LOW). Package options include 96-ball Thin Profile Fine Pitch BGA (TFBGA, MO-TB). Inputs Output RESET CS0 CS1 of inputs = H (0-21) PARIN* PTYERR** H L H Even L H H L H Odd L L H L H Even H L H L H Odd H H H H L Even L H H H L Odd L L H H L Even H L H H L Odd H H H H H X X PTYERR 0 H X X L or H L or H X X L * PARIN arrives one clock cycle after the data to which it applies. PTYERR 0 ** This transition assumes PTYERR is high at the crossing of going high and going low. If PTYERR is low, it stays latched low for two clock cycles or until RESET is driven low. H 3

4 Ball Assignment Signal Group Signal Name Type escription Ungated inputs E0, E1, OT0, OT1 SSTL_18 RAM function pins not associated with Chip Select. Chip Select gated inputs SSTL_18 RAM inputs, re-driven only when Chip Select is LOW. Chip Select inputs Re-driven outputs CS0, CS1 SSTL_18 RAM Chip Select signals. These pins initiate RAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all -inputs only (CSGateEN high) when at least one Chip Select input is LOW. Q0...Q20, QCS0-1, QE0-1, QOT0-1 SSTL_18 Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock. Parity input PARIN SSTL_18 Input parity is received on pin PARIN and should maintain odd parity across the inputs, at the rising edge of the clock. Parity error output Program inputs CSGateEN PTYERR Open drain When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard R-II register with parity (in JEEC definition). 1.8 V LVCMOS Chip Select Gate Enable. When HIGH, the inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the inputs will be latched and redriven on every rising edge of the clock. Clock inputs, SSTL_18 ifferential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (). Miscellaneous inputs RESET 1.8 V LVCMOS Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET also resets the PTYERR signal. VREF 0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability. 4

5 5 ICSSSTUB32871A Block iagram Q R Q R Q R Q R Q R Q R Q R PARIN 0 20 VREF (CS ACTIVE) CS0 CS1 E0, E1 OT0, OT1 CSGateEN RESET 21 PARITY GENERATOR AN CHEER Q0 Q20 QCS0 QCS1 QE0, QE1 QOT0, QOT1 PTYERR

6 Parity Functionality Block iagram n 21 Q 21 Qn LATCHING AN RESET FUNCTION see Note (1) PTYERR PARIN (1) This function holds the error for two cycles. See functional description and timing diagram. CLO 002aaa417 6

7 Register Timing RESET CSn n n + 1 n + 2 n + 3 n + 4 t ACT t su th n (1) t PM, t PMSS to Q Qn t su t h PARIN PTYERR t PHL to PTYERR t PHL, t PLH to PTYERR H, L, or X H or L (1) After RESET is switched from LOW to HIGH, all data and PARIN input signals must be set and held LOW for a minimum time of t (max) to avoid false error. ACT Figure 4 RESET switches from L to H 7

8 Register Timing RESET CSn n n + 1 n + 2 n + 3 n + 4 t su t h n (1) t PM, t PMSS to Q Qn t su t h PARIN t PHL, t PLH to PTYERR PTYERR Unknown input event Output signal is dependent on the pr ior unknown event H or L 002aaa984 Figure 5 RESET being held HIGH 8

9 Register Timing RESET t INACT CSn (1) (1) n (1) t RPHL RESET to Q Qn PARIN (1) t RPLH RESET to PTYERR PTYERR H, L, or X H or L Figure 6 RESET switches from H to L (1) After Reset is switched from HIGH to LOW, all data and clock input signals must be set and held at valid logic levels (not ) for a minimum time of t INACT (max) 9

10 Absolute Maximum Ratings Storage Temperature C to +150 C Supply Voltage V to 2.5V Input Voltage 1, V to V +2.5V Output Voltage 1, V to VQ + 0.5V Input Clamp Current ±50 ma Output Clamp Current ±50mA Continuous Output Current ±50mA V or GN Current/Pin ±100mA Package Thermal Impedance C Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JES 51. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions PARAMETER ESCRIPTION MIN TYP MAX UNITS V Q I/O Supply Voltage V REF Reference Voltage 0.49 x V 0.5 x V 0.51 x V V TT Termination Voltage V REF V REF V REF V I Input Voltage 0 V Q V IH (C) C Input High Voltage V REF V IH (AC) AC Input High Voltage V REF ata Inputs V IL (C) C Input Low Voltage V REF V IL (AC) AC Input Low Voltage V REF V V IH Input High Voltage Level 0.65 x V Q RESET V IL Input Low Voltage Level 0.35 x V Q V ICR Common mode Input Range , V I ifferential Input Voltage I OH High-Level Output Current -8 ma I OL Low-Level Output Current 8 T A Operating Free-Air Temperature 0 70 C 1 Guaranteed by design, not 100% tested in production. Note: Rst and Cn inputs must be helf at valid logic levels (not ) to ensure proper device operation. The differential inputs must not be unless Rst is low. 10

11 Electrical Characteristics - C T A = 0-70 C; V = 2.5 +/-0.2V, V Q =2.5 +/-0.2V; (unless otherwise stated) SYMBOL PARAMETERS CONITIONS V Q MIN TYP MAX UNITS V OH I OH = -8mA 1.7V 1.2 V OL I OL = 8mA 1.7V 0.5 V I I All Inputs V I = V or GN 1.9V ±5 µa Standby (Static) RESET = GN 200 µa I V I = V IH(AC) or V IL(AC), 1.9V Operating (Static) RESET = V 150 ma ynamic operating (clock only) RESET = V,V I = V IH(AC) or V IL(AC), CLK and CLK switching 50% duty cycle. I O = 0 TB µa/clock MHz I ynamic Operating (per each data input) RESET = V, V I = V IH(AC) or V IL (AC), CLK and CLK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle 1.8V TB µa/ clock MHz/data ata Inputs V I = V REF ±350mV pf C i CLK and CLK V ICR = 1.25V, V I(PP) = 360mV RESET V I = V Q or GN 4.5 pf Notes: 1 - Guaranteed by design, not 100% tested in production. Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) PARAMETER V = 1.8V ± 0.1V MIN MAX UNIT dv/dt_r 1 4 V/ns dv/dt_f 1 4 V/ns dv/dt_δ 1 1 V/ns 1. ifference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate) 11

12 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS V = 1.8V ±0.1V MIN MAX UNITS f clock Clock frequency 410 MHz t W Pulse duration 1 ns t ACT ifferential inputs active time 10 ns t INACT ifferential inputs inactive time 15 ns t S ata before CLK, CLK 0.6 Setup time CS0, SC1 before CLK, ns 0.7 CLK, CSR HIGH CS, OT, E and n Hold time 0.6 ns after CLK, CLK t H Hold time PAR_IN after CLK, CLK 0.5 ns Notes: 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK signal input slew rate of 1V/ns. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) Symbol Parameter Measurement Conditions MIN MAX Units fmax Max input clock frequency 410 MHz t PM Propagation delay, single bit switching CLK and CLK to Qn ns t LH Low to High propagation CLK and CLK to delay PTYERR ns t HL High to low propagation CLK and CLK to delay PTYERR ns t PMSS Propagation delay simultaneous switching CLK and CLK to Qn 2 ns t PHL High to low propagation delay RESET to Qn 3 ns t PLH Low to High propagation delay RESET to PTYERR 3 ns 1. Guaranteed by design, not 100% tested in production. 12

13 Inputs TL=50Ω Test Point UT Out TL=350ps, 50Ω C L = 30 pf (see Note 1) V R L = 1000Ω Test Point R L = 1000Ω R L = 100Ω Test Point LOA CIRCUIT VCMOS RST Inp ut V /2 V /2 V 0 V V I t inact t act V ICR V ICR I (see Note 2) 10% 90% VOLTAGE AN CURRENT WAVEFORMS INPUTS ACTIVE AN INACTIVE TIMES V t I w t PLH t PHL V OH Output V TT V TT V OL VOLTAGE WAVEFORMS PROPAGATION ELAY TIMES Inpu t V ICR V ICR VOLTAGE WAVEFORMS PULSE URATION V I V ICR LVCMOS RST Input V /2 t RPHL V IH V IL t su t h V IH Inpu t V REF V REF V IL VOLTAGE WAVEFORMS SETUP AN HOL TIMES V OH Output V TT V OL VOLTAGE WAVEFORMS PROPAGATION ELAY TIMES Figure 6 Parameter Measurement Information (V = 1.8V ± 0.1V) Notes: 1. C L incluces probe and jig capacitance. 2. I tested with clock and data inputs held at V or GN, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR 10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. V REF = V /2 6. V IH = V REF mv (ac voltage levels) for differential inputs. V IH = V for LVCMOS input. 7. V IL = V REF mv (ac voltage levels) for differential inputs. V IL = GN for LVCMOS input. 8. V I = 600 mv 9. t PLH and t PHL are the same as t PM. 13

14 UT V R L = 50Ω Out C L = 10 pf (see Note 1) Test Point LOA CIRCUIT HIGH-TO-LOW SLEW-RATE MEASUREMENT Output 80% V OH dv_f 20% dt_f V OL VOLTAGE WAVEFORMS HIGH-TO-LOW SLEW-RATE MEASUREMENT UT Out C L = 10 pf (see Note 1) Test Point R L = 50Ω LOA CIRCUIT LOW-TO-HIGH SLEW-RATE MEASUREMENT dv _r 80% dt_r V OH Output 20% V OL VOLTAGE WAVEFORMS LOW-TO-HIGH SLEW-RATE MEASUREMENT Figure 7 Output Slew-Rate Measurement Information (V = 1.8V ± 0.1V) Notes: 1. C L includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, Z O = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 14

15 3 Test circuits and switching waveforms (cont d) 3.3 Error output load circuit and voltage measurement information (V =1.8V±0.1V) All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z o = 50 Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. UT Out C L = 10 pf (see Note 1) V R L = 1KΩ Test Point LOA CIRCUIT HIGH-TO-LOW SLEW-RATE MEASUREMENT (1) C L includes probe and jig capacitance. Figure 28 Load circuit, error output measurements LVCMOS RST Input Output Waveform 2 tplh V CC / V _ V CC 0 V V OH 0 V Figure 29 Voltage waveforms, open-drain output low-to-high transition time with respect to reset input VI(PP) Timing Inputs VICR V ICR Output Waveform 1 tphl _ V CC/2 V CC VOL Figure 30 Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs VI(PP) Timing Inputs VICR VICR tphl Output Waveform V V OH 0 V Figure 31 Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs 15

16 3 Test circuits and switching waveforms (cont d) 3.4 Partial-parity-out load circuit and voltage measurement information (V =1.8V±0.1V) All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z o = 50 Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. UT Out CL = 5 pf (see Note A) Test Point RL = 1 kω (1) C L includes probe and jig capacitance. Figure 32 Partial-parity-out load circuit, V ICR t PLH V ICR t PHL V i(p-p) OUTPUT V TT V OH V OL 002aaa375 V TT = V /2 t PLH and t PHL are the same as t P. V I(PP) = 600 mv Figure 33 Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs INPUT LVCMOS RST V /2 t PHL V IH V IL OUTPUT V TT V OH V OL 002aaa376 V TT = V /2 t PLH and t PHL are the same as t P. V IH = V REF mv (AC voltage levels) for differential inputs. V IH = V for LVCMOS inputs. V IL = V REF mv (AC voltage levels) for differential inputs. V IL = V for LVCMOS inputs. Figure 34 Partial-parity-out voltage waveforms; propagation delay times with respect to reset input 16

17 A1 Seating Plane C T b REF Numeric esignations for Horizontal Grid A B C Alpha esignations for Vertical Grid (Letters I, O, Q & S not used) d TYP 1 TOP VIEW - e - TYP E h TYP 0.12 C c REF E1 - e - TYP ALL IMENSIONS IN MILLIMETERS BALL GRI Max. REF. IMENSIONS E T e HORIZ VERT TOTAL d h b c Min/Max Min/Max Min/Max Bsc 5.50 Bsc 1.20/ Bsc / / Bsc 5.00 Bsc 1.00/ Bsc / / Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used C Ordering Information ICSSSTUB32871Az(LF)T Example: ICS XXXX y z (LF) T * Source Ref.: JEEC Publication 95, MO-205 esignation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Package Type H = LFBGA (reduced size: 5.5 x 13.50) HM = TFBGA (reduced size: 5.0 x 11.50) Revision esignator (will not correlate with datasheet revision) evice Type Prefix ICS = Standard evice 17

18 Revision History Rev. Issue ate escription Page # B 3/20/2006 Updated Ordering Information. 17 C 2/2/2007 Applications, 2nd bullet, changed ULP877 to ULPA877A, added ITCSPUA877A 1 Page 1, Applications, 3rd bullet, removed 800; page 11, Electrical table, 3/1/2007 changed Idd Operating Max from 80 to 150, changed RESET Typ from 2.5 1, 11, 12 to 4.5; page 12, Timing table, changed ts (ata before...) from 0.5 to 0.6, changed th (CS, OT...) from 0.5 t E 3/6/2007 Timing table, th hold time, changed Q to n; Switching Cha. Table, fixed typos. 12 F 3/13/2007 Page 1, Recc. List, changed 3rd bullet to "Provides complete R IMM solution with ICS98ULPA877A, ICS97ULP877, or ITCSPUA877A"; page 1, 11 11, fixed typos. G 4/16/2007 Electrical Cha. Table, changed Ci: ata Inputs max from 3.5 to 5, and CLK Max from 3 to

ICSSSTUA32866B. 25-Bit Configurable Registered Buffer for DDR2. Integrated Circuit Systems, Inc. Pin Configuration. Functionality Truth Table

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