ICSSSTUA32866B. 25-Bit Configurable Registered Buffer for DDR2. Integrated Circuit Systems, Inc. Pin Configuration. Functionality Truth Table

Transcription

1 Integrated Circuit Systems, Inc. ICSSSTUA32866B 25-Bit Configurable egistered Buffer for 2 ecommended Application: 2 Memory Modules Provides complete IMM solution with ICS97ULP877 Ideal for 2 400,533 and 667 Product Features: 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity check functionality Supports SSTL_18 JEEC specification on data inputs and outputs Supports LVCMOS switching levels on CS# and ESET# inputs Low voltage operation V = 1.7V to 1.9V Available in 96 BGA package rop-in replacement for ICSSSTUA32864 Green packages available Pin Configuration A B C E F G H J K L M N P Functionality Truth Table I nputs ST# CS# CS# # n, OT, E Qn Outputs QCS# QOT, QE H L L L L L L H L L H H L H H L L L or H L or H X Q 0 Q 0 Q 0 H L H L L L L H L H H H L H H L H L or H L or H X Q 0 Q 0 Q 0 H H L L L H L H H L H H H H H H L L or H L or H X Q 0 Q 0 Q 0 H H H L Q 0 H L H H H H Q 0 H H H H H L or H L or H X Q 0 Q 0 Q 0 L X or Floating X or Floating X or Floating X or Floating X or Floating L L L T 96 Ball BGA (Top View)

2 Ball Assignments 25 bit 1:1 egister A E PPO V EF V QE NC B 2 15 GN GN Q2 Q15 C 3 16 V V Q3 Q16 OT QE# GN GN QOT NC E 5 17 V V Q5 Q17 F 6 18 GN GN Q6 Q18 G PA_IN ST# V V C1 C0 H CS# GN GN QCS# NC J # CS# V V ZOH ZOL K 8 19 GN GN Q8 Q19 L 9 20 V V Q9 Q20 M GN GN Q10 Q21 N V V Q11 Q22 P GN GN Q12 Q V V Q13 Q24 T V EF V Q14 Q C0 = 0, C1 = 0 14 bit 1:2 egisters A E PPO V EF V QEA QEB B 2 NC GN GN Q2A Q2B C 3 NC V V Q3A Q3B OT QE# GN GN QOTA QOTB E 5 NC V V Q5A Q5B F 6 NC GN GN Q6A Q6B G PA_IN ST# V V C1 C0 H CS# GN GN QCSA# QCSB# J # CS# V V ZOH ZOL K 8 NC GN GN Q8A Q8B L 9 NC V V Q9A Q9B M 10 NC GN GN Q10A Q10B N 11 NC V V Q11A Q11B P 12 NC GN GN Q12A Q12B 13 NC V V Q13A Q13B T 14 NC V EF V Q14A Q14B egister A (C0 = 0, C1 = 1) A 1 PPO V EF V Q1A Q1B B 2 NC GN GN Q2A Q2B C 3 NC V V Q3A Q3B 4 QE# GN GN Q4A Q4B E 5 NC V V Q5A Q5B F 6 NC GN GN Q6A Q6B G PA_IN ST# V V C1 C0 H CS# GN GN QCSA# QCSB# J # CS# V V ZOH ZOL K 8 NC GN GN Q8A Q8B L 9 NC V V Q9A Q9B M 10 NC GN GN Q10A Q10B N OT NC V V QOTA QOTB P 12 NC GN GN Q12A Q12B 13 NC V V Q13A Q13B T E NC V EF V QEA QEB egister B (C0 = 1, C1 = 1) 2

3 General escription This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V V operation. All clock and data inputs are compatible with the JEEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the -II IMM load. ICSSSTUA32866B operates from a differential clock ( and #). ata are registered at the crossing of going high, and # going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). A - Pair Configuration (CO 1 = 0, CI 1 = 1 and CO 2 = 0, CI 2 = 1) Parity that arrives one cycle after the data input to which it applies is checked on the PA_IN of the first register. The second register produces to PPO and QE# signals. The QE# of the first register is left floating. The valid error information is latched on the QE# output of the second register. If an error occurs QE# is latched low for two cycles or until eset# is low. B - Single Configuration (CO = 0, C1 = 0) The device supports low-power standby operation. When the reset input (ST#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VEF) inputs are allowed. In addition, when ST# is low all registers are reset, and all outputs are forced low. The LVCMOS ST# and Cn inputs must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, ST# must be held in the low state during power up. In the -II IMM application, ST# is specified to be completely asynchronous with respect to and #. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of ST# until the input receivers are fully enabled, the design of the ICSSSTUA32866B must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both CS# and CS# inputs and will gate the Qn outputs from changing states when both CS# and CS# inputs are high. If either CS# or CS# input is low, the Qn outputs will function normally. The ST input has priority over the CS# and CS# control and will force the outputs low. If the CS#-control functionality is not desired, then the CS# input can be hardwired to ground, in which case, the setup-time requirement for CS# would be the same as for the other data inputs. Package options include 96-ball LFBGA (MO-205CC). Parity and Standby Functionality Truth Table Inputs Outputs st# CS# CS# # Sum of Inputs = H (1-25) PA_IN PPO QE# H L X Even L L H H L X Odd L H L H L X Even H H L H L X Odd H L H H H L Even L L H H H L Odd H H L H H H X X PPO 0 QE 0 # H X X L or H L or H X X PPO 0 QE 0 # L X or Floating X or Floating X or Floating X or Floating X or Floating X or Floating 1. CO = 0 and CI = 0, ata inputs are 2, 3, 5, 6, CO = 0 and CI = 1, ata inputs are 2, 3, 5, 6, 8-14 CO = 1 and CI = I, ata inputs are 1-6, 8-10, 12, PA_IN arrives one clock cycle after the data to which it applies when CO = PA_IN arrives two clock cycles after the data to which it applies when CO = Assume QE# is high at the and # crossing. If QE# is low it stays latched low for two clock cycles on until st# is low. L H 3

4 4 ICSSSTUA32866B Name erminal T n escriptio Electrical Characteristics N G d roun G t inpu Ground V e voltag supply ower P l 1.8V nomina V F E e voltag reference nput I l 0.9V nomina Z H O e us future for eserved t Inpu Z L O e us future for eserved t Inpu K C t inpu clock master ositive P t inpu ifferential K C t inpu clock master egative N t inpu ifferential C1 0, C s input control onfiguration C s LVCMOS input ST# V disables and registers resets - input reset synchronous A F E d an data receivers differential-input clock input LVCMOS CS# CS#, inputs both when switching outputs 24-1 disables - inputs select Chip high are input SSTL_ the and of edge rising the of crossing the on in clock - input ata # of edge falling input SSTL_18 OT and CS# the by suspended be not will bit register this of outputs The control CS# input SSTL_18 E and CS# the by suspended now be will bit register this of outputs The control CS# input SSTL_18 Q25-1 Q l contro CS# and CS# the by suspended are that ouputs ata S CMO 1.8V CS# Q l contro CS# and CS# the by suspended be not will that output ata S CMO 1.8V OT Q l contro CS# and CS# the by suspended be not will that output ata S CMO 1.8V E Q l contro CS# and CS# the by suspended be not will that output ata S CMO 1.8V PO P inputs of parity off indicates out parity artial P S CMO 1.8V A_IN P t inpu data corresponding the after cycle clock one arrives input arity P t inpu SSTL_18 QE# data corresponding the after cycle clock one bit-generated error Output output drain Open output Ball Assignment

5 Block iagram for 1:1 mode (positive logic) ST# # V EF E C1 QEA OT C1 QOTA CS# 1 C1 QCSA# CS# C1 Q1A Q1B * To 21 Other Channels *Note: isabled in 1:1 configuration 5

6 Block iagram for 1:2 mode (positive logic) ST# # V EF E 1 C1 QEA QEB* OT 1 C1 QOTA QOTB* CS# 1 C1 QCSA# QCSB#* CS# C1 Q1A Q1B * To 10 Other Channels *Note: isabled in 1:1 configuration 6

7 2. evice standard (cont'd) ST# G2 # 2 3, 5 6, 8-25 V EF H1 J1 22 A3, T3 LPS0 (internal node) CE Q , 5 6, , 5 6, Q2 Q3, Q5 Q6, Q8 Q25 Parity Generator C1 G5 PA_IN G1 Q 0 1 Q CE Q 1 0 A2 2 PPO QE# C0 G6 2 Bit Counter LPS1 (internal node) Q 0 1 Figure 6 Parity logic diagram for 1:1 register configuration (positive logic); C0=0, C1=0 7

8 2. evice standard (cont'd) ST# G2 # 2 3, 5 6, 8-14 VEF H1 J1 11 A3, T3 LPS0 (internalnode) CE Q , 5 6, , 5 6, Q2A Q3A, Q5A Q6A, Q8A Q14A Q2B Q3B, Q5B Q6B, Q8B Q14B Parity Generator C1 G5 0 1 A2 PPO PA_IN G1 Q 1 Q Q CE 0 2 QE# C0 G6 2 Bit Counter LPS1 (internal node) Q 0 1 Figure 7 Parity logic diagram for 1:2 register-a configuration (positive logic); C0=0, C1=1 Figure 7 Parity logic diagram for 1:2 register-a configuration (positive logic); C0=0, C1=1 8

9 2. evice standard (cont'd) ST# G2 # H1 J1 LPS0 (internal node) 1 6, 8-13 V EF 11 A3, T3 CE Q , , Q1A Q6A, Q8A Q13A Q1B Q6B, Q8B Q13B Parity Generator C1 G5 PA_IN G1 Q 0 1 Q Q CE 1 0 A2 2 PPO QE# C0 G6 2 Bit Counter LPS1 (internal node) Q 0 1 Figure 8 Parity logic diagram for 1:2 register-b configuration (positive logic); C0=1, C1=1 9

10 2. evice standard (cont'd) ST# CS# CS# n n + 1 n + 2 n + 3 n + 4 # t act t su t h 1 25 t pdm, t pdmss to Q Q1 Q25 t su t h PA_IN t pd to PPO PPO t PHL to QE# t PHL, t PLH to QE# QE# ata to QE# Latency H, L, or X H or L Figure 9 Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; ST# Switches from L to H After ST# is switched fro low to high, al data and PA_IN inputs signals must be se and held lo for a minimum time of t ACT max, to avoid false error. If the data is clocked in on the n clock pulse, the QE# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 10

11 2. evice standard (cont'd) ST# CS# CS# n n + 1 n + 2 n + 3 n + 4 # t su t h 1 25 t pdm, t pdmss to Q1 Q25 t su t h PA_IN t pd to PPO PPO ata to PPO Latency t PHL or t PLH to QE# QE# ata to QE# Latency Unknown input event Output signal is dependent on the prior unknown input event H or L Figure 10 Timing diagram for SSTU32866 used as a single device; C0=0, C1=0; ST# being held high If the data is clocked in on the n clock pulse, the QE# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QE# output is driven low, it stays latched low for a minimum of two clock cycles or until ST# is driven low. 11

12 2. evice standard (cont'd) ST# t inact CS# CS# # 1 25 t PHL ST# to Q Q1 Q25 PA_IN t PHL ST# to PPO PPO QE# t PLH ST# to QE# H, L, or X H or L Figure 11 Timing diagram fo SSTU32866 used as a single device; C0=0, C1=0; ST# switches from H to L After ST# is switched from high to low, all data and clock inputs signals must be set and held at valid logic levels (not floating) for a minimum time of t INACT max 12

13 2. evice standard (cont'd) ST# CS# CS# n n + 1 n + 2 n + 3 n + 4 # t act t su t h 1 14 t pdm, t pdmss to Q Q1 Q14 t su t h PA_IN t pd to PPO PPO t PHL to QE# t PHL, t PLH to QE# QE# (not used) ata to QE# Latency H, L, or X H or L Figure 12 Timing diagram for the firs SSTU32866 (1:2 register-a configration) device used in pair; C0 = 0, C1 = 1; ST# switches from L to H After ST# is switched fro low to high, al data and PA_IN inputs signals must be se and held lo for a minimum time of t ACT max, to avoid false error If the data is clocked in on the n clock pulse, the QE# output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. 13

14 2. evice standard (cont'd) ST# CS# CS# n n + 1 n + 2 n + 3 n + 4 # t su t h 1 14 t pdm, t pdmss to Q Q1 Q14 t su t h PA_IN t pd to PPO PPO QE# (not used) ata to PPO Latency ata to QE# Latency t PHL or t PLH to QE# Unknown input event Output signal is dependent on the prior unknown input event H or L Figure 13 Timing diagram for the firs SSTU32866 (1:2 register-a configration) device used in pair; C0 = 0, C1 = 1; ST# bein held high If the data is clocked in on the n clock pulse, the QE# output signal will be generated on the n+1 clock pulse, and it will be valid on the n+2 clock pulse. If an error occurs and the QE# output is driven low, it stays latched low for a minimum of two clock cycles or until ST# is driven low. 14

15 2. evice standard (cont'd) ST# t inact CS# CS# # 1 14 t PHL ST# to Q Q1 Q14 PA_IN t PHL ST# to PPO PPO QE# (not used) t PLH ST# to QE# H, L, or X H or L Figure 14 Timing diagram for the firs SSTU32866 (1:2 register-a configration) device used in pair; C0 = 0, C1 = 1; ST# switches from H to L After ST# is switched from high to low, all data and clock inputs signals must be held at valid logic levels (not floating) for a minimum time of t INACT max 15

16 2. evice standard (cont'd) ST# CS# CS# n n + 1 n + 2 n + 3 n + 4 # t act t su t h 1 14 t pdm, t pdmss to Q Q1 Q14 t su t h PA_IN PPO (not used) t pd to PPO t PHL to QE# t PHL, t PLH to QE# QE# ata to QE# Latency H, L, or X H or L Figure 15 Timing diagram for the second SSTU32866 (1:2 register-b configration) device used in pair; C0 = 1, C1 = 1; ST# switches from L to H After ST# switched fro low to high, al data and PA_IN inputs signals must be se and held lo for a minimum time of t ACT max, to avoid false error PA_IN is driven from PPO of the first SSTU32866 device If the data is clocked in on the n clock pulse, the QE# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. 16

17 2. evice standard (cont'd) ST# CS# CS# n n + 1 n + 2 n + 3 n + 4 # tsu th 1 14 tpdm, t pdmss to Q Q1 Q14 tsu th PA_IN tpd to PPO PPO QE# (not used) ata to PPO Latency ata to QE# Latency tphl or t PLH to QE# Unknown input event Output signal is dependent on the prior unknown input event H or L Figure 16 Timing diagram for the second SSTU32866 (1:2 register-b configration) device used in pair; C0 = 1, C1 = 1; ST# being held high PA_IN is driven from PPO of the first SSTU32866 device If the data is clocked in on the n clock pulse, the QE# output signal will be generated on the n+2 clock pulse, and it will be valid on the n+3 clock pulse. If an error occurs and the QE# output is driven low, it stays latched low for a minimum of two clock cycles or until ST# is driven low. 17

18 2. evice standard (cont'd) ST# t inact CS# CS# # 1 14 t PHL ST# to Q Q1 Q14 PA_IN t PHL ST# to PPO PPO (not used) QE# t PLH ST# to QE# H, L, or X H or L Figure 17 Timing diagram for the second SSTU32866 (1:2 register-b configration) device used in pair; C0 = 1, C1 = 1; ST# switches from H to L After ST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) fo a minimum time of t INACT max 18

19 * egister Configurations ATA INPUT: ATA OUTPUT: CO CI 2, 3, 5, 6, , 3, 5, 6, , 8-10, 12, 13 2, 3, 5, 6, , 3, 5, 6, , 8-10, 12,

20 Absolute Maximum atings Storage Temperature C to +150 C Supply Voltage V to 2.5V Input Voltage 1, V to +2.5V Output Voltage 1, V to V + 0.5V Input Clamp Current ±50 ma Output Clamp Current ±50mA Continuous Output Current ±50mA V or GN Current/Pin ±100mA Package Thermal Impedance C Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 2.5V maximum. 3. The package thermal impedance is calculated in accordance with JES 51. Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ecommended Operating Conditions PAAMETE ESCIPTION MIN TYP MAX UNITS V Q I/O Supply Voltage V EF eference Voltage 0.49 x V 0.5 x V 0.51 x V V TT Termination Voltage V EF V EF V EF V I Input Voltage 0 V Q V IH (C) C Input High Voltage V EF V IH (AC) AC Input High Voltage V EF ata Inputs V IL (C) C Input Low Voltage V EF V V IL (AC) AC Input Low Voltage V EF V IH Input High Voltage Level ST#, 0.65 x V Q V IL Input Low Voltage Level C0, C x V Q V IC Common mode Input ange , # V I ifferential Input Voltage I OH High-Level Output Current -8 I OL Low-Level Output Current 8 ma T A Operating Free-Air Temperature 0 70 C 1 Guaranteed by design, not 100% tested in production. Note: st# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless st# is low. 20

21 Electrical Characteristics - C T A = 0-70 C; V = 1.8 +/-0.1V (unless otherwise stated) SYMBOL PAAMETES CONITIONS V MIN TYP MAX UNITS V IK I I = -18mA -1.2 V OH I OH = -6mA 1.7V 1.2 V V OL I OL = 6mA 1.7V 0.5 I I All Inputs V I = V or GN 1.9V -5 5 µa Standby (Static) ESET# = GN 100 µa I V I = V IH(AC) or V IL(AC), 1.9V Operating (Static) ESET# = V 40 ma ESET# = V, ynamic operating V I = V IH(AC) or V IL(AC), µ/clock 39 (clock only) CLK and CLK# switching MHz 50% duty cycle. ESET# = V, I O = 0 I ynamic Operating (per each data input) 1.8V 1:1 mode V I = V IH(AC) or V IL (AC), 19 CLK and CLK# switching 50% duty cycle. One data ynamic Operating (per each data input) 1:2 mode input switching at half clock frequency, 50% duty cycle 35 ata Inputs V I = V EF ±350mV C i CLK and CLK# V IC = 1.25V, V I(PP) = 360mV 2 3 ESET# V I = V or GN 2.5 Notes: 1 - Guaranteed by design, not 100% tested in production. µa/ clock MHz/data pf Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) PAAMETE V = 1.8V ± 0.1V MIN MAX UNIT dv/dt_r 1 4 V/ns dv/dt_f 1 4 V/ns dv/dt_ 1 1 V/ns 1. ifference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate) 21

22 Timing equirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PAAMETES V = 1.8V ±0.1V MIN MAX UNITS f clock Clock frequency MHz t W Pulse duration,, HIGH or LOW 1 - ns t ACT ifferential inputs active time (See Notes 1 and 2) - 10 ns t INACT ifferential inputs inactive time (See Notes 1 and 3) - 15 ns t su Setup time S# before, #, CS# high 0.7 ns t su Setup time CS# before, #, CS# high 0.7 ns t su Setup time CS# before, #, CS# low 0.5 ns t su Setup time OT, E and data before, # 0.5 ns t su Setup time PA_IN before, # 0.5 ns t H Notes: Hold time CS#, OT, E and Q after, # 0.50 ns Hold time PA_IN after, # 0.50 ns 1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) Symbol Parameter Measurement Conditions MIN MAX Units fmax Max input clock frequency 410 MHz t PM Propagation delay, single bit switching to # QN ns t P Propagation delay to # to PPO ns t LH Low to High propagation delay to # to QE# ns t HL High to low propagation delay to # to QE# ns t PMSS Propagation delay simultaneous switching to # QN - 2 ns t PHL High to low propagation delay st# to QN 3 ns t PHL High to low propagation delay st# to PPO 3 ns t PLH Low to High propagation delay st# to QE# 3 ns 2. Guaranteed by design, not 100% tested in production. 22

23 Inputs TL=50Ω Test Point UT # Out TL=350ps, 50Ω C L =30pF (see Note 1) V L =1000Ω Test Point L =1000Ω L =100Ω Test Point LOA CICUIT VCMOS ST# Input V /2 V /2 V 0 V V I t in act t act V IC V IC I (see Note 2) 10% t w 90% VOLTAGE AN CUENT WAVEFOMS INPUTS ACTIVE AN INACTIVE TIMES V I Output t PLH t PHL V OH V TT V TT V OL VOLTAGE WAVEFOMS POPAGATION ELA TIMES Input V IC V IC VOLTAGE WAVEFOMS PULSE UATION V I V IC LVCMOS ST# Input V /2 t PHL V IH V IL Inpu t t su t h V EF V EF V IH V IL VOLTAGE WAVEFOMS SETUP AN HOL TIMES Output VOLTAGE WAVEFOMS POPAGATION ELA Figure 6 Parameter Measurement Information (V = 1.8 V ± 0.1 V) V TT V OH V OL TIMES Notes: 1. C L incluces probe and jig capacitance. 2. I tested with clock and data inputs held at V or GN, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: P 10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. V EF = V /2 6. V IH = V EF mv (ac voltage levels) for differential inputs. V IH = V for LVCMOS input. 7. V IL = V EF mv (ac voltage levels) for differential inputs. V IL = GN for LVCMOS input. 8. V I = 600 mv 9. t PLH and t PHL are the same as t PM. 23

24 UT V L = 50Ω Out C L = 10 pf (see Note 1) Test Point LOA CICUIT HIGH-TO-LOW SLEW-ATE MEASUEMENT Output 80% V OH dv_f 20% dt_f V OL VOLTAGE WAVEFOMS HIGH-TO-LOW SLEW-ATE MEASUEMENT UT Out C L = 10 pf (see Note 1) Test Point L = 50Ω LOA CICUIT LOW-TO-HIGH SLEW-ATE MEASUEMENT dv _r 80% dt_r V OH Output 20% V OL VOLTAGE WAVEFOMS LOW-TO-HIGH SLEW-ATE MEASUEMENT Figure 7 Output Slew-ate Measurement Infor mation (V = 1.8 V ± 0.1 V) Notes: 1. C L includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: P 10MHz, Z O = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified). 24

25 3 Test circuits and switching waveforms (cont d) 3.3 Error output load circuit and voltage measurement information (V =1.8V±0.1V) All input pulses are supplied by generators having the following characteristics: P 10 MHz; Z o = 50 Ω ; input slew rate = 1 V/ns ± 20%, unless otherwise specified. UT Out C L = 10 pf (see Note 1) V L = 1KΩ Test Point LOA CICUIT HIGH-TO-LOW SLEW-ATE MEASUEMENT (1) C L includes probe and jig capacitance. Figure 28 Load circuit, error output measurements LVCMOS ST# Input Output Waveform 2 tplh V CC / V _ V CC 0 V V OH 0 V Figure 29 Voltage waveforms, open-drain output low-to-high transition time with respect to reset input VI(PP) Timing Inputs VIC V IC Output Waveform 1 tphl _ V CC/2 V CC VOL Figure 30 Voltage waveforms, open-drain output high-to-low transition time with respect to clock inputs VI(PP) Timing Inputs VIC VIC tphl Output Waveform V V OH 0 V Figure 31 Voltage waveforms, open-drain output low-to-high transition time with respect to clock inputs 25

26 Test circuits and switching waveforms (cont d) 3.4 Partial-parity-out load circuit and voltage measurement information (V =1.8V±0.1V) All input pulses are supplied by generators having the following characteristics: P Z o = 50Ω input slew rate = 1 V/ns ± 20%, unless otherwise specified. 10 MHz; UT Out CL = 5 pf (see Note A) Test Point L = 1 kω (1) C L includes probe and jig capacitance. Figure 32 Partial-parity-out load circuit, V IC t PLH V IC t PHL V i(p-p) OUTPUT V TT = V /2 t PLH an t PHL are the same as t P. V I(PP) =600mV Figure 33 Partial-parity-out voltage waveforms; propagation delay times with respect to clock inputs V TT V OH V OL 002aaa375 INPUT LVCMOS ST# V /2 t PHL V IH V IL OUTPUT V TT V OH V OL 002aaa376 V TT = V /2 t PLH an t PHL are the same as t P. V IH = V EF mv (AC voltage levels for differential inputs. V IH = V for LVCMOS inputs. V IL = V EF 250 mv (A voltag levels) for differential inputs. V IL = V for LVCMOS inputs. Figure 34 Partial-parity-out voltage waveforms; propagation delay times with respect to reset input 26

27 A1 Seating Plane C T b EF Numeric esignations for Horizontal Grid A B C Alpha esignations for Vertical Grid (Letters I, O, Q & S not used) d TYP 1 TOP VIEW - e - TYP E h TYP 0.12 C c EF E1 - e - TYP ALL IMENSIONS IN MILLIMETES BALL GI Max. EF. IMENSIONS E T e HOIZ VET TOTAL d h b c Min/Max Min/Max Min/Max Bsc 5.50 Bsc 1.30/ Bsc / / Bsc 5.00 Bsc / Bsc / / Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used C Ordering Information ICSSSTUA32866Bz(LF)T Example: ICS XXXX y z (LF) T * Source ef.: JEEC Publication 95, MO-205 esignation for tape and reel packaging Lead Free (Optional) Package Type H = LFBGA (standard size: 5.5 x 13.50) HM = TFBGA (reduced size: 5.0 x 11.50) evision esignator (will not correlate with datasheet revision) evice Type Prefix ICS = Standard evice 27