A Gate-Delay Model for High-Speed CMOS Circuits *

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1 Gate-Delay Model for High-Speed CMOS Circuits * Florentin Dartu, Noel Menezes, Jessica Qian, and Lawrence T Pillage Department of Electrical and Computer Engineering The University of Texas at ustin, ustin, Texas 787 bstract -- s signal speeds increase and delays decrease for high-performance digital integrated circuits, the delay modeling problem becomes increasingly more difficult With scaling, increasing interconnect resistances and decreasing output impedances make it more difficult to empirically characterize -delay models Moreover, the single-input-switching assumption for the empirical models is incompatible with the inevitable simultaneous switching for today s high-speed logic paths In this paper a new empirical delay model is proposed Instead of building the empirical equations in terms of capacitance loading and input-signal transition time, the models are generated in terms of parameters which combine the benefits of empirically derived k-factor models and switch-resistor models to efficiently: ) handle capacitance shielding due to metal interconnect resistance, ) model the C interconnect delay, and ) provide tighter bounds for simultaneous switching I INTODUCTION s the minimum-feature sizes for integrated circuits scale downward, the portion of the delays attributable to the s decreases, while the percentage of the delay due to the C interconnect increases It is reasonable to expect that a significant amount of the overall path delay is attributable to the C interconnect delay This relative increase in interconnect delay is mainly because the interconnect lengths do not generally scale due to increasing chip densities, while the C per unit length product for the interconnect actually increases with scaling due to the fringing field effects In addition, if the output impedances of the s are decreased with scaling, the increased metal resistance will shield some of the load capacitance from the, thereby lowering the delay Unfortunately, this shift in delay dominance makes it significantly more difficult to efficiently model the delays with empirical equations, since the loading is not purely capacitive lso, it is difficult for empirical delay models of the output signal delay and transition time to approximate the delay in the case of simultaneous switching, when more than one input switches, since these delays can be significantly different than the single input transition delays * This work was supported in part by IM Corporation, the Semiconductor esearch Corporation under contract 9-DJ- and the National Science Foundation under contract MIP-97 In this paper a new empirical delay model is proposed which accurately captures the delay while modeling the C shielding and the C interconnect delay This is done in terms of a fixed dc resistance model for the s output impedance, along with a timevarying voltage source input The resistance value is a function of the only, and there is a single resistance value for the pull-up path (there is a different one for the pull-down path) which is independent of the load and the input transition time The voltage source parameters in this model are empirically generated in terms of the input waveform(s) and the effective capacitance loading Extensions are proposed for the simultaneous switching problem and for estimating the and interconnect delay in terms of simple equations for higher level analyses in terms of the best- and worst-case switching II CKGOUND There are two approaches to delay modeling which have gained considerable acceptance: ) a switch-resistor model comprised of a linear resistor and a step function of voltage, and ) empirically derived expressions for delay and output-signal transition time as a function of load capacitance and input-signal transition time (k-factor equations) oth methods are empirically based, since even the second method requires empirical fitting to approximate the resistance value as a function of input transition time and output load k-factor models When the load is purely capacitive, one can completely precharacterize a s delay and output signal behavior as a function of input signal transition time, t in, and load capacitance, C L [9] The experimental data for the delay, t d, and the -output waveform transition time, t r or t f, are generally fitted to k-factor equations: t d = k( t in, C L ) and t r/f = k' ( t in, C L ) Fig typical -delay problem For today s technologies the loads cannot be modeled as purely capacitive due to the C interconnect, as shown in Fig Traditionally, the delay from to and output rise or fall time at in this figure would be calculated from the equations in () using the total load capacitance (the sum of all of the interconnect capacitance and the input capacitances at C and D) and the signal transition time at The C delay would then be analyzed separately using the waveform at which is characterized by the result from () This two-step delay approximation works well when the load seen by the is accurately approximated by the total capacitance of the net That is, the procedure described for Fig assumes that the driving point admittance of the interconnect is equal to the total capacitance It has been recognized, however, that this is an invalid assumption for today s high speed CMOS C D ()

2 It was first recognized for ECL s that the total capacitance was not a valid model of the load [] In [], the nd order driving point admittance was modeled as a π-circuit, as shown in Fig Computing and storing k-factor equations for loads which are modeled by a π-circuit would be prohibitively expensive In [], the ECL s are modeled by linear Thevenin equivalents which drive the π-circuit in Fig x(t) t x Fixed{ Gate v (t) Z L (s) C C Fig nd order driving point admittance model for the interconnect load at node x(t) t x Fixed{ v(t) v^ (t) ZL (s) Linear resistance model It would appear that the switch-resistor model is a more effective delay model when the load is not purely capacitive That is, the resistance model is able to capture the interaction of the s output resistance and the C load Modeling the as a single resistance in series with a voltage step permits the use of computational efficient C tree and mesh signal delay bounds [,] to approximate the complete and interconnect delay In addition, it is recognized that the Elmore delay [] facilitates the efficient incorporation of estimated C circuit delays at the synthesis and floor planning levels of design Higher-order C analyses, such as the symptotic Waveform Evaluation (WE) technique, can be used to generate an extremely accurate C delay approximation; however, the result is only as accurate as the switch-resistor model for the Timing analysis tools such as TV [] and Crystal [] were developed using switch-resistor models to analyze the transistor level circuit descriptions The main difficulty with these approaches is calculating a single linear resistor which captures the switching behavior of a CMOS ecognizing that this resistance is a function of the s input signal transition time and output load, in [], a single output resistance for the is empirically derived from something similar to a k-factor equation That is, the resistance is calculated as the average output impedance as a function of the input signal transition time and the output load This extension is advantageous from an accuracy standpoint; however, when the load is not purely capacitive, it has the same limitations as the k-factor model The model III HIGH-PEFOMNCE GTE DELY MODEL The proposed model is shown in Fig ramp-like input signal is assumed throughout this paper as in (); however, complex C loading is considered here The limitations of the ramp-like waveshape assumption are discussed in section VI The linear resistor is selected independent of the load and input waveform It is computed in a pre-characterization step based upon the maximum allowable capacitive load complete description of the calculation of is given in section IV This waveshape can be obtained by applying the actual output waveform, v (t), to the inverse transfer function: Figures and show the V id (t) waveshapes obtained for this model given a capacitance load and an C load, respectively lso shown in Figures and are the saturated ramp approximations of - V id (t) and the response waveforms that they produce From these examples it is apparent that the V id (t) waveshape is accurately modeled by a simple, linearized waveshape The model in use Fig The model proposed for the digital cells V H ( s) = Z L ( s) egion egion egion C ctual output Linearized v(t) Ideal v(t) Fig esults obtained for an inverter with a pf load Similar to the equations in (), each is precharacterized by k- factor-like coefficients for the functions that define t and t of the voltage source: () To begin, we note the transfer function of the model in Fig is: H( s) V^( s) = = V( s) Z L ( s ) Z L ( s) + () t = f( t in, C L ) t = g( t in, C L ) t t () The ideal waveshape for this voltage source model (V id (t)) would be the one which produces the same output waveform as the itself single resistance value,, for the pull-up or pull-down path of the is also calculated

3 ctual output Linearized v(t) Ideal v(t) Go to step until convergence is reached + - I π C C + - Fig The averaging of the load currents I Ceff C eff - Fig esults obtained when an inverter drives a π-load with C =pf, C =pf, =89Ω When the load is not purely capacitive, it was shown in [] that a π-load represents a very accurate approximation of the CMOS C-interconnect load It was also shown that a nd order model is guaranteed to exist [] Since (), as (), is not valid for non-capacitive loads, we propose a method for mapping the π-circuit to a unique capacitance value which can then be used to determine (via ()) the values of t and t This capacitance is similar to the effective capacitance (C eff ) described in [] asically, we maintain the principle of equating the average current drawn by the effective capacitance and the π-circuit in the active region We differ from the approach in [] in our definition of the active region -- the time period over which the (the MOS transistors) can be naturally modeled as an average current In [], the active region was artificially terminated at the % point thereby ignoring the influence of the input waveform and load on the duration of the active region Our model uses egion from Fig as a more natural time period for the averaging process procedure to compute the voltage source parameters (through C eff ) is: Use min(c tot, C max ) as an initial estimate for C eff Compute t from () assuming C L = C eff Find the new C eff by equating the average current drawn from the voltage source (Fig ) in t time (egion ) by C eff and the π- load: I π = I Ceff These currents are given by: I π = t ---- p e p t D ( ) ---- p e p t V dd + + ( ) ( t) I C = eff t C eff t ( C eff ) V e d C eff dd ( t) where z z p z p = = D = p p p ( p p ) p ( p p ) and z, p, p are the zero and the two poles respectively of the transfer function (V o (s)-v(s))/v(s) () () (7) Steps through describe a simple fixed-point iteration procedure Fig 7 depicts a typical plot of the solutions of () for different values of t using t = g(t in,c L ) from () The intersection of these two curves represents the solution From the graph we observe that a Newton-aphson procedure to compute C eff would converge within fewer iterations For this reason we use N- iteration in practice We C eff Solution curv e of () for different t The curve t=g(t in,c eff ) from () the solution t (ns) Fig 7 Graphical representation of the iteration procedure for the result in Fig also note that by taking min(c tot, C max ) as an initial estimate for C eff, we never pass through an intermediate solution smaller than C eff We should point out that the C eff from Fig is the same as C L in Fig Therefore, the voltage source models in Figures and are identical, even though the response waveform are vastly different IV COMPUTTION OF THE MODEL PMETES n implicit assumption in our model is that the behavior of a can be classified into three operating regions (shown explicitly in Fig ) Consequently, the model offers three degrees of freedom for a best fit of the experimental data The driver s resistance t for the π-load Using the model in Fig, we are modeling the last operating region (egion C in Fig ) as a linear resistor connected to ground (for a falling transition) or V dd (for a rising transition) This is a refinement over switch-level simulators that use a linear resistor to model the over all operating regions Our solution is more accurate due to the reduced swing in the output voltage over which we linearize the output resistance We precharacterize while making the following observations (exemplified for a falling transition): For purely capacitive loads, a larger load capacitance will drive the into egion C earlier (larger initial voltage for region C) The average output resistance increases with the increase in the initial voltage

4 The final portion of the tail (when the output voltage is less than some voltage, V min ) is of no importance for delay and output slope computation Taking this portion of the waveform into consideration would artificially decrease the output resistance resulting in greater inaccuracy in the region of interest Increasing causes the output waveform to shift in a pessimistic direction We, therefore, fit the resistor value based on the largest load capacitance, C max, encountered by the driver in an actual circuitthe model output voltage in region C is given by: t t t v o () t V e d C = L (8) ctual output (d=) (d=) (d=) The two unknowns -- V and -- require us to provide two constraints The first constraint is the Least-Mean-Squared (LMS) best fit of the actual data windowed between two time points (at which the output voltage equal V and % of the V dd, respectively) The other constraint is that there exists a set of model parameters that will fit the %, % points of the output waveform as well as V Finding a solution for the above system can be viewed as an iterative process (again, this procedure is described for a falling transition) during precharacterization: Perform a SPICE analysis with the maximum allowable load capacitance to obtain the vector of the output voltage, v[n], and the corresponding vector of the discrete time points t[n] (n represents the n-th time point) Choose an initial value for V (V dd / is a good choice) Find the smallest k such that v[k] < V and the smallest m such that v[m] < V dd Compute to obtain a least-squares fit of the data with (8) m V t [] i ln v [] i i k = C L max m t [] j j k Using this value of, compute t and t in the manner described in the following subsection Find the smallest k such that t[k] > t + t 7 Go to step until convergence is reached This procedure usually converges within two or three iterations For the NND in Fig 7 an of Ω was obtained The response is compared with SPICE in Fig 8 We should point out that the delay approximation is fairly insensitive to the value of as shown in Fig 8 This is because the voltage source specifies the correct average current for egion, for any Using a large or a small will mainly impact the tail portion of the waveform (egion C) The empirical characterization of the One of the most obvious advantages of this model is the replacement of the output voltage (which grows further away from a digital shape with increasingly finer feature sizes) with a more digital waveform To take full advantage of this feature of the model, we propose the replacement of the ubiquitous k-factor equations in () (9) Fig 8 esults obtained for a NND driving a π-load with C =7pF, C =pf and =Ω when the model is precharacterized using different resistance values with the empirical characterization of the voltage source parameters, t and t, in equation () The basic approach used to obtain the empirical equations remains unchanged -- perform SPICE runs for different input transition times and different load capacitances However, instead of recording the output voltage parameters, t d and t r, we record parameters of the ideal voltage source voltage, v id (t) Unlike the output voltage, the ideal voltage source is not an observable waveform Fortunately, it can be easily derived from the SPICE simulation itself For a purely capacitive load: V id ( s) = V o ( s) ( + s C L ) which can be rewritten in the time domain as: () d v id () t = v o () t + C L vo () t = v () dt o () t + i CL () t where i is the current through the load capacitance -- a quantity available from the SPICE CL () t simulation lthough the ramp voltage can be characterized in the same manner as the output voltage in the k-factor equations in () (eg by the %-delay and the -9% slope) we prefer a slight modification Firstly, we do not characterize the %-delay since it has no physical significance now Secondly, we apply a correction to the t and t obtained from the -9% levels of V id (t) so as to match the % and % levels of the output voltage This correction, which provides an increased level of confidence in the new model precision, requires solving two nonlinear equations in two unknowns This iterative computation during precharacterization is efficient since the t and t of V (t), which is a good approximation of the corrected waveform, serve as excellent initial values Linearizing V id (t) id by the straight line passing through the % and 8% points is not as accurate V EXMPLES There are applications that require empirical models for complex cells (eg flip-flops, latches, etc) and/or multiple inputs s (eg n-inputs NND s) The complex cell case proved to be easily solvable by the method proposed in this paper Fig 9 presents the

5 result obtained using this model for a D-latch The comparison is ctual output One input active Voltage source models Fig 9 esults obtained for a D-latch drving a π-load with C =pf, C =pf and =89Ω between the actual SPICE result with an edge on CLK and that obtained with our model Two C eff iterations were required ccurate modeling of simultaneous switching is extremely difficult due to the ambiguity of the signal waveshapes and arrival times With the model proposed here, however, we can easily bound the simultaneous switching response on both sides, and in the process demonstrate the sensitivity of the delay to the number of inputs switching s an example, an empirical model was developed (following the steps outlined in Section IV) for a two-input NND with both inputs tied together and for one input switching alone (with the other input set to the proper sensitization value) The voltage source waveshapes and the response waveforms, as they compare with SPICE, are shown in Fig oth models use the same pull-down resistance, but notice that for a falling transition the voltage source delay is smaller and the transition time is shorter for the single input transition as compared to the same input signal arriving at both inputs simultaneously For the arrival of two signals with different waveshapes, the voltage source model for the two inputs tied together is a worst case response if the slower of the two edges is used in the empirical equation Similarly, the single input transition response with the slower of the two transition times is an optimistic prediction for the delay VI FUTUE WOK ND CONCLUSIONS We have presented a delay modeling approach that works extremely well for the highly-resistive interconnect loads present in today's CMOS circuits We observe that this approach accurately captures the non-digital behavior of the output waveforms The parameters for this model can be precharacterized efficiently We have also demonstrated the potential capabilities of this model for bounding the simultaneous switching delay In addition, it should be noted that since the resistor for the model is fixed, one can completely precharacterize the C loading and the in terms of dominant time constants following extraction The only parameter which varies during timing analysis is the voltage source slope and delay This facilitates the use of an extremely efficient delay equation for the and the interconnect Using worst-case (or best-case) voltage source parameters one can also use this model to "estimate" the delay at a very high level of design such as floor planning This model provides the foundation for several directions of future work First, we plan to provide more formal assertions regarding the bounds for simultaneous switching Secondly, we plan to develop metrics and bounds so that this model can be used with Inputs tied together Fig esults obtained for a NND driving a π-load with C =7pF, C =pf and =Ω wiring estimates and loading estimates for high-level delay estimation Finally, and perhaps most importantly, with this model the largest delay modeling error is now incurred when we attempt to apply the fan-out waveforms to subsequent stages Since these waveshapes no longer appear digital, substantial error is incurred when we model them as linear We will work on a more accurate, yet efficient, waveshape model which is compatible with this empirically-based delay methodology EFEENCES [] J ubenstein, P Penfield, Jr, and M Horowitz, Signal delay in C tree networks, IEEE Trans Computer-ided Design, vol CD-, pp -, July 98 [] J L Wyatt, Jr, Signal delay in C mesh networks, IEEE Trans on Circuits and Systems, vol CS-, no, pp 7-, May 98 [] W C Elmore, The transient response of damped linear networks with particular regard to wide-band amplifiers, J pplied Physics, vol 9, no, pp -, Jan 98 [] N Jouppi, Timing analysis and performance improvement of MOS VLSI designs, IEEE Trans Computer-ided Design, vol CD-, pp-, July 987 [] J K Ousterhout, switch-level timing verifier for digital MOS VLSI, IEEE Trans Computer-ided Design, vol CD-, no, pp -9, July 98 [] P O rien and TL Savarino, Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation, Proc IEEE Intl Conf Computer-ided Design, November 989 [7] CL atzlaff, N Gopal, and LT Pillage, ICE: apid Interconnect Circuit Evaluator, Proc 8th CM/IEEE Design utomation Conference, June 99 [8] LT Pillage and ohrer, symptotic waveform evaluation for timing analysis, IEEE Trans Computer-ided Design, pril, 99 [9] N H E Weste and K Eshraghian, Principles of CMOS VLSI Design, nd edition, ddison-wesley Publishing Company, Empirical Delay Models, pp, 99 [] CL atzlaff, S Pullela, and LT Pillage, Modeling the C-interconnect effects in a hierarchical timing analysis, IEEE Custom Integrated Circuits Conference, May 99 [] N Gopal and L T Pillage, Evaluation of on-chip interconnect using moment matching, Proc of the Intl Conf on Computer-ided Design, November, 99 [] LM rocco, SP Mccormick and J llen, Macromodeling CMOS circuits for timing simulation, IEEE Trans Computer-ided Design, December 988

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