Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models

Transcription

1 Driver Waveform Computation for Timing Analysis with Multiple Voltage Threshold Driver Models Peter Feldmann IBM T. J. Watson Research Center Yorktown Heights, NY Soroush Abbaspour, Debjit Sinha, Gregory Schaeffer, Revanta Banerji, Hemlata Gupta IBM Electronic Design Automation Hopewell Junction, NY Abstract This paper formalizes a family of logic gate characterization methods that result in Multiple Voltage Threshold Models MVTM. This modeling technique includes the existing industry standards, such as CCS and ECSM driver models as special cases. Based on this general model, the paper introduces a novel analysis algorithm for computing the output waveform of the driver gate loaded by an arbitrary interconnect circuit. The analysis technique relies solely on the primary MVTM characterization data and, unlike competing solutions, it does not require the explicit instantiation of controlled current source models, thus bypassing an intermediate modeling step. As a consequence, the method is more accurate, efficient and more general than the emerging industry standards. The theoretical results are validated by detailed simulations and through full chip timing analysis. I. INTRODUCTION Timing and noise analysis are the key verification steps in every design flow for ultra deep sub-micron UDSM VLSI circuits. In these applications a pre-characterized high level model of a logic gate loaded by an interconnect circuit is analyzed in order to determine delays through the various logic stages. Traditionally logic gates were modeled by ideal delays and their driving properties by simple Thevenin voltage sources. The signals were represented as idealized ramp shaped voltage waveforms. This approach has proven to be insufficiently accurate for timing and noise analysis purposes for chips implemented in the newest technologies. The main source of inaccuracy is the fact that the pre-characterization process can be practically performed only in terms of purely capacitive loads while the reality of the modern VLSI interconnect drifts further and further away from this assumption. On chip wires are highly resistive and even the inductive effects become significant at high frequencies. As a consequence the timing analysis algorithm has the challenge to adapt the pre-characterization data collected with just pure capacitive loading to the reality of RLC loads. The VLSI industry addressed this challenge mainly by introducing the concept of an effective capacitance that would capture the effect of a resistive-capacitive load 8], 9], 1]. The effective capacitance is a function of two parameters: 1 output voltage waveform of the driving gate and the characteristics of the load, more specifically the driving point admittance of the interconnect. Two gates are considered to be equivalent in terms of calculating effective capacitance if they produce the same output waveform when driving the same load 8]. As shown in Figure 1, a CMOS gate driving an RCπ load, will only see C n as its load if R π value goes to infinity. Fig. 1. A CMOS gate which drives an RCπ calculated load On the other hand, if R π goes to zero, then the gate will see C total = C n + C f. Therefore, the effective capacitance that the CMOS gate sees, can be written as: C eff = C n + k.c f, where < k < 1. Using a two-piece output waveform, Qian et al. proposed an effective capacitance calculation technique that approximates the output waveform of a CMOS gate 9]. The authors calculate the effective capacitance by equating the charges at the gate output when using the driving-point admittance of the load and using a single effective capacitance as the load. Average charges for both load models are equated until the gate output voltage reaches the 5% threshold. By using a table of circuit simulation results and a pair of two-dimensional delay tables, Macys et al. 8] calculated a value for the effective capacitance. In their work, the effective capacitance is a function of the total capacitance in the Π- model C total, the gate output slew rate, and the Elmore delay 5] of the load. Authors approximate the P i-model load with an effective capacitance such that the output voltage waveforms of the driving cell passes through some critical voltages e.g., and.75vdd at the same instances in time. In 1] the authors calculate an effective capacitance, which approximately matches both 5% propagation delay and the output transition time. All these approaches which produce just a single number, the effective capacitance, are bound to become inaccurate for the increasingly complicated interconnect models in advanced VLSI technologies. As a consequence, the recent trend in the industry is to adopt nonlinear driver modeling e.g., Controlled Current Source Models 4], 7] within timing and noise analysis engines. Examples are Cadence and Magma s effective current source model ECSM ] and Synopsys composite current source model CCS 1]. The ECSM model, for example, represents drivers as controlled current sources dependent on the driving point voltage and a so called dynamic capacitance: I = f I V, C. The

2 characterization process for this model is repeated simulations over ranges of ideal voltage ramp input excitations and pure capacitive loads. The results of these simulations are tabulated as driving point transition times as a function of voltage thresholds, and capacitive loads, T = f T V, C data. The controlled-current source model I = f I V, C model is obtained by fitting to the T = V, C data. CCS uses a similar characterization style; the main difference is that the characterization data is stored as current rather than voltage as a function of time and capacitive load. The two raw characterization data sets are essentially equivalent and can be mapped from one to another. Both ECSM and CCS modeling imply the transformation of raw modeling data, E.G., T = f T V, M into a nonlinear controlled current source device, e.g., I = f I V, C. This intermediate transformation incurs additional approximations and loss of accuracy. Moreover, these models require a relatively high degree of continuity and smoothness for accurate, reliable, and efficient timing and/or noise analysis. In this paper, we address these issues and propose a new analytical framework which is stable, efficient, accurate and extensible to a wide array of modeling techniques, including the abovementioned emerging industry standards. We introduce an algorithm for the simulation of a controlled current source driver model in conjunction with a linear interconnect RLC load. The algorithm advances on the voltage axis as opposed to the time axis and requires only the raw T = f T V, C-type driver characterization data in its original tabular format. The data transformation step and smoothing procedure involved in creating the intermediate current source model I = f I V, C, is eliminated and, as a consequence, the associated computational effort, and loss of accuracy is avoided. This novel algorithm has similar or superior efficiency to the ones that involve the generation of an explicit controlled current source model. II. DYNAMIC CAPACITANCE CONCEPT Most timing analysis methodologies used in practice in both past and present, pre-characterize and store in libraries the driving behaviour of logic gates. This behaviour is tabulated as functions of an input ramp signal of various transition times and a range of capacitive loads. The common problem facing all such methodologies is the fact that the true loads driven by the instances of the gate are not purely capacitive. Modern VLSI interconnect is highly resistive and even inductive effects are no longer negligible at high frequencies. As a consequence the timing analysis algorithm has the challenge to adapt the pre-characterization data collected with just pure capacitive loading to the reality of RLC loads. The traditional techniques abstracted the output waveform of a gate as an ideal voltage ramp, easily described by two parameters: the delay and the slew. Gate characterization consists of tabulating delay and slew of the voltage at the gate output as function of the gate input slew and a capacitive load. For general loads, these techniques use the concept of effective capacitance 9], 8], 1] and iteratively reduce the representation of a complicated RLC load to one single number, C eff. The recent controlled-current source models were introduced as a consequence of the fact that in stateof-the-art VLSI technologies such reduction can no longer be made without compromising analysis accuracy. The recent controlled-current source methods capture more detail of the output behaviour. The ECSM ] method and the technique presented in this paper tabulate a representation of the driving point voltage waveform as function of a load capacitance, and an input signal slew. The CCS 1] method tabulate a representation of the gate output current waveform as function of the same. In all cases the analysis algorithm must adapt to the real load typically represented by an RLC circuit. We now derive the theoretical foundation for this adaptation process, and in the sequel we will base an analysis algorithm on this foundation. Given that the input of the gate is assumed known, the result of timing analysis performed on the previous logic stage, we model the gate output as a nonlinear dynamic system with one state-variable. We conveniently chose this state variable as the gate output voltage, v. With such a model, the gate current is i = f d v, dv 1 dt In fact, the full transistor level equations for a CMOS inverter with known input will result in exactly this form. More complicated gates will have additional states corresponding to charges stored in internal nodes but they may still be approximated at least in a worst-case sense by such a model. Equation 1 constitutes a model which does not depend explicitly on the load attached at the gate output. Instead, the output voltage waveform will depend implicitly on the admittance of the load. When the load is a pure capacitance, C, as it happens during gate pre-characterization, we can rewrite the model equation as i = f d v, i C which can be solved formally to make i explicit i = f vc v, C Under mild assumptions, Equations 1 and are equivalent, the difference being essentially just a change of variables. The parameter C can be interpreted as a time varying instantaneous equivalent load capacitance Ct = it/ dv dt t which we denote as dynamic capacitance, C d t. Therefore parametrizing the output current waveform as a function of this instantaneous capacitive load is equivalent to assuming that the gate is described by the one-state nonlinear dynamical system in Equation 1. From a circuit simulation perspective, we would prefer modeling gates as dynamical systems, but for historical reasons, the timing community continues to use parametrization in terms of an equivalent capacitance.

3 Therefore the rest of the paper will carefully define and adopt C d for this purpose. It is interesting to note the connection between this newly defined dynamic capacitance and the effective capacitance used by traditional methods 9], 8], 1]. The effective capacitance for a voltage threshold V l, typically chosen as the mid-point of the full voltage swing, V 5%, satisfies by definition the relation Tl i o tdt = C e,l V l 3 where represents the threshold crossing time. For the case of MVTM analysis this definition introduces a sequence of effective capacitances each corresponding to a different threshold. Therefore we can write Tl i o tdt = i o tdt i o tdt = C e,l+1 V l+1 C e,l V l = C d,l V l+1 V l The result is an formula connecting the dynamic and effective capacitances C d,l = V l+1c e,l+1 V l C e,l V l+1 V l 4 III. DRIVER WAVEFORM COMPUTATION For the sequel of the paper we assume that gate characterization tabulates the output voltage waveforms as a function of input ramp slew and load capacitance. Further assuming that the output waveforms are monotonous, we can represent the waveforms as a sequence of crossing times corresponding to a sequence of voltage thresholds. Note that the monotonicity assumption is problematic for RLC circuits which may exhibit more complicated behaviour, e.g., ringing. We will not address this problem in this paper. For a given ramp slew value, the model captures the crossing times T i, of voltage thresholds V i, respectively, when the gate, loaded by an ideal capacitance, C l, performs a full transition T i C l = ΘV i, C l, i = 1,...,m, l = 1,...,n 5 Such a model is easily pre-characterized by performing full circuit simulation on the gate loaded by various pure capacitive loads, and excited by voltage ramps of a varying slew rates. The pre-characterization results can be stored in tabular form. In general, multiple tables will be needed for various input ramp slews. We denote this particular form of pre-characterization as Multiple Voltage Threshold Modeling MVTM. Based on the MVTM pre-characterized gate described above, we introduce a novel analysis algorithm that determines during timing analysis the waveform at the driving point of the gate loaded by an arbitrary interconnect circuit. The algorithm is restricted to monotonous output waveforms. We assume the input excitation slew known determined by the analysis of the previous stage. We first select and/or calculate by interpolation the MVTM table of Equation 5 corresponding to this slew. We take advantage of the assumption that the transition at the gate driving point is monotonic and proceed to calculate the times needed to cross a sequence of voltage thresholds. With no loss of generality, we analyze a rising transition at the driving point. Each step of the analysis determines the time, T i, for the driving point voltage to advance between successive voltage thresholds V l, V l+1. We impose for the voltage interval V l, V l+1 ] a charge equilibrium condition: the integral of the current supplied by the driver must be equal to the charge that flows into the load. The subsequent analysis is based on the additional assumption of a piecewise linear representation of the output voltage, i.e., the driving point voltage changes linearly between successive break-points V l and V l+1. We compute the charge supplied by the driver and obtain i o tdt = = i o t v vdt C d t V l+1 V l +1 dt i o tdt = V l+1 V l C d,l 6 where C d,l denotes the average dynamic capacitance exhibited by the gate between the two threshold crossings. We now derive an analytical expression for the charge flowing into the load. The load is fully characterized by the Laplace-domain admittance, Y s. Y s is determined from the linear interconnect circuit either directly, by model order reduction techniques, or in the form of a Π-model. The most general form that this admittance may take for an RLC circuit is k j Y s = k 1 s + k s j=1 From it we derive an expression for the current integral as a sum of charge states Tl i o tdt = j= 1 Q j,l Here Q 1,l corresponds to the term in s, the directly attached capacitance, Q,l corresponds to the integral of the DC current, equal to zero when the interconnect has no DC path to ground, and Q 1,l,...,Q N,l correspond to the d 1,..., d N time constants of the interconnect circuit. For timing analysis purposes, the state charges are conveniently expressed recursively, the state at the crossing of threshold V l+1, as a function of the state at the crossing of

4 threshold V l. Q 1,l+1 = Q 1,l + k 1 V l+1 V l 7 Q,l+1 = Q,l + 1 N k i V l+1 + V l +1 Q j,l+1 where i= = I j,l + Q j,l e Tl+1, j = 1,...,N I j,l = k j V l 1 e +1 ] + k j V l+1 V l 1 +1 ] 1 e T1+1 The detailed derivation of Equation 7 is straightforward and is omitted for conciseness. The charge flowing into the load is between voltage thresholds V l, V l+1 ] is i o tdt = Q j,l+1 Q j,l j= 1 and we equate it with the charge produced by the driver in Expression 6 to obtain the equation that needs to be solved for each new voltage threshold V l+1 C d,l V l+1 V l = k 1 V l+1 V l N k i V l+1 + V l +1 + j=1 i= I j,l + Q j,l e Tl+1 ] 1 This equation needs to be solved at each voltage threshold crossing, V l+1 assuming that a similar equation was solved at the previous crossing V l. The main unknown is the crossing time +1, but the dynamic capacitance is also unknown. Fortunately, we can write an additional equation from the driver model. We assume that between the crossing of thresholds V l and V l+1 the driver behaves as if loaded by a capacitive load equal to C d,l, i.e., +1 = ΘC d,l, V l+1 ΘC d,l, V l 9 The Equation 9 can be substituted in Equation 8 resulting in a single equation with a single unknown, C d,l, that can be solved numerically with a zero finding algorithm such as 3]. The new crossing time +1 results trivially from Equation 9 In the special case of a Π-model interconnect with parameters C n, R π, C f, k 1 = C n k =, k 1 = 1 and d 1 = R π C f R π the recursive state formulas 7 become Q 1,l+1 = Q 1,l + C n V l+1 V l 1 Q,l+1 = Q,l = Q j,l+1 = I j,l + Q j,l e Tl+1 and the Equation 8 to be solved for each new threshold voltage V l+1 becomes C d,l V l+1 V l = C n V l+l V l 11 + C f V l+1 V l 1 R πc f 1 e T1+1 ] +1 T l + C f V l 1 e Tl+1 ] + Q 1,l e Tl+1 1 IV. ALGORITHM The analysis presented in the previous section can be summarized by the following algorithm which will produce the crossing times for the voltage thresholds present in the MVTMs. 1 Set initial charge states Q 1 = Q = Q 1 =,...,Q N = Repeat for l = 1,...,M a Solve Equation 8 using, e.g., a Brent type zerofinding algorithm 3] C d,l V l+1 V l = k 1 V l+1 V l + 1 N k i V l+1 + V l +1 i= + I j,l + Q j,l e Tl+1 ] 1 j=1 after substituting +1 = ΘC d, V l+1 ΘC d, V l The substitution leaves C d,l as the only unknown in the equation. Upon convergence, we find its value. b The desired crossing time is trivially recovered +1 = ΘC d, V l+1 + ΘC d, V l c Finally we update interconnect charge states: Q 1,l+1 = Q 1,l + k 1 V l+1 V l Q,l+1 = Q,l + 1 N k i V l+1 + V l +1 i= Q j,l+1 = I j,l + Q j,l e Tl+1, j = 1,...,N and we advance to the next threshold value This algorithm avoids the time-domain integration that would be necessary for a straightforward controlled current source model. In that case the nonlinear equation of the model i = f vc v, c needs to be added to the time-domain differential equations of the linear interconnect, in full or reduced form and solved by various techniques, e.g., the one used by ]. This approach requires a smooth representation of the model, time-step control, etc. In contrast the algorithm proposed above uses the raw characterization data directly, avoiding the errors

5 introduced by the current-source modeling. The size and the number of steps is dictated solely by the accuracy of the model and not by the stiffness of the equation. V. RESULTS In order to verify the efficiency and accuracy of the proposed technique, the algorithm is applied first to small test cases two CMOS gates driving RC interconnect, then to large designs in 65nm technology. While the implemented method supports full RLC interconnect circuits with monotonic transitions, all the examples in the sequel have only RC interconnect. A. Small test case experimental setup For small test case experiments, we assume the circuit configuration shown in Figure. The circuit consists of a CMOS inverter followed by a CMOS gate which is chosen from the following set: {INVERTER, BUFFER, NAND, XOR}. Some important characteristics of the CMOS gates are shown in Table I. A fixed trapezoidal voltage waveform with the rising/falling transition time of ps is applied to the input pin of the first inverter driving a capacitive load C in, in addition to the CMOS gate under test. C in is used to control the voltage transition time at the input pin of the CMOS gate under test. To perform MVTM analysis, we employ a library of look-up tables containing the gate propagation delay and output voltage waveform V dd percentiles as functions of input transition time and output capacitive load. To confirm the advantage and stability of the proposed technique, For the interconnect portion of the simulation, we employ various RC topologies, that result in Π-models with a wide range of ratios between the effective near-end and far-end capacitances, C n, and C f, as well as a wide range of resistive shielding values. The value of total load resistance is chosen from the set R Π = {, 5, 1, 7, 1, 5}Ω and the total load capacitances chosen from the set C t = {4, 5, 6, 1, }ff. The voltage waveforms and their corresponding arrival times at the output terminal of the CMOS gates under test and the sink of the interconnect are determined successively by SPICE simulation, MVTM, and traditional gate timing analysis using the C eff technique. Since the CMOS gate library is characterized as a function of a ramp voltage waveform, a weighted least square fitting technique 6] has been used to approximate the arbitrary voltage waveform at the input pin of each gate with a saturated ramp waveform. Furthermore, a pole/residue representation of the interconnect transfer function has been used to propagate a piece-wise linear voltage waveform from the interconnect source to its sink terminals. The minimum, average, and maximum error for gate and interconnect propagation delay, interconnect source and sink 1 9% slew, as well as the time axis least square error of the corresponding voltage waveforms between SPICE vs. MVTM and SPICE vs. the C eff method are calculated and presented in Table II. Furthermore, the voltage waveform for some of these cases are shown in Figures 3-5. Experimental results confirm that MVTM is stable and accurate compared to the SPICE results for all the different Fig.. Experimental setup for small testcases. In this experiment, the CMOS gate under test is chosen from: {INVERTER, BUFFER, NAND, XOR} CMOS gate types INVERTER, BUFFER NAND, XOR Technology node 65nm Process variations Nominal condition Vdd 1. Volt Temp 85 o C Library characterized.,.1,.,.3,.4, threshold points v.5,.6,.7,.8,.9,.95 TABLE I LIBRARY CHARACTERISTICS FOR SMALL TESTCASE RESULTS circuit topologies and the different CMOS gate types. The MVTM waveforms and arrival times closely follow the SPICE simulation results, while the voltage waveforms and arrival times obtained from the C eff technique become quite inaccurate for certain loading conditions. B. Large designs experimental setup The proposed technique has been employed on several large high-performance industrial designs, including two 65nm technology microprocessor designs, denoted here as Design 1 and Design. Table III presents important statistics for these two designs. Two separate timing runs have been performed on these designs: 1 using traditional C eff technique, using MVTM technique. The arrival times and 1 9% transition times at every timing endpoint of the design in each run have been stored in a file and compared with each other. The statistics of the differences between the two runs are presented in Table IV. Next, the maximum differences between arrival times and slews were identified and SPICE simulation has been run on these identified circuits. It has been observed that the LSE error of the voltage waveforms using MVTM technique is within % of SPICE run. In addition, the comparison of the C eff and MVTM runs in Table IV shows that C eff technique is generally more pessimistic compared the MVTM and SPICE results. Moreover, as shown in Table III, the static timing analysis runtime using the MVTM technique is, on average, 5% longer than the corresponding timing run using the C eff technique, while the additional memory required by MVTM is about %. The memory increase is due to the fact that in MVTM, piecewise linear waveforms are stored and propagated in the timing graph instead of just delay and slews in the C eff run.

6 Fig. 3. In this experiment, the CMOS gate under test is a NAND. The effective C n = ff, effective C f = 48fF, and effective R π=5ω. This experiment shows that MVTM follows SPICE, while the C eff technique incures about % error in gate delay and about 4% in slew calculation. SPICE vs. MVTM SPICE vs. C eff Min/Avg/Max gate -4% / % / 4% -3% / 1% / % propagation delay error Min/Avg/Max % / 5% / 7% -1% / 15% / 8% source slew error Avg/Max LSE error 1% / 4% 1% / 4% at source timing point Min/Avg/Max interconnect -% / 1% / 3% -4% / 11% / 17% propagation delay error Min/Avg/Max % / % / 3% -8% / 1% / 3% sink slew error Avg/Max LSE error 1% / 3% 8% / 33% at sink timing point TABLE II MINIMUM, AVERAGE, AND MAXIMUM ERROR PERCENTAGE BETWEEN SPICE/MVTM/C EFF Design Gates Nets Runtime Runtime Mem. Mem. C eff MVTM C eff MVTM 1 1.1M 1.4M 1s 16s 3.1GB 3.7GB.M.3M 335s 3395s 6.3GB 7.9GB TABLE III 65NM MICROPROCESSOR DESIGN SPECIFICATIONS Fig. 4. In this experiment, the CMOS gate under test is an XOR. The effective C n = 5fF, effective C f = 5fF, and effective R π=5ω. Again, this experiment confirm that MVTM follows SPICE even when the effective C n is equal to its effective C f, while C eff technique is highly inaccurate. Fig. 5. In this experiment, the CMOS gate under test is a BUFFER. The effective C n = 4fF, effective C f = ff, and effective R π=3ω. To confirm the stability of MVTM for all different load topologies, the load is chosen such that its effective C n is greater than its effective C f. VI. CONCLUSION The paper introduced a novel timing analysis method of the driver gate and interconnect circuit. The analysis operates on logic gates described as Multiple Voltage Threshold Models MVTM, and a interconnect circuit driving point admittance described in pole/residue form. MVTMs are a formal category of model characterization techniques which include and generalize the existing industry standards. The analysis technique relies solely on the raw MVTM characterization data and does not require the explicit instantiation of controlled current Des- Compare No. of No. of Max Min Avg. ign type points diff. diff. diff. diff. 1 Arrival time..45 M.99 M 31.6ps 1.1ps.6ps Slew.45 M 1.9 M 1.4ps.5ps 5.3ps Arrival time M 1.3 M 45.3ps.8ps 3.1ps Slew 3.54 M 1.95 M TABLE IV 14.5ps.3ps 5.4ps STATISTICS OF THE DIFFERENCE BETWEEN MVTM RUN VS. C EFF RUN source models and, therefore, is more general, accurate, efficient. The experimental results presented in the paper confirm that the technique is as efficient as the traditional analysis based on Thevenin type models, while producing waveforms that are within 3% of Spice-level circuit simulation REFERENCES 1] Composite Current Source Model CCS - Synopsys web resource. faq.html. ] Effective Current Source Model ECSM - Cadence web resource. 3] R. Brent. An algorithm with guaranteed convergence for finding a zero of a function. The Computer Journal, 14:4 45, ] J. F. Croix and D. F. Wong. Blade and razor: cell and interconnect delay analysis using current based models. In Proceeding of ACM/IEEE Design Automation Conference, pages , 3. 5] W. C. Elmore. The transient response of damped linear networks with particular regard to wideband amplifiers. Journal of Applied Physics, 19:55 63, ] M. Hashimoto, Y. Yamada, and H. Onodera. Equivalent waveform propagation for static timing analysis. In Proceeding of IEEE International Conference on Computer Aided Design, pages , 3. 7] I. Keller, K. Tseng, and N. Verghese. A robust cell-level crosstalk delay change analysis. In Proceeding of IEEE International Conference on Computer Aided Design, pages , 4. 8] R. Macys and S. McCormick. A new algorithm for computing the effective capacitance in deep sub-micron circuits. In Proceeding of the IEEE Custom Integrated Circuits Conference, pages , ] J. Qian, S. Pullela, and L. T. Pillage. Modeling the effective capacitance for the RC interconnect of CMOS gates. IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 13: , ] S.Abbaspour and M. Pedram. Calculating the effective capacitance for the RC interconnect in VDSM technologies. In Proceeding of Asia and South Pacific Design Automation Conference, pages 43 48, 3.