Signal-Path Driven Partition and Placement for Analog Circuit. Di Long, Xianlong Hong, Sheqin Dong EDA Lab, Tsinghua University

Transcription

1 Signal-Path Driven Partition and Placement for Analog Circuit Di Long, Xianlong Hong, Sheqin Dong EDA Lab, Tsinghua University

2 Agenda Research Background Overview of the analog placement researches Signal-Path Driven Analog Circuit Partition Algorithm of Core-Circuit Placement Algorithm of Bias-Circuit Placement Experiment and Conclusion

3 Research Background SOC integrates all of the circuits on one chip Analog circuits design is still a manual process The fast changes of demands in ASIC market

4 Agenda Research Background Overview of the analog placement researches Signal-Path Driven Analog Circuit Partition Algorithm of Core-Circuit Placement Algorithm of Bias-Circuit Placement Experiment and Conclusion

5 Researches about the analog placement automation The constructive placement techniques M. Kayal--SALIM Iteratively combining min-cut partitioning and force-directed placement E. Malavasi--Quick placement with geometric constraints simulated annealing and genetic algorithms ILAC, KOAN/ANAGRAM II, PUPPY-A, LAYLA Topological representations (BSG, SP, CBL), which still adopts the optimization engines of SA or GA and implement symmetry constraints

6 Agenda Research Background Overview of the analog placement researches Signal-Path Driven Analog Circuit Partition Algorithm of Core-Circuit Placement Algorithm of Bias-Circuit Placement Experiment and Conclusion

7 Observations of the Methodology hierarchical design for analog circuit structural feature of circuit based on signal-path requirements of matching/symmetry constraint and the reduction of parasitics

8 The methodology of hierarchical design and layout Whole analog circuit Functional circuit 1 Functional circuit i Functional circuit n Core circuit Bias circuit

9 Necessary Definition (1) core-circuit,, which is the main circuit in each unit-functional circuit, is responsible for transporting and processing analog signal. bias-circuit is responsible for providing bias voltages and bias currents for some MOS transistors in core-circuit.

10 Necessary Definition (2) power-earth transistor chain is a chain composed of transistors satisfying the following conditions The source/drain of each transistor in the chain must be connected to the power net or the earth net or the source/drain of another transistor in the same chain. There is one and only one transistor in the chain, source/drain of which is connected to the power net and there is one and only one transistor in the chain, source/drain of which is connected to the earth net.

11 Necessary Definition (3) signal-path is a special type of power-earth transistor chain, the generation algorithm of which is listed as follows: Ι: set of signal input nets Γ pec : set of all pecs { } Mj = g, s, d : set of transistor's gate net, source net and drain net j j j { Mj Mj I φ } Φ = Ι ケ : set of initial input transistors { pec pec I φ } Ψ 0 = i i Φ ケ : initial set of signal-paths can be defined

12 Necessary Definition (4) A loop procedure to generate the set of signal-paths Ψ = Ψ U Ψ U Ψ n+ 1 n sd g n n n n { pec ( pec ホ ) ル ( pec ホ ) pec I pec ケ φ } Ψ = Γ Ψ Ψ sd i i pec n n i Ψ g = i Γ pec Ψ n Ψ n peci ( Mj ホ pec ) ( Mh ホ pec ) s = g レ d = g ( pec ホ ) ル ( pec ホ ) i h j h j The stop condition of the above loop procedure Ψ = φ ル Ψ = sd n g n φ

13 Comments on the sets Ψ sd n : the current of pec in the set is controlled by the source/drain i current of pec, which is the direct front-stage of pec i Ψ g n : the current of pec in the set is controlled by the source/drain i voltage of pec, which is the direct front-stage of pec i Ψ is core-circuit and Γ Ψ n pec n is bias-circuit

14 Example for signal-path generation (1) Schematics of full-differential Miller-compensated two-stage amplifier and the diagram of all pecs pec3 pec4 { 1, 2,..., 6} and {, } { M M } { pec pec } Γ pec = pec pec pec Ι = VIP VIN so Φ = 1, 2 and Ψ =, { 3 4} g φ U { pec pec pec pec } when n = 0, Ψ = pec, pec and Ψ = sd 0 0 So Ψ = Ψ U Ψ Ψ =,,, 1 0 sd g pec 1 pec 2 pec 5 pec 6 when n = 1, Ψ = φ and Ψ = pec, pec sd g { 5 6 } { pec pec pec pec pec pec } So Ψ = Ψ U Ψ U Ψ =,,,,, 2 1 sd g when n = 2, Ψ = φ and Ψ = φ, stop sd g 2 2

15 Agenda Research Background Overview of the analog placement researches Signal-Path Driven Analog Circuit Partition Algorithm of Core-Circuit Placement Algorithm of Bias-Circuit Placement Experiment and Conclusion

16 Inner placement of each signal-path the same signal-path has the sequential drain/source connection relationship Signal is transported in the form of drain/source current the metals used to connect drain/source are required very short Layout all the MOS transistors from left to right according to the connection sequence from the power net to earth net

17 whole placement of the core-circuit Consideration: metals used to connect the nets among signal-paths are to transport the voltage, so these metals are not required very short 0 { pec pec } assuming Ψ =,..., n 0 0 n 1 n 1 1 Ψ, Ψ, Ψ,..., Ψ, Ψ is arranged by generation sequence sd g sd g core-circuit is full-symmetrical structure j { } { } Ψ is divided into Ψ S = pec,..., pec and Ψ M = pec,..., pec n n 1 j / 2 n 1 + j / 2 j core-circuit is not full-symmetrical structure part but not all of transistors in pec i have symmetry constraints with others in pec j

18 Objectives of the core-circuit placement minimizing the differences of the height of all MOS transistor layouts in the same signal-path; minimizing the differences of the width of all signal-paths in the core-circuit; minimizing the total capacitance parasitics of all the MOS transistors; maximizing the area utility.

19 Transistor s variants for objectives implementation poly gate source drain W エ F = W エ F m m n n

20 Cost function to be optimized ( ) (, ) ( 1 ) CP = α H + β W + γ P + δ U core max_ diff max_ diff cap area ( ) ( ) H = max 鴿 max height M height M k n k, i k, j k max_ diff k, i k, j pec ホ Ψ M, M ホ pec ( ) ( ) W = max width pec width pec max_ diff i j pec, pec ホ Ψ n h i i j n P = C F U cap jbst i j i = 1 j = 1 area = 裹 ( ) ( ) ( ) i= 1 j = 1 ( i, j ) height M エ ( i, j ) width M l l 1 鴿 max 鴿 width pec max height M RSS pec, pec ( i ) エ裹鴿 ( i, j ) + ( i i + 1 ) peci ホ Ψ n M 1 i, j ホ pec i = i i = 1 height M = W F + 2δ h i i, j i, j i, j head l 裹 h i h i 1 鴿 width ( pec ) = 裹 F L + ( F + 1 ) δ + RSM M, M ( ) ( + ) i i, j i, j i, j gap i, j i, j 1 j = 1 j = 1

21 Calculation of distance between transistors M i, j ( i, j, i, j 1 ) RSM M M + (, ) RSS peci pec i + 1 δ gap height ( M ) M i, j + 1 δ head width ( M )

22 Calculation of source/drain bulk capacitance C j AC PC 踐 V 踐 ω V = +, let α = 1 and β = 1 j jsω 踐 V 踐銷 j BS V φ 銷 φ BS 顏顏 1 1 銷 φ 銷顏 j 顏 φ j j js BS BS jsbt m m j m m jsω ( ) = ( α + α δ + 2β δ ) + 2β ( + δ ) + ( α δ + 2β ) C F WL W L W F W jsbt gap gap gap gap 1 F

23 Agenda Research Background Overview of the analog placement researches Signal-Path Driven Analog Circuit Partition Algorithm of Core-Circuit Placement Algorithm of Bias-Circuit Placement Experiment and Conclusion

24 Objectives of the bias-circuit placement minimizing the total parasitic capacitance of all the MOS transistors belonging to the bias-circuit; minimizing the total length of routing metals; maximizing the area utility. CP = ω P + θ L + λ 1 U ( ) bias cap routing area

25 Agenda Research Background Overview of the analog placement researches Signal-Path Driven Analog Circuit Partition Algorithm of Core-Circuit Placement Algorithm of Bias-Circuit Placement Experiment and Conclusion

26 Case 1 pec3 pec4 pec 6 pec 1 pec 2 pec 5

27 Case 2 pec 2 pec3 pec4 pec 1 pec5 pec6

28 Case 3 pec 6 pec 9 pec 1 pec 2 pec 4 pec 7 pec 8 pec 12 pec 3 pec 10 pec 11 pec 5

29 Conclusions a new methodology of signal-path driven partition and placement for analog the thinking of hierarchical design structural feature of analog circuit based on signal-path variants of MOS transistors. Layout is compact with high performance and it is universal and effective.

30 Thank you