ECE 497 JS Lecture - 11 Modeling Devices for SI

Transcription

1 ECE 497 JS Lecture 11 Modeling Devices for SI Spring 2004 Jose E. SchuttAine Electrical & Computer Engineering University of Illinois 1

2 Announcements Thursday Feb 26 th NO CLASS Tuesday March 2 nd Speaer: Carl Werner Rambus Inc., Los Altos, CA 2

3 Motivations Z o Z o C Loads are nonlinear Need to model reactive elements in the time domain Generalize to nonlinear reactive elements 3

4 TimeDomain Model for Linear Capacitor For linear capacitor C with voltage v and current i which must satisfy i = dv C dt Using the bacward Euler scheme, we discretize time and voltage variables and obtain at time t = nh v = v hv ' n 1 n n 1 4

5 TimeDomain Model for Linear Capacitor After substitution, we obtain v' = n 1 i C n 1 so that n 1 vn 1 = vn h C i The solution for the current at tn1 is, therefore, C C i v v h h n 1 = n 1 n 5

6 TimeDomain Model for Linear Capacitor i v C i n1 i n1 v n1 R=h/C v n C/h v n1 R=h/(2C) v n 2C/hi n Bacward Euler companion model at t=nh Trapezoidal companion model at t=nh 6

7 Step response comparisons Vo (volts) 0.2 Exact Bacward Euler Trapezoidal Time (ns) 7

8 TimeDomain Model for Linear Inductor v = di L dt Bacward Euler i i hi i = n 1 v L n 1 L L v = i i h h n 1 n 1 n : n 1 = n n 1 V i L V n1 i n1 R= L h L h i n 8

9 TimeDomain Model for Linear Inductor If trapezoidal method is applied h i = i i i 2 [ ] n 1 n n 1 n 2L 2L v = i v h h n 1 n 1 n V i L i n1 V n1 R= 2L h 2L h i n V n 9

10 NewtonRaphson Method Problem: Wish to solve for f(x)=0 Use fixed point iteration method: Define F( x) = x K( x) f ( x) I : x = F( x ) = x K( x ) f( x ) With Newton Raphson: df = = K( x) [ f ( x)] 1 therefore, I : x = x [ f ( x )] f( x ) 1 dx 10

11 NEWTONRAPHSON ALGORITHM (graphical interpretation) f(x) f(x 1 ) P f(x ) P 1 slope Q x 1 x x 11

12 NewtonRaphson Algorithm ( ) 1 : 1 N R x = x A f x Ax 1 = Ax f( x) S. x 1 is the solution of a linear system of equations. A x = S LU fact Forward and bacward substitution. A is the nodal matrix for N S is the rhs source vector for N. 12

13 NR Algorithm voltage controlled current controlled } } 0. 0, gives V0, i0 1. Find V, i compute companion mod els. G {,,, I R E Obtain A, S. 3. Solve A x = S. V c C c 4. x 1 Solution 5. Chec for convergence x 1 x < ε. If they converge, then stop. 6. 1, and go to step1. 13

14 Application to Diode Circuit R E V I I diode I* load line V* V V E f V I e R V / V ( ) = ( t s 1) 14

15 NR Diode It is obvious from the circuit that the solution must satisfy f(v) = 0 We also have 1 Is V / Vt f '( V) = e R Vt The Newton method relates the solution at the (1)th step to the solution at the th step by f( V ) V 1 = V f '( V ) V 1 = V V E I s R 1 Is e R V t V / V ( e t 1) V / V t 15

16 NewtonRaphson (cont ) After manipulation we obtain 1 R E g V = J R 1 g = I V s t e V / V t J I e V g V / Vt = s( 1) 16

17 NewtonRaphson for Diode NewtonRaphson representation of diode circuit at th iteration R i 1 E v 1 g J g = I V s t e V / V t J I e V g / ( V Vt = s 1) 17

18 Current Controlled i V V R Companion E i I R = dh() i di = i i E = h( i ) R i 18

19 For a General Networ Let x = vector variables in the networ to be solved for. Let f(x) = 0 be the networ equations. Let x be the present iterate, and define A = f ( x ) Jacobian of f at x = x Let N be the linear networ where each nonlinear resistor is replaced by its companion model computed from x. j j i j V j I = g ( V ) j j j 19

20 General Networ V = P P j j j Companion model j j G I I V V G = dg( V ) dv = V V [ ] I = g V GV 20

21 Nonlinear Reactive Elements: i n1 i n1 V C(v) V q(v) n1 h J n V n1 g J J n dq q= f() v, i = dt qn 1 = qn h dt t= tn dq 1 qn 1 qn f( vn 1) or, in 1 = in 1( vn 1) = h h h 21

22 General Element I I=f(V) I slope= g V V J I i 1 v I=f(V) v 1 g J 22

23 Bipolar Transistor C B E C V bc C bc α f I de B I dc I B I C I de I E V be C be α r I dc E 23

24 TTL Gate V cc V cc R 1 R 2 R 3 R 3 Q2 R 1 Q 3 R 2 Vin Q 6 Q 1 R E V out Q4 Vin R E I out V out R 4 R 5 R 4 R 5 Q 5 24

25 IV Curves for TTL Gate 200 AS04 TT L 100 I out (ma) Vin=0.8V Vin=1.4V Vin=1.6V Vin=1.8V V out 25

26 IBIS Introduction I/O Buffer Information Specification is a Behavioral method of modeling I/O buffers based on IV curve data obtained from measurements or circuit simulation. The IBIS format is standardized and can be parsed to create the equivalent circuit information needed to represent the behavior of an IC. Can be integrated within a circuit simulator using an IBIS translator.

27 Advantages of IBIS Protection of proprietary information Adequate for signal integrity simulation Models are free from vendors Faster simulations (with acceptable accuracy) Standardized topology

28 IBIS Diagram Power Clamp Input Pacage Enable Pacage GND Clamp Power Clamp Threshold & Enable Logic Pullup Ramp Pulldown Ramp Pullup V/I Pulldown V/I Power Clamp GND Clamp Output Pacage GND Clamp 28

29 IBIS Input Topology Vcc R_pg L_pg Power_Clamp C_pg GND_Clamp C_comp GND GND

30 IBIS Output Topology V cc V cc R_pg C_omp L_pg C_pg Pullup Pulldown Ramp Power_Clamp GND_Clamp GND GND 30

31 IBIS Model Generation Create an IBIS model from either simulation or empirical data Model from Empirical data? No Get SPICE I/O info Yes Collect Data Data in IBIS text file Run SPICE to IBIS Translator Run IBIS Parser No Parser Pass Yes Run model on Simulator No Model validated? Yes Adopt model 31

32 IBIS for Signal Integrity Crosstal Ringing, Overshoot, undershoot Distortion, Nonlinear effects Reflections issues Line termination analysis Topology scheme analysis Visit